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2011-12-19	Sebastien Bourdeauducq	README: Flow	commit \| commitdiff \| tree
2011-12-19	Sebastien Bourdeauducq	README: Core Logic, Bus, Bank	commit \| commitdiff \| tree
2011-12-19	Sebastien Bourdeauducq	README: structure + FHDL description	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	examples: remove old-style declarations	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	corelogic: fix signal exports	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	fhdl: better matching of assignment	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	Remove uses of declare_signal	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	fhdl: also take into account object attributes in _make_sign...	commit \| commitdiff \| tree
2011-12-18	Sebastien Bourdeauducq	fhdl: automatic signal name from assignment	commit \| commitdiff \| tree
2011-12-17	Sebastien Bourdeauducq	bank: support raw registers	commit \| commitdiff \| tree
2011-12-17	Sebastien Bourdeauducq	fhdl: fix series of if/elif/else	commit \| commitdiff \| tree
2011-12-17	Sebastien Bourdeauducq	32-device, 8-bit CSR bus	commit \| commitdiff \| tree
2011-12-17	Sebastien Bourdeauducq	verilog: get the simulator to run the combinatorial...	commit \| commitdiff \| tree
2011-12-17	Sebastien Bourdeauducq	verilog: support for float parameters in instances	commit \| commitdiff \| tree
2011-12-16	Sebastien Bourdeauducq	verilog: user-definable reset and clock	commit \| commitdiff \| tree
2011-12-16	Sebastien Bourdeauducq	fhdl: simpler syntax	commit \| commitdiff \| tree
2011-12-16	Sebastien Bourdeauducq	Pay a bit more attention to PEP8	commit \| commitdiff \| tree
2011-12-13	Sebastien Bourdeauducq	wishbone2csr: wait for WB deack	commit \| commitdiff \| tree
2011-12-13	Sebastien Bourdeauducq	timeline: only trigger in rest state	commit \| commitdiff \| tree
2011-12-13	Sebastien Bourdeauducq	examples: Wishbone interconnect test bench	commit \| commitdiff \| tree
2011-12-13	Sebastien Bourdeauducq	verilog: use blocking assignment in combinatorial process	commit \| commitdiff \| tree
2011-12-13	Sebastien Bourdeauducq	wishbone: decoder: fix slave cyc generation in registered...	commit \| commitdiff \| tree
2011-12-12	Sebastien Bourdeauducq	wishbone2csr: fix double-write bug	commit \| commitdiff \| tree
2011-12-12	Sebastien Bourdeauducq	wishbone: only send ack to the active master in arbiter	commit \| commitdiff \| tree
2011-12-12	Sebastien Bourdeauducq	fhdl: allow a namespace to be specified for Verilog...	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	fhdl: support Constant parameters for Verilog conversion	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	fhdl: fix list references (thanks Lars)	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bus: fix CSR interconnect data readback	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bus: 14-bit CSR addresses	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bank: fix csrgen address decoder	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	bus: Wishbone to CSR bridge	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	corelogic: timeline module	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	fhdl: remove broken fragment iadd	commit \| commitdiff \| tree
2011-12-11	Sebastien Bourdeauducq	convtools: insert reset on variables	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	autofragment: remove debug	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: autofragment	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: fix += for empty fragment	commit \| commitdiff \| tree
2011-12-10	Sebastien Bourdeauducq	fhdl: pad support in fragments	commit \| commitdiff \| tree
2011-12-09	Sebastien Bourdeauducq	wishbone: decoder + shared bus interconnect	commit \| commitdiff \| tree
2011-12-09	Sebastien Bourdeauducq	fhdl: replication support	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	wishbone: arbiter	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	simplebus: export GetSigName function	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: multimux module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	verilog: handle default in case statements	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	fhdl: improve automatic signal naming	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Corelogic conversion example	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: MC divider module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	fhdl: support negation operator	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	verilog: fix unary operator conversion	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	corelogic: round-robin module	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Named buses	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	wishbone: add missing SEL	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	instances: signal override	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Wishbone declarations	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Simple bus base class	commit \| commitdiff \| tree
2011-12-08	Sebastien Bourdeauducq	Instance support	commit \| commitdiff \| tree
2011-12-07	Sebastien Bourdeauducq	fhdl: fix implicit slice index	commit \| commitdiff \| tree
2011-12-07	Sebastien Bourdeauducq	fhdl: cleanup value bv	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Variable conversion	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Cleanup	commit \| commitdiff \| tree
2011-12-05	Sebastien Bourdeauducq	Case support + register bank generator	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	CSR bus definitions	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Examples folder	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Reset insertion	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Verilog generator	commit \| commitdiff \| tree
2011-12-04	Sebastien Bourdeauducq	Initial import, FHDL basic structure, divider example	commit \| commitdiff \| tree

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