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add another bad hack in parser.py which identifies "undefined" slice assignment
2020-06-13
Cesar Strauss
Wait for all active rel signals to be high, and only...
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2020-06-09
Cesar Strauss
Keep the sequencer in the "done" state until ready_i...
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2020-06-09
Cesar Strauss
Avoid a combinatorial loop on valid_o
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2020-06-07
Cesar Strauss
Assign the one-clock delay operation from ADD to SHR
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2020-06-07
Cesar Strauss
Try responding with ready_i on the same cycle as valid_o
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2020-06-07
Cesar Strauss
Assert valid_o one clock early, as alu_done is asserted
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2020-06-07
Cesar Strauss
Make the test ALU conform to the valid/ready protocol
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2020-06-03
Cesar Strauss
Check completion of the sub-processes
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2020-06-03
Cesar Strauss
Simplify immediate check
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2020-06-03
Cesar Strauss
Preliminary check of the alu protocol
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2020-06-03
Cesar Strauss
Pass along the operand, in the cycle in which go is...
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2020-06-02
Cesar Strauss
Allow at least one operand to be fetched
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2020-06-02
Cesar Strauss
Hold rdmaskn active during the busy_o cycle
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2020-06-01
Cesar Strauss
Add rdmaskn parameter and assert it along issue_i
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2020-05-29
Cesar Strauss
Allow immediate assertion of go in the same cycle as rel
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2020-05-29
Cesar Strauss
Correct typo
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2020-05-29
Cesar Strauss
Send a one-clock "go" pulse after a configurable number...
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2020-05-28
Cesar Strauss
Check that rd rises after issue_i, unless it's immediate
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2020-05-28
Cesar Strauss
Store and present parameters together with issue_i
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2020-05-27
Cesar Strauss
Move test case parameters to an "operation" member...
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2020-05-27
Cesar Strauss
Remove the monitor process
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2020-05-25
Cesar Strauss
Check that busy_o doesn't rise on its own
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2020-05-25
Cesar Strauss
Implement the issue_i/busy_o protocol check.
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2020-05-25
Cesar Strauss
Move process list to CompUnitParallelTest
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2020-05-25
Cesar Strauss
Fix detection of busy_o inside the monitor process
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2020-05-25
Cesar Strauss
Proof of concept of a parallel test
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2020-05-25
Cesar Strauss
Show oper_r and oper_i in the signal list, in simulation
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2020-05-24
Cesar Strauss
Avoid overwriting the first vcd file with the second one
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2020-05-24
Cesar Strauss
Rename the internal DFF of latchregisters to avoid...
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2020-05-23
Cesar Strauss
Add a few test cases with zero_a set, in combination...
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2020-05-23
Cesar Strauss
Allow zero_a to be set when simulating an operation
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2020-05-23
Cesar Strauss
Choose between RA (src1) and zero immediate, conditioned...
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2020-05-21
Cesar Strauss
Fixed typo and left-over from refactoring
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