soc.git
2020-08-30 Luke Kenneth... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-30 Luke Kenneth... working on dcache.py
2020-08-30 Luke Kenneth... tidyup on mul proof
2020-08-30 Luke Kenneth... set mul post_stage o.ok only when needed, and fix xer_s...
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-30 Cole Poiriericache.py commit progress, about a third through the...
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza...
2020-08-29 Cole Poiriermem_types add more types from common.vhdl specifially...
2020-08-29 Cole Poiriermem_types.py arrange in alphabetical order for ease...
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!
2020-08-29 Cole Poiriermmu.py remove duplicate comment left over from mmu...
2020-08-29 Cole Poiriericache.py initial commit of first attempt at translatio...
2020-08-29 Cesar StraussMove new write_gtkw and its example to nmutil
2020-08-29 Luke Kenneth... minor code-shuffle, comments
2020-08-29 Luke Kenneth... slowly morphing towards using an XER bit-field selector...
2020-08-29 Samuel A. Falvo IIMUL pipeline formal proofs complete, I *think*.
2020-08-29 Luke Kenneth... break down XER into flags
2020-08-29 Luke Kenneth... add XER read via DMI interface to sim.py
2020-08-29 Luke Kenneth... add hack to get at XER through DMI interface
2020-08-29 Luke Kenneth... submodule update
2020-08-29 Samuel A. Falvo IIWIP: prep for 64-bit insns
2020-08-29 Luke Kenneth... yep disable OE for MULH64/32 and EXTS and CNTZ
2020-08-29 Luke Kenneth... investigating CR mtocrf / mfocrf
2020-08-29 Luke Kenneth... add additional CR regression tests
2020-08-29 Luke Kenneth... allow pseudocode numbering to decrement in for-loops
2020-08-29 Luke Kenneth... add wat to write out raw binary assembled programs
2020-08-29 Luke Kenneth... CR FXM becomes a full mask.
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb...
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu...
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Cole Poirierdcache.py implement the remaining vhdl generate stateme...
2020-08-27 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=476
2020-08-27 Luke Kenneth... xer so is not being passed through to CR0
2020-08-27 Luke Kenneth... really bad hack to fix simulator bug in carry handling
2020-08-27 Luke Kenneth... augment addme test case to show bug #476
2020-08-27 Luke Kenneth... add addze and addme uni tests
2020-08-27 Luke Kenneth... incompatibility with POWER9 on mulhw/u due to lack...
2020-08-27 Luke Kenneth... overflow-enable does not occur on shift operations
2020-08-27 Luke Kenneth... oink, write_cr shiftrot record width was zero (??)
2020-08-27 Luke Kenneth... sorting out shift_rot to use new output stage data...
2020-08-27 Luke Kenneth... need to read SO if Rc=1
2020-08-27 Luke Kenneth... reorg of SO handling related to CR0
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with...
2020-08-26 Luke Kenneth... use sub-test in logical test_pipe_caller
2020-08-26 Luke Kenneth... investigating div fsm and simulator bug
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions...
2020-08-25 Jacob Lifshayfix broken remainder for div FSM
2020-08-25 Jacob Lifshayclean up formatting
2020-08-25 Luke Kenneth... although shift-rot does not alter XER.so it still needs...
2020-08-25 Luke Kenneth... add way to capture CR from DMI in litex sim
2020-08-25 Luke Kenneth... add CR read to DMI interface
2020-08-25 Luke Kenneth... shorten using temp vars
2020-08-25 Luke Kenneth... add CR DMI interface
2020-08-25 Luke Kenneth... add crxor unit test to qemu
2020-08-25 Cole Poirierdcache.py fix whitespace, fomatting, syntax
2020-08-25 Cole Poirierdcache.py fix formatting
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top...
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file
2020-08-24 Luke Kenneth... argh, reading regfile over DMI was overlapped and corru...
2020-08-24 Luke Kenneth... add isel CR tests to run on qemu (confirmed working)
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup
2020-08-24 Luke Kenneth... make it easier to select FSM/Pipe DIV unit
2020-08-24 Luke Kenneth... fix *another* ld-update-related timing / FSM issue
2020-08-24 Luke Kenneth... tidyup / shuffle after review
2020-08-24 Luke Kenneth... remove default parameter
2020-08-24 Luke Kenneth... "WAY" does not exist - range(NUM_WAYS) was intended
2020-08-24 Luke Kenneth... use WAY_BITS in appropriate locations
2020-08-24 Luke Kenneth... reminder that the license (reflecting what is in setup...
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about...
2020-08-23 Luke Kenneth... update copyright notices to include additional primary...
2020-08-23 Luke Kenneth... add load algebraic immediate unit test
2020-08-23 Luke Kenneth... add algebraic ld tests lwax, lwaux
2020-08-23 Michael NolanAdd copyright to files I primarily authored in simulator/
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py
2020-08-23 Luke Kenneth... bring "core stopped" signal out through DMI interface
2020-08-23 Luke Kenneth... add in DMI "stat" loop which monitors core "stopping"
2020-08-23 Cesar StraussAllow an empty style, and passing default styles as...
2020-08-23 Cesar StraussAdd comment node type
2020-08-23 Cesar StraussAdd base and display styles
2020-08-23 Cesar StraussApply style from node own name
2020-08-23 Cesar StraussAdd color style
2020-08-23 Cesar StraussCollect styles from the tuple
2020-08-23 Cesar StraussPropagate the root style to all signals
2020-08-23 Luke Kenneth... comment why litex sim mem map is altered
2020-08-23 Luke Kenneth... multiply does not have invert_in, zero_a or invert_out
2020-08-22 Luke Kenneth... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth... update submodule
2020-08-22 Luke Kenneth... load bios not 1.bin unit test
2020-08-22 Luke Kenneth... add extra div regression tests
2020-08-22 Cesar StraussMove comments to the docstring
2020-08-22 Cesar StraussWalk the DOM and emit the trace names
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