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soc.git
2020-05-24
Luke Kenneth...
error in alu output stage formal proof setup
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2020-05-24
Luke Kenneth...
output registers need to be Data type (consistently)
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2020-05-24
Luke Kenneth...
spelling mistake in variable
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2020-05-24
Luke Kenneth...
TODO mention OP_MTMSR/OP_MFMSR
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2020-05-24
Luke Kenneth...
add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
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2020-05-24
Luke Kenneth...
move docstring to wiki for compunit
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2020-05-23
colepoirier
Added branch and shift_rot imports to fu/compunits...
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2020-05-23
Cesar Strauss
Add a few test cases with zero_a set, in combination...
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2020-05-23
Cesar Strauss
Allow zero_a to be set when simulating an operation
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2020-05-23
Luke Kenneth...
add input / output stage missing modules
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2020-05-23
Luke Kenneth...
common function for op zero and op immed
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2020-05-23
Cesar Strauss
Choose between RA (src1) and zero immediate, conditione...
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2020-05-23
Luke Kenneth...
update docs on compunits
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2020-05-23
Luke Kenneth...
remove extraneous test_isel
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2020-05-23
Luke Kenneth...
add comments
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2020-05-23
Luke Kenneth...
document purpose of regspec module
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2020-05-23
Luke Kenneth...
split out RegSpecs into separate module
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2020-05-23
Luke Kenneth...
add TODO on multi-in multi-out Function Units
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2020-05-23
Luke Kenneth...
split out RegSpec API into separate class (TODO: move...
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2020-05-23
Luke Kenneth...
add notes on FunctionUnit API
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2020-05-23
Luke Kenneth...
make MultiCompUnit and testing ALU use regspec API...
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2020-05-23
Luke Kenneth...
remove unneeded imports
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2020-05-23
Luke Kenneth...
make demo/test ALU look like nmigen pipeline API
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2020-05-23
Luke Kenneth...
add stub DataMerger class
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2020-05-23
Luke Kenneth...
add link to regspecs on wiki
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2020-05-23
Luke Kenneth...
add regspec capability to MultiCompUnit
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2020-05-23
Michael Nolan
Modify proof of isel to use full CR register
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2020-05-23
Michael Nolan
Add test_isel
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2020-05-23
Luke Kenneth...
make immediate-or-RA selection optional based on awaren...
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2020-05-23
Luke Kenneth...
start to morph MultiCompUnit to take "regspec" as the...
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2020-05-23
Luke Kenneth...
add CR_ISEL formal proof to CR pipeline
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2020-05-23
Luke Kenneth...
add CR_ISEL (and unit test) to CR pipeline
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2020-05-23
Luke Kenneth...
update to (corrected) csv files for CR_ISEL
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2020-05-23
Luke Kenneth...
select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
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2020-05-23
Luke Kenneth...
add gitignore
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2020-05-23
Luke Kenneth...
CR field on Br input data is specd as 0:3 range
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2020-05-23
Luke Kenneth...
add b to CR pipe input data, for isel
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2020-05-22
Luke Kenneth...
add TODO and link to SHIFT_ROT formal bugreport
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2020-05-22
Luke Kenneth...
remove xer.so from ShiftRot formal proof
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2020-05-22
Luke Kenneth...
remove sticky overflow from Shift Rot pipeline
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2020-05-22
Luke Kenneth...
test branch ctr ok flag
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2020-05-22
Luke Kenneth...
cleaner way to test link register ok
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2020-05-22
Luke Kenneth...
whitespace
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2020-05-22
Michael Nolan
Fix link handling in branch proof
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2020-05-22
Michael Nolan
Update to latest wiki version - fix cr0 input for OP_CNTZ
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2020-05-22
Luke Kenneth...
variable-name munging for branch formal
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2020-05-22
Michael Nolan
Add formal proof for branch unit, fix bug with bcreg
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2020-05-22
Luke Kenneth...
cleanup logical pipe formal proof
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2020-05-22
Luke Kenneth...
split out Logical Input and Output stages to common...
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2020-05-22
Luke Kenneth...
div probably uses ALU not Logical, needs double-checkin...
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2020-05-22
Luke Kenneth...
update comments for ALUCompUnit
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2020-05-22
Luke Kenneth...
soc.fu.logical.input_stage no different from ALU: delete
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2020-05-22
Luke Kenneth...
covert ALU FU to CommonInputStage
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2020-05-22
Luke Kenneth...
create common input pipe spec to avoid code-duplication
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2020-05-22
Luke Kenneth...
move CR over to CompCROpSubset
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2020-05-22
Michael Nolan
Convert branch unit to new CR interface
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2020-05-22
Michael Nolan
Complete CR proof
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2020-05-22
Luke Kenneth...
increase fu-fu test matrix size
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2020-05-22
Luke Kenneth...
remove unneeded code
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2020-05-22
Luke Kenneth...
rename ShiftRot to Mul in fu mul test
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2020-05-22
Luke Kenneth...
rename Logical to Div in fu div test
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2020-05-22
Luke Kenneth...
cookie-cut start on div pipe
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2020-05-22
Luke Kenneth...
add cookie-cut mul pipeline template
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2020-05-22
Luke Kenneth...
whitespace
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2020-05-22
Luke Kenneth...
over 80 chars
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2020-05-22
Luke Kenneth...
comment tidyup
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2020-05-22
Luke Kenneth...
use CompBROpSubset and reduce it down in size (remove...
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2020-05-22
Luke Kenneth...
code-shuffle
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2020-05-22
Luke Kenneth...
remove accidentally added branch input stage
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2020-05-22
Tobias Platen
fix ModuleNotFoundError
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2020-05-21
Luke Kenneth...
add fu logical_input_record.py
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2020-05-21
Luke Kenneth...
update CROutputData to use Data()
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2020-05-21
Luke Kenneth...
update comments
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2020-05-21
Luke Kenneth...
whitespace cleanup
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2020-05-21
Luke Kenneth...
whitespace cleanup
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2020-05-21
Luke Kenneth...
remove input_cr, output_cr and is_32bit from CompCROpSubset
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2020-05-21
Luke Kenneth...
add read_cr_whole and write_cr_whole to CompCROpSubset
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2020-05-21
Luke Kenneth...
add first cut at cr_input_record.py
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2020-05-21
Luke Kenneth...
move Logical over to use CompLogicalOpSubset
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2020-05-21
Michael Nolan
Partial attempt at proving the new cr unit.
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2020-05-21
Luke Kenneth...
argh syntax error
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2020-05-21
Luke Kenneth...
update and comment CR Input/Output Data specs
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2020-05-21
Michael Nolan
All CR tests now working
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2020-05-21
Luke Kenneth...
add CR out decoder debug
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2020-05-21
Michael Nolan
OP_CROP now working
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2020-05-21
Michael Nolan
Begin porting cr pipeline to new interface
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2020-05-21
Michael Nolan
Add third cr register select field to decoder
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2020-05-21
Michael Nolan
Update to latest wiki version
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2020-05-21
Luke Kenneth...
comment CompALUOpSubset, data_len is actually used...
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2020-05-21
Luke Kenneth...
comment DecodeCRIn and DecodeCROut, gratuitously
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2020-05-21
Luke Kenneth...
document subkls in CompUnitRecord
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2020-05-21
Luke Kenneth...
ARSE! frickin git submodules!
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2020-05-21
Luke Kenneth...
move CompLDSTOpSubset to fu.ldst.ldst_input_record
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2020-05-21
Michael Nolan
Fix broken unit tests in test_caller
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2020-05-21
Michael Nolan
Add cr output decoder to power_decoder2.py
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2020-05-21
Michael Nolan
Add CR In decoder to power_decoder2.py
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2020-05-21
Michael Nolan
Convert CR out to enum in power_decoder
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2020-05-21
Michael Nolan
Update to latest wiki version - convert CR out to enum
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2020-05-21
Michael Nolan
Convert CR In field to enum instead of single bit
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2020-05-21
Michael Nolan
Update to latest wiki version
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