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riscv-tests.git
2017-10-24
Tim Newsome
Increase dual-core RV64 timeouts.
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2017-10-19
Tim Newsome
Get helpful gdb output in MemTestBlock.
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2017-10-12
Tim Newsome
Pay attention to server_timeout_sec
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2017-10-04
Tim Newsome
Resurrect priv tests.
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2017-10-04
Tim Newsome
Merge pull request #79 from riscv/multigdb
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2017-09-29
Tim Newsome
Make ExamineTarget multi-core aware.
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2017-09-29
Tim Newsome
Fix tests to work in multi-gdb mode.
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2017-09-22
Tim Newsome
Remove unused function.
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2017-09-21
Tim Newsome
Add coverage for single-core non-rtos OpenOCD.
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2017-09-20
Tim Newsome
Allow multiple reset vectors.
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2017-09-19
Andrew Waterman
Link against libm for fma()
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2017-09-19
Tim Newsome
Merge pull request #76 from riscv/multicore
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2017-09-19
Tim Newsome
Forgot to commit this earlier.
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2017-09-18
Tim Newsome
Add interrupts to MulticoreRunHaltStepiTest.
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2017-09-15
Tim Newsome
Don't read entire log into RAM just to print it.
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2017-09-14
Tim Newsome
misa is stored in the hart now, not the target
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2017-09-14
Tim Newsome
When spike fails to launch, display its output.
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2017-09-14
Tim Newsome
Test debugging code with interrupts.
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2017-09-14
Tim Newsome
Call postMortem() when a test fails.
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2017-09-14
Tim Newsome
Clarify timeout units.
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2017-09-14
Andrew Waterman
Move link options to end of gcc command line
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2017-09-12
Tim Newsome
Merge pull request #69 from riscv/multicore
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2017-09-01
Andrew Waterman
Improve ma_fetch test to cover JAL and branches
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2017-09-01
Tim Newsome
Add some infrastructure for multicore tests.
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2017-09-01
Tim Newsome
Use 32-bit link script for 32-bit target.
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2017-08-28
Tim Newsome
This file isn't ready yet.
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2017-08-28
Tim Newsome
Forgot to add this file.
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2017-08-28
Tim Newsome
Increase remotetimeout for spike targets.
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2017-08-28
Tim Newsome
Fix rebase bug.
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2017-08-28
Tim Newsome
Make MemTestBlock output a more descriptive error.
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2017-08-28
Tim Newsome
Fix MemTest* after sloppy rebase.
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2017-08-28
Tim Newsome
Rename test to MulticoreRunHaltStepiTest.
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2017-08-28
Tim Newsome
Make pylint happy.
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2017-08-28
Tim Newsome
WIP multicore testing.
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2017-08-28
Tim Newsome
WIP towards multiple gdb instances.
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2017-08-28
Tim Newsome
Make the debug tests aware of multicore.
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2017-08-28
Tim Newsome
Increase delay in UserInterrupt.
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2017-08-16
Palmer Dabbelt
Merge pull request #67 from riscv/sfence_vma
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2017-08-16
Palmer Dabbelt
Inform GCC that "sfence.vma" clobbers memory
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2017-08-14
Tim Newsome
Put logfile code back so everything works again.
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2017-08-14
Megan Wachs
Merge pull request #66 from riscv/debug_user_niceness
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2017-08-14
Megan Wachs
debug: clean up Temporary Log File messages
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2017-08-14
Megan Wachs
debug: Avoid None type error
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2017-08-14
Megan Wachs
debug: Revert change to print backtrace, as that is...
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2017-08-14
Megan Wachs
debug: Allow OpenOCD startup timeout to be specified...
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2017-08-14
Megan Wachs
When a test fails with exception, actually print out...
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2017-08-13
Tim Newsome
Make MemTest* catch reading too many words.
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2017-08-11
Tim Newsome
Show the OpenOCD log in all(?) failure cases.
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2017-08-11
Tim Newsome
Print out name of logfile when debug test is run.
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2017-08-11
Tim Newsome
When make fails to run a test, print out the log.
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2017-08-11
Tim Newsome
Don't use `set pipefail` which is a bashism.
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2017-08-11
Tim Newsome
Don't eat errors in debug Makefile.
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2017-08-10
Tim Newsome
Don't run debug tests as part of build.
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2017-08-10
Tim Newsome
Pylint target files as well.
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2017-08-10
Tim Newsome
Give these sim targets a chance of passing.
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2017-08-08
Palmer Dabbelt
Merge pull request #62 from richardxia/only-emit-f...
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2017-08-07
Richard Xia
rv64[ms]i-csr: Only emit F instructions when compiled...
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2017-08-04
Andrew Waterman
RV32 div tests should use -2^31 for min value, not...
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2017-08-04
Andrew Waterman
Improve RVC test
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2017-07-31
Tim Newsome
Fix the end of MulticoreTest.
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2017-07-27
Tim Newsome
Make pylint happy.
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2017-07-26
Tim Newsome
Use new OpenOCD messages to determine gdb port.
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2017-07-21
Tim Newsome
Only clean up logfiles that we know we created.
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2017-07-21
Tim Newsome
Add back code to clean up triggers in entry.S
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2017-07-18
Tim Newsome
Check all PCs after reset.
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2017-07-13
Tim Newsome
Print out logs in more failure cases.
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2017-07-06
Tim Newsome
Merge pull request #58 from riscv/fpga_reset_halt
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2017-07-06
mwachs5
debug: Make the 'out of reset' tests actually apply...
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2017-07-03
Tim Newsome
Add gdb_setup to target for arbitrary gdb commands
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2017-07-03
Tim Newsome
Don't clear triggers during execution.
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2017-06-27
Tim Newsome
Tolerate missing misa register.
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2017-06-27
Tim Newsome
Merge pull request #55 from riscv/debug
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2017-06-27
Tim Newsome
Merge pull request #56 from riscv/config
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2017-06-26
Tim Newsome
Move target definition into individual files.
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2017-06-23
Tim Newsome
Test gdb/OpenOCD during regular test run.
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2017-06-23
Tim Newsome
Add basic multicore test.
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2017-06-20
Tim Newsome
Smoketest multicore.
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2017-06-19
Tim Newsome
Write OpenOCD log when it crashes early.
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2017-06-16
Tim Newsome
Store logs for all tests in logs/
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2017-06-15
Tim Newsome
Test 64-bit addressing.
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2017-06-09
Tim Newsome
Add final echo to E300/U500 OpenOCD scripts
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2017-06-09
Tim Newsome
Make HiFive1 testing (mostly) work again
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2017-06-09
Tim Newsome
Fix using defaults for --server_cmd and --sim_cmd
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2017-06-09
Tim Newsome
Default to openocd, not riscv-openocd
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2017-06-05
Tim Newsome
Make pylint happy.
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2017-05-25
Palmer Dabbelt
Merge pull request #53 from richardxia/fail-if-simulato...
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2017-05-23
Richard Xia
Fail if simulator exits early.
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2017-05-22
Andrew Waterman
minNum -> minimumNumber
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2017-05-18
Megan Wachs
Merge pull request #52 from riscv/vcs_sim_cmd
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2017-05-18
Megan Wachs
debug: Correct the calling for a 32-bit simulation...
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2017-05-17
Andrew Waterman
Manually assemble bad shift amount, since assembler...
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2017-05-17
Palmer Dabbelt
Shorten the debug tests
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2017-05-17
Palmer Dabbelt
Merge pull request #49 from riscv/no_examine_target
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2017-05-17
Palmer Dabbelt
Show the debug logs to stdout, to avoid travis timeouts
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2017-05-16
Megan Wachs
debug: remove unused auto_int function
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2017-05-16
Megan Wachs
debug: Allow skipping the ExamineTarget task.
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2017-05-16
Megan Wachs
debug: Allow skipping the ExamineTarget step by specify...
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2017-05-16
Palmer Dabbelt
Merge pull request #47 from riscv/debug-0.13
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2017-05-16
Palmer Dabbelt
Change Spike's RAM location to match the linker script
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2017-05-16
Palmer Dabbelt
Link the infinate loop at 0x10000000
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