projects / soc.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
soc.git
2020-09-02 Luke Kenneth... series of extensive modifications to fix long-standing... commit | commitdiff | tree
2020-08-31 Luke Kenneth... add XER to fastregs and "construct" it in mfspr/mtspr commit | commitdiff | tree
2020-08-30 Luke Kenneth... redo OP_CMP based on microwatt. L=1 had been ignored commit | commitdiff | tree
2020-08-30 Luke Kenneth... reversal of FXM mask for one-hot selection in OP_MTCR... commit | commitdiff | tree
2020-08-30 Luke Kenneth... working on dcache.py commit | commitdiff | tree
2020-08-30 Luke Kenneth... tidyup on mul proof commit | commitdiff | tree
2020-08-30 Luke Kenneth... set mul post_stage o.ok only when needed, and fix xer_s... commit | commitdiff | tree
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-30 Cole Poiriericache.py commit progress, about a third through the... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs commit | commitdiff | tree
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza... commit | commitdiff | tree
2020-08-29 Cole Poiriermem_types add more types from common.vhdl specifially... commit | commitdiff | tree
2020-08-29 Cole Poiriermem_types.py arrange in alphabetical order for ease... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!! commit | commitdiff | tree
2020-08-29 Cole Poiriermmu.py remove duplicate comment left over from mmu... commit | commitdiff | tree
2020-08-29 Cole Poiriericache.py initial commit of first attempt at translatio... commit | commitdiff | tree
2020-08-29 Cesar StraussMove new write_gtkw and its example to nmutil commit | commitdiff | tree
2020-08-29 Luke Kenneth... minor code-shuffle, comments commit | commitdiff | tree
2020-08-29 Luke Kenneth... slowly morphing towards using an XER bit-field selector... commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIMUL pipeline formal proofs complete, I *think*. commit | commitdiff | tree
2020-08-29 Luke Kenneth... break down XER into flags commit | commitdiff | tree
2020-08-29 Luke Kenneth... add XER read via DMI interface to sim.py commit | commitdiff | tree
2020-08-29 Luke Kenneth... add hack to get at XER through DMI interface commit | commitdiff | tree
2020-08-29 Luke Kenneth... submodule update commit | commitdiff | tree
2020-08-29 Samuel A. Falvo IIWIP: prep for 64-bit insns commit | commitdiff | tree
2020-08-29 Luke Kenneth... yep disable OE for MULH64/32 and EXTS and CNTZ commit | commitdiff | tree
2020-08-29 Luke Kenneth... investigating CR mtocrf / mfocrf commit | commitdiff | tree
2020-08-29 Luke Kenneth... add additional CR regression tests commit | commitdiff | tree
2020-08-29 Luke Kenneth... allow pseudocode numbering to decrement in for-loops commit | commitdiff | tree
2020-08-29 Luke Kenneth... add wat to write out raw binary assembled programs commit | commitdiff | tree
2020-08-29 Luke Kenneth... CR FXM becomes a full mask. commit | commitdiff | tree
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb... commit | commitdiff | tree
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu... commit | commitdiff | tree
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-27 Cole Poirierdcache.py implement the remaining vhdl generate stateme... commit | commitdiff | tree
2020-08-27 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=476 commit | commitdiff | tree
2020-08-27 Luke Kenneth... xer so is not being passed through to CR0 commit | commitdiff | tree
2020-08-27 Luke Kenneth... really bad hack to fix simulator bug in carry handling commit | commitdiff | tree
2020-08-27 Luke Kenneth... augment addme test case to show bug #476 commit | commitdiff | tree
2020-08-27 Luke Kenneth... add addze and addme uni tests commit | commitdiff | tree
2020-08-27 Luke Kenneth... incompatibility with POWER9 on mulhw/u due to lack... commit | commitdiff | tree
2020-08-27 Luke Kenneth... overflow-enable does not occur on shift operations commit | commitdiff | tree
2020-08-27 Luke Kenneth... oink, write_cr shiftrot record width was zero (??) commit | commitdiff | tree
2020-08-27 Luke Kenneth... sorting out shift_rot to use new output stage data... commit | commitdiff | tree
2020-08-27 Luke Kenneth... need to read SO if Rc=1 commit | commitdiff | tree
2020-08-27 Luke Kenneth... reorg of SO handling related to CR0 commit | commitdiff | tree
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with... commit | commitdiff | tree
2020-08-26 Luke Kenneth... use sub-test in logical test_pipe_caller commit | commitdiff | tree
2020-08-26 Luke Kenneth... investigating div fsm and simulator bug commit | commitdiff | tree
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions... commit | commitdiff | tree
2020-08-25 Jacob Lifshayfix broken remainder for div FSM commit | commitdiff | tree
2020-08-25 Jacob Lifshayclean up formatting commit | commitdiff | tree
2020-08-25 Luke Kenneth... although shift-rot does not alter XER.so it still needs... commit | commitdiff | tree
2020-08-25 Luke Kenneth... add way to capture CR from DMI in litex sim commit | commitdiff | tree
2020-08-25 Luke Kenneth... add CR read to DMI interface commit | commitdiff | tree
2020-08-25 Luke Kenneth... shorten using temp vars commit | commitdiff | tree
2020-08-25 Luke Kenneth... add CR DMI interface commit | commitdiff | tree
2020-08-25 Luke Kenneth... add crxor unit test to qemu commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py fix whitespace, fomatting, syntax commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py fix formatting commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top... commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file commit | commitdiff | tree
2020-08-24 Luke Kenneth... argh, reading regfile over DMI was overlapped and corru... commit | commitdiff | tree
2020-08-24 Luke Kenneth... add isel CR tests to run on qemu (confirmed working) commit | commitdiff | tree
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup commit | commitdiff | tree
2020-08-24 Luke Kenneth... make it easier to select FSM/Pipe DIV unit commit | commitdiff | tree
2020-08-24 Luke Kenneth... fix *another* ld-update-related timing / FSM issue commit | commitdiff | tree
2020-08-24 Luke Kenneth... tidyup / shuffle after review commit | commitdiff | tree
2020-08-24 Luke Kenneth... remove default parameter commit | commitdiff | tree
2020-08-24 Luke Kenneth... "WAY" does not exist - range(NUM_WAYS) was intended commit | commitdiff | tree
2020-08-24 Luke Kenneth... use WAY_BITS in appropriate locations commit | commitdiff | tree
2020-08-24 Luke Kenneth... reminder that the license (reflecting what is in setup... commit | commitdiff | tree
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about... commit | commitdiff | tree
2020-08-23 Luke Kenneth... update copyright notices to include additional primary... commit | commitdiff | tree
2020-08-23 Luke Kenneth... add load algebraic immediate unit test commit | commitdiff | tree
2020-08-23 Luke Kenneth... add algebraic ld tests lwax, lwaux commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright to files I primarily authored in simulator/ commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary... commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py commit | commitdiff | tree
2020-08-23 Luke Kenneth... bring "core stopped" signal out through DMI interface commit | commitdiff | tree
2020-08-23 Luke Kenneth... add in DMI "stat" loop which monitors core "stopping" commit | commitdiff | tree
2020-08-23 Cesar StraussAllow an empty style, and passing default styles as... commit | commitdiff | tree
2020-08-23 Cesar StraussAdd comment node type commit | commitdiff | tree
2020-08-23 Cesar StraussAdd base and display styles commit | commitdiff | tree
2020-08-23 Cesar StraussApply style from node own name commit | commitdiff | tree
2020-08-23 Cesar StraussAdd color style commit | commitdiff | tree
2020-08-23 Cesar StraussCollect styles from the tuple commit | commitdiff | tree
2020-08-23 Cesar StraussPropagate the root style to all signals commit | commitdiff | tree
2020-08-23 Luke Kenneth... comment why litex sim mem map is altered commit | commitdiff | tree
2020-08-23 Luke Kenneth... multiply does not have invert_in, zero_a or invert_out commit | commitdiff | tree
2020-08-22 Luke Kenneth... rename invert_a to invert_in because logical inverts RB commit | commitdiff | tree
2020-08-22 Luke Kenneth... update submodule commit | commitdiff | tree
2020-08-22 Luke Kenneth... load bios not 1.bin unit test commit | commitdiff | tree
next