soc.git
2020-06-25 Luke Kenneth... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth... add nmigen-soc to dependencies
2020-06-25 Luke Kenneth... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanUpdate comments for LoadStoreUnitInterface
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface again
2020-06-24 Michael NolanUpdate comments on LoadStoreUnitInterface
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth... move comments to minerva LoadStoreInterface
2020-06-24 Luke Kenneth... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth... annoying error in latest nmigen
2020-06-23 Luke Kenneth... TstL0CacheBuffer returns array of ports differently now
2020-06-22 Luke Kenneth... remove unused module
2020-06-22 Luke Kenneth... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth... comments for LDST CompUnit test
2020-06-22 Luke Kenneth... enable byte-reverse in CompLDSTUnit test
2020-06-22 Luke Kenneth... remove CompLDSTOpSubset, replace with just data_len.
2020-06-22 Luke Kenneth... move BE/LE byte-reverse into LDSTCompUnit
2020-06-20 Luke Kenneth... expand Memory width to 64 and granularity to 16 in...
2020-06-20 Luke Kenneth... add asserts to check data output is correct
2020-06-20 Luke Kenneth... add test_sram_wishbone.py
2020-06-20 colepoirierAdd code, commented-out, for TRAP so as to not break...
2020-06-19 Luke Kenneth... whitespace update
2020-06-19 Luke Kenneth... move trunc_div and trunc_rem to nmutil
2020-06-19 Luke Kenneth... add comments on trunc_div and trunc_rem
2020-06-19 Luke Kenneth... add divide-by-zero test to test_div_sim.py
2020-06-19 Luke Kenneth... add docstring comment for SelectableInt
2020-06-19 Luke Kenneth... add test_0_moduw and correct name to trunc_rem
2020-06-19 Luke Kenneth... add abs SelectableInt unit test (very quick)
2020-06-19 Luke Kenneth... add SelectableInt.abs
2020-06-19 Luke Kenneth... add another bad hack in parser.py which identifies...
2020-06-19 Luke Kenneth... add in really bad hack which calls trunc_div or trunc_mod
2020-06-19 Luke Kenneth... add trunc_div and trunch_rem to decoder helpers
2020-06-19 Luke Kenneth... auto-assign needs to use concat / selectconcat
2020-06-19 Luke Kenneth... whoops detected page name wrong, for special case fixed...
2020-06-19 Luke Kenneth... bit of a mess. getting carry recognised and output...
2020-06-19 Luke Kenneth... add auto-assign mode detecting uninitialised variable...
2020-06-19 Luke Kenneth... div needs to be floordiv
2020-06-19 Luke Kenneth... add true and floor div to SelectableInt
2020-06-19 Luke Kenneth... add simulator test for divw
2020-06-19 Luke Kenneth... do mix-in for test_sim.py so that jacob can write some...
2020-06-19 Luke Kenneth... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-19 Luke Kenneth... parameterise LoadStoreUnitInterface to be expandable
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Luke Kenneth... enable general test cases in test_issuer
2020-06-18 Luke Kenneth... got loop example operational by noting when PC fastreg...
2020-06-18 Luke Kenneth... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth... get instructions immediately from assembly code
2020-06-18 Luke Kenneth... move test_sim.py unit tests to different class (split)
2020-06-18 Luke Kenneth... slightly hacky way to keep an eye on the PC
2020-06-18 Luke Kenneth... whoops generate core ilang not TestIssuer
2020-06-18 Luke Kenneth... use while / exception in test_compunit loop
2020-06-18 Luke Kenneth... investigating mtocrf/mtcrf issue
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-17 Luke Kenneth... add bug reference to mtocrf/mtcrf name decoding
2020-06-17 Luke Kenneth... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth... update submodule
2020-06-17 Luke Kenneth... add comment/assembly decode in power enums
2020-06-17 Luke Kenneth... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth... add loop example, required a bit of munging.
2020-06-17 Luke Kenneth... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth... got fed up of adding arguments to ISACaller / ISA,...
2020-06-17 Luke Kenneth... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth... comment ISACaller setup
2020-06-17 Luke Kenneth... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth... use an independent power decoder in ISACaller
2020-06-17 Luke Kenneth... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth... add optional instruction memory
2020-06-17 Luke Kenneth... split out TestIssuer into separate module
2020-06-17 Luke Kenneth... remove unneeded yield
2020-06-17 Luke Kenneth... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth... move debug statements to check function
2020-06-16 Luke Kenneth... hack LD/ST ad/st together, allow PC to be set externally
2020-06-16 Luke Kenneth... move check regs in simple core to separate function
2020-06-16 Luke Kenneth... move test core reg set up into separate function
2020-06-16 Luke Kenneth... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth... add ports to TestMemory
2020-06-16 Luke Kenneth... add beginnings of TestIssuer class, to issue instructio...
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