2020-07-17 |
Luke Kenneth... | use convenience vars in spr proof |
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2020-07-17 |
Samuel A. Falvo II | Flesh out SPR-related FV properties. |
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2020-07-17 |
Luke Kenneth... | whitespace |
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2020-07-17 |
Luke Kenneth... | whitespace |
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2020-07-17 |
Jacob Lifshay | add simulation-only division core using nmigen div... |
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2020-07-17 |
Jacob Lifshay | rename DIV->Div to be consistent |
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2020-07-17 |
Jacob Lifshay | format div code |
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2020-07-17 |
Jacob Lifshay | add missing fixedldstcache.py to .gitignore |
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2020-07-17 |
Jacob Lifshay | update submodule |
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2020-07-16 |
Luke Kenneth... | whoops tried doing mtspr priv, it failed but failed... div_pipeline |
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2020-07-16 |
Luke Kenneth... | get shiftrot compunit working |
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2020-07-16 |
Luke Kenneth... | more tidyup on use of CompOpSubsetBase |
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2020-07-16 |
Luke Kenneth... | use CompOpSubsetBase in ldst record |
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2020-07-16 |
Luke Kenneth... | sigh, bug in sprset.patch |
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2020-07-16 |
Luke Kenneth... | update cr input record to use new CompOpSubsetBase |
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2020-07-16 |
Luke Kenneth... | add regression test on setb simulator error |
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2020-07-16 |
Luke Kenneth... | use CompOpSubsetBase class in Branch op record |
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2020-07-16 |
Luke Kenneth... | get branch compunit working (missing bigendian arg) |
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2020-07-16 |
Luke Kenneth... | get trap compunit test working, adding bigendian and msr |
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2020-07-16 |
Luke Kenneth... | add mfmsr trap tests |
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2020-07-15 |
Luke Kenneth... | use new CompOpSubsetBase in trap |
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2020-07-15 |
Luke Kenneth... | remove unneeded comment in trap msin stage |
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2020-07-15 |
Luke Kenneth... | remove unneeded comment in trap pipe_data |
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2020-07-15 |
Luke Kenneth... | document branch pipeline relationship with PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | simplify instr_is_priv |
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2020-07-15 |
Luke Kenneth... | move traptype to soc.consts |
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2020-07-15 |
Luke Kenneth... | add better comments on mul overflow |
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2020-07-15 |
Luke Kenneth... | test privileged rfid call |
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2020-07-15 |
Luke Kenneth... | spelling error |
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2020-07-15 |
Luke Kenneth... | range of testing overflow was incorrect in mul |
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2020-07-15 |
Luke Kenneth... | set MSR up properly for privileged mtmsr test |
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2020-07-15 |
Luke Kenneth... | whoops forgot to update PC after trap in ISACaller |
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2020-07-15 |
Luke Kenneth... | move priv test to above illegal/trap test |
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2020-07-15 |
Luke Kenneth... | comments on IntegerData class |
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2020-07-15 |
Luke Kenneth... | import PipeContext not FPPipeContext |
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2020-07-15 |
Luke Kenneth... | minor reorg on PowerDecoder2, use switch/case rather... |
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2020-07-15 |
Luke Kenneth... | comments on SPRmap done in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | comments on SPRmap done in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | use case statement in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | select RA based on LDSTMode.update in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | add cache cx to LDSTMode |
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2020-07-15 |
Luke Kenneth... | remove unused class XerBits |
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2020-07-15 |
Luke Kenneth... | use Record Assert and also check muxid |
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2020-07-15 |
Luke Kenneth... | no need to check individual port members, just check... |
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2020-07-14 |
Luke Kenneth... | cookie-cut setup from alu proof_main_stage.py |
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2020-07-14 |
Luke Kenneth... | reduce code size by using CompOpSubsetBase for ALU... |
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2020-07-14 |
Luke Kenneth... | split out CompOpSubsetBase (meaning to do for a while) |
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2020-07-14 |
Luke Kenneth... | update docstrings |
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2020-07-14 |
Luke Kenneth... | adding MSR.PR unit test intended to activate privileged... |
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2020-07-14 |
Luke Kenneth... | attempting to access self.msr directly |
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2020-07-14 |
Samuel A. Falvo II | SPR: FV that should fail currently passes |
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2020-07-14 |
Luke Kenneth... | set up masks for OP_RL* formal proof |
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2020-07-14 |
Luke Kenneth... | add priv instruction checking to ISACaller simulator |
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2020-07-14 |
Luke Kenneth... | add in privileged instruction decision-making in PowerD... |
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2020-07-14 |
Luke Kenneth... | add MSR reading to issue FSM |
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2020-07-14 |
Luke Kenneth... | comments on PowerDecode2 |
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2020-07-14 |
Luke Kenneth... | add MSR to PowerDecoder2 |
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2020-07-14 |
Luke Kenneth... | disable cxxsim test |
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2020-07-14 |
Luke Kenneth... | attempting running cxxsim on ALU pipeline test |
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2020-07-14 |
Luke Kenneth... | first attempt running cxxsim |
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2020-07-14 |
Tobias Platen | fix path to nmigen-soc.git |
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2020-07-13 |
Luke Kenneth... | whitespace |
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2020-07-13 |
Luke Kenneth... | formal proof of OP_EXTSWSLI |
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2020-07-13 |
Luke Kenneth... | quick test showing how left/right mask work |
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2020-07-13 |
Tobias Platen | add nmigen-soc to .gitlab-ci.yml |
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2020-07-13 |
Luke Kenneth... | add mtmsrd instruction and unit test |
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2020-07-13 |
Luke Kenneth... | comments |
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2020-07-13 |
Luke Kenneth... | attempting formal proof of OP_EXTSWSLI |
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2020-07-13 |
Luke Kenneth... | reduce rotl module to one line (use bit_select) |
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2020-07-13 |
Luke Kenneth... | document rb as sh |
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2020-07-13 |
Luke Kenneth... | increase range of test values for extswsli |
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2020-07-13 |
Luke Kenneth... | add EXTSWSLI "pass" to formal shift_rot proof |
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2020-07-13 |
Luke Kenneth... | remove unneeded spec patching |
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2020-07-13 |
Luke Kenneth... | enable extswsli tests, fix spec-patching |
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2020-07-13 |
Luke Kenneth... | add regression test, simulator is wrong |
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2020-07-13 |
Luke Kenneth... | add simulator test against qemu for extswsli |
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2020-07-13 |
Luke Kenneth... | fix read of sliced register |
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2020-07-13 |
Luke Kenneth... | not perfect but close enough: add read registers RA... |
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2020-07-13 |
Luke Kenneth... | add extswsli unit test |
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2020-07-13 |
Luke Kenneth... | add link to rotator, sign-extend mode OP_EXTSWSLI |
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2020-07-12 |
Luke Kenneth... | rename InternalOp to MicrOp |
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2020-07-12 |
Luke Kenneth... | attempting to get test_trap_sim working, seems to switc... |
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2020-07-12 |
Luke Kenneth... | submodule update |
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2020-07-12 |
Luke Kenneth... | add OP_ATTN test back in |
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2020-07-12 |
Luke Kenneth... | exit FSM when termination detected |
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2020-07-12 |
Luke Kenneth... | code-morph on core connect_instruction |
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2020-07-12 |
Luke Kenneth... | modify PowerDecoder to read LDSTMode correctly |
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2020-07-12 |
Luke Kenneth... | change CSV LD/ST update field to LDSTMode (support... |
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2020-07-12 |
Luke Kenneth... | return unsigned int from binary reading |
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2020-07-12 |
Luke Kenneth... | update submodule |
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2020-07-12 |
Luke Kenneth... | missed setting of link register on OP_BC in PowerDecoder2 |
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2020-07-12 |
Luke Kenneth... | msb of instruction causing sign-overflow |
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2020-07-12 |
Luke Kenneth... | add std and stdu ldst unit tests |
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2020-07-12 |
Luke Kenneth... | update-mode request write signalled too early |
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2020-07-11 |
Luke Kenneth... | sort out core write latching: gate by busy, and use... |
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2020-07-11 |
Luke Kenneth... | * clarifying core function unit enable |
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2020-07-11 |
Luke Kenneth... | add bigendian flag |
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2020-07-11 |
Luke Kenneth... | add endian |
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2020-07-11 |
Luke Kenneth... | fix spr setting, set endianness |
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2020-07-11 |
Luke Kenneth... | sigh spelling |
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next |