soc.git
2021-12-08 Jacob Lifshayaccount for Mock absurdities
2021-12-07 Luke Kenneth... complete the i-cache fetch through the MMU, including...
2021-12-07 Luke Kenneth... set separate "iside" signal in LoadStore1 to not confuse it
2021-12-07 Luke Kenneth... start extending icache loadstore test
2021-12-07 Luke Kenneth... whoops another serious error in the CacheTagArray
2021-12-07 Luke Kenneth... add first i-cache fetch (non-virtual), no MMU lookup...
2021-12-07 Luke Kenneth... code-comments
2021-12-07 Luke Kenneth... add in I-Cache into LoadStore1 - presently unused ...
2021-12-07 Luke Kenneth... add discussion links and bugreport
2021-12-07 Luke Kenneth... invert mmureq statements
2021-12-07 Luke Kenneth... submodule tidyup
2021-12-07 Jacob Lifshaymake bitmanip operations conditional on pspec.draft_bit...
2021-12-07 Jacob Lifshayformat code
2021-12-07 Jacob Lifshaymove rotator mode assignments as requested by lkcl
2021-12-07 Jacob Lifshayformat code
2021-12-07 Luke Kenneth... tidyup, comments
2021-12-07 Luke Kenneth... debug print
2021-12-06 Luke Kenneth... another major bug, CacheTagArray valid was only 1 bit...
2021-12-06 Luke Kenneth... tidyup: move hit_set to DCachePendingHit in dcache.py
2021-12-06 Luke Kenneth... dcache.py tidyup
2021-12-06 Luke Kenneth... rename dtlb to dtlb_valid and tidyup
2021-12-06 Luke Kenneth... convert TLBArray to TLBValidArray
2021-12-06 Luke Kenneth... convert DTLBUpdate to use a pair of Memorys
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate
2021-12-06 Luke Kenneth... more signals local to DTLBUpdate
2021-12-06 Luke Kenneth... update DTLBUpdate to reflect internal API now
2021-12-06 Luke Kenneth... ooo nasty bug. used tlb_hit.way instead of tlb_hit...
2021-12-06 Luke Kenneth... move DTLB Tags/Valids/PTEs into DTLBUpdate module
2021-12-06 Luke Kenneth... start moving TLBArray into DTLBUpdate
2021-12-06 Luke Kenneth... PLRUs were selecting an output index, only one selected
2021-12-06 Luke Kenneth... repeated copies of read/write addr/sel to Cache SRAMs
2021-12-06 Luke Kenneth... move bank of PLRUs to their own submodule in both dcach...
2021-12-06 Luke Kenneth... code-comments
2021-12-06 Luke Kenneth... use binary-to-unary encoders in dcache.py
2021-12-06 Luke Kenneth... global (one) do_read signal in cache_rams dcache.py
2021-12-06 Luke Kenneth... use one-hot binary-to-unary in dcache.py
2021-12-06 Luke Kenneth... use i_in.req to gate hit_way via Decoder in icache.py
2021-12-06 Luke Kenneth... use Decoder (binary-to-unary) in icache.py to deal...
2021-12-05 Luke Kenneth... use unary encoding (one-hot) for replace_way hit_way...
2021-12-05 Luke Kenneth... code-comments
2021-12-05 Luke Kenneth... whitespace and minor cleanup of D-Cache
2021-12-05 Luke Kenneth... more use of TLBHit Record in D-Cache
2021-12-05 Luke Kenneth... correct tlb_hit_way and index sizes, use TLBHit Record...
2021-12-05 Luke Kenneth... use TLBRecord in D-Cache for which TLB is selected
2021-12-05 Luke Kenneth... split out TLBRecord, correct number of valid bits
2021-12-05 Luke Kenneth... use Record in DCache for TLB
2021-12-05 Luke Kenneth... use Record in D-Cache Cache Tags
2021-12-05 Luke Kenneth... whitespace
2021-12-05 Luke Kenneth... use Record for I-Cache Cache Tag/Valid
2021-12-05 Luke Kenneth... whitespace
2021-12-05 Luke Kenneth... use Record for ICache TLB
2021-12-05 Luke Kenneth... sorting out test_mmu_dcache.py to use wb_get
2021-12-05 Luke Kenneth... convert icache.py to standard wishbone Interface
2021-12-05 Luke Kenneth... fake up wishbone stall signal in icache.
2021-12-05 Luke Kenneth... fix icache row store issue
2021-12-05 Luke Kenneth... using same tag/row functions as in dcache.py
2021-12-05 Luke Kenneth... more signal sizes in icache.py
2021-12-05 Luke Kenneth... incorrect Signal sizes in icache.py,
2021-12-05 Luke Kenneth... sorting out icache.py, used to work
2021-12-05 Luke Kenneth... remove redundant code
2021-12-05 Luke Kenneth... add I-Cache standard bus (not used yet)
2021-12-05 Luke Kenneth... remove yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth... replace yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth... wishbone bus convert on dcache
2021-12-05 Luke Kenneth... correct import of wg_get function
2021-12-04 Luke Kenneth... remove yet another duplicated copy of wb_get and add...
2021-12-04 Luke Kenneth... rename function which needs replacing
2021-12-04 Luke Kenneth... should have been using common version of wb_get, not...
2021-12-04 Luke Kenneth... should not have been duplicating wb_get function in...
2021-12-04 Luke Kenneth... get test_mmu_dcache.py working again
2021-12-04 Luke Kenneth... remove wb_get, should not have been duplicated
2021-12-04 Luke Kenneth... remove wb_get, should not have been massively duplicate...
2021-12-04 Luke Kenneth... fix return results from pi_ld
2021-12-04 Luke Kenneth... wark-wark, broke mmu with removing rin. reverted
2021-12-04 Tobias Platenfixed wait_addr to exit immediately on exception
2021-12-04 Luke Kenneth... tidyup, comments
2021-12-04 Luke Kenneth... tidyup mmu
2021-12-04 Luke Kenneth... sigh in MMU FSM use direct access to ldst.dar/dsisr...
2021-12-04 Luke Kenneth... remove DAR from PortInterface (where is the data going...
2021-12-04 Luke Kenneth... stop using dar_o from PortInterface, get DAR directly...
2021-12-04 Luke Kenneth... put DSISR and DAR publicly accessible in LoadStore1
2021-12-04 Luke Kenneth... whoops fix up exception happened if alignment triggers...
2021-12-04 Luke Kenneth... fix pi_st which should not be trying to wait for the...
2021-12-04 Luke Kenneth... fixing DAR updating from exceptions
2021-12-04 Luke Kenneth... whoops
2021-12-04 Luke Kenneth... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-04 Luke Kenneth... store DAR in LoadStore1
2021-12-04 Luke Kenneth... not busy if excrption occurs on MMU_LOOKUP in loadstore.py
2021-12-04 Luke Kenneth... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth... in loadstore.py set align_intr from request which comes...
2021-12-03 Luke Kenneth... driver conflict on priv_mode and virt_mode, do not...
2021-12-03 Luke Kenneth... fix up test_loadstore1.py
2021-12-03 Luke Kenneth... in loadstore.py, when an exception is done or if the FSM
2021-12-03 Luke Kenneth... fix PortInterfaceBase
2021-12-03 Luke Kenneth... fix up LDST test functions pi_ld and pi_st to respect...
2021-12-03 Luke Kenneth... whitespace
2021-12-03 Luke Kenneth... add misaligned ld/st to trigger an exception
2021-12-03 Luke Kenneth... comment out dsisr and dar in mmu FSM for now
2021-12-02 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
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