soc.git
2021-12-05 Luke Kenneth... remove yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth... replace yet another duplicate copy of wb_get, possible...
2021-12-05 Luke Kenneth... wishbone bus convert on dcache
2021-12-05 Luke Kenneth... correct import of wg_get function
2021-12-04 Luke Kenneth... remove yet another duplicated copy of wb_get and add...
2021-12-04 Luke Kenneth... rename function which needs replacing
2021-12-04 Luke Kenneth... should have been using common version of wb_get, not...
2021-12-04 Luke Kenneth... should not have been duplicating wb_get function in...
2021-12-04 Luke Kenneth... get test_mmu_dcache.py working again
2021-12-04 Luke Kenneth... remove wb_get, should not have been duplicated
2021-12-04 Luke Kenneth... remove wb_get, should not have been massively duplicate...
2021-12-04 Luke Kenneth... fix return results from pi_ld
2021-12-04 Luke Kenneth... wark-wark, broke mmu with removing rin. reverted
2021-12-04 Tobias Platenfixed wait_addr to exit immediately on exception
2021-12-04 Luke Kenneth... tidyup, comments
2021-12-04 Luke Kenneth... tidyup mmu
2021-12-04 Luke Kenneth... sigh in MMU FSM use direct access to ldst.dar/dsisr...
2021-12-04 Luke Kenneth... remove DAR from PortInterface (where is the data going...
2021-12-04 Luke Kenneth... stop using dar_o from PortInterface, get DAR directly...
2021-12-04 Luke Kenneth... put DSISR and DAR publicly accessible in LoadStore1
2021-12-04 Luke Kenneth... whoops fix up exception happened if alignment triggers...
2021-12-04 Luke Kenneth... fix pi_st which should not be trying to wait for the...
2021-12-04 Luke Kenneth... fixing DAR updating from exceptions
2021-12-04 Luke Kenneth... whoops
2021-12-04 Luke Kenneth... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-04 Luke Kenneth... store DAR in LoadStore1
2021-12-04 Luke Kenneth... not busy if excrption occurs on MMU_LOOKUP in loadstore.py
2021-12-04 Luke Kenneth... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth... in loadstore.py set align_intr from request which comes...
2021-12-03 Luke Kenneth... driver conflict on priv_mode and virt_mode, do not...
2021-12-03 Luke Kenneth... fix up test_loadstore1.py
2021-12-03 Luke Kenneth... in loadstore.py, when an exception is done or if the FSM
2021-12-03 Luke Kenneth... fix PortInterfaceBase
2021-12-03 Luke Kenneth... fix up LDST test functions pi_ld and pi_st to respect...
2021-12-03 Luke Kenneth... whitespace
2021-12-03 Luke Kenneth... add misaligned ld/st to trigger an exception
2021-12-03 Luke Kenneth... comment out dsisr and dar in mmu FSM for now
2021-12-02 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-12-02 Tobias Platencleanup test_compldst_multi_mmu.py
2021-12-02 Luke Kenneth... add a bitvector remap function, the plan is to use...
2021-12-02 Tobias Platenfix test_random in test_loadstore1
2021-12-02 Luke Kenneth... use new namedtuple in core when calling regspec_decode()
2021-12-02 Luke Kenneth... add module parameter to regspec_decode and therefore...
2021-12-02 Jacob Lifshayremove bitmanip fu cuz ternlogi (the only instruction...
2021-12-02 Jacob Lifshayadd ternlogi to shiftrot
2021-12-02 Jacob Lifshayformat code
2021-12-01 Luke Kenneth... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth... experimenting with option to shorten MultiCompUnit...
2021-12-01 Luke Kenneth... create single-stage ALU pipeline, shorten latency on...
2021-12-01 Luke Kenneth... allow MultiCompUnit to set read and write latches to...
2021-12-01 Luke Kenneth... FunctionUnitBaseMulti which derives from ReservationSta...
2021-12-01 Luke Kenneth... better name for read latch in core.py
2021-12-01 Luke Kenneth... use m.submodules[name] instead of getattr
2021-12-01 Luke Kenneth... remove redundant / mis-named variable in core
2021-12-01 Luke Kenneth... code-comments
2021-12-01 Luke Kenneth... remove unneeded data structure in core
2021-12-01 Luke Kenneth... whoops treereduce on write-vector set/clr error
2021-12-01 Luke Kenneth... more code-cleanup
2021-12-01 Luke Kenneth... use new regspec_decode and fu.get_iospec functions
2021-12-01 Luke Kenneth... core tidyup
2021-12-01 Luke Kenneth... add Regspecs get_io_spec function
2021-11-30 Luke Kenneth... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias Platenrandom loadstore1 test: readback written data
2021-11-30 Tobias Platenreenable dcbz test case
2021-11-30 Tobias Platenreturn correct data from microwatt
2021-11-30 Tobias Platencleanup test_loadstore1.py
2021-11-30 Tobias Platenloadstore: add done_delay
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth... add LogicalTestCases back in to test_core.py (pass)
2021-11-30 Luke Kenneth... let PowerDecode2 decide which operand class to use...
2021-11-30 Luke Kenneth... use latched readflag (recspec_decode_read "ok") instead...
2021-11-30 Luke Kenneth... tidyup on read-flag latches
2021-11-30 Luke Kenneth... fix read-decode information by latching not just the...
2021-11-30 Luke Kenneth... fix write-after-write hazard checking
2021-11-30 Luke Kenneth... allow busy to settle before checking state in test_core.py
2021-11-30 Luke Kenneth... only check regs right at the end in test_core.py overla...
2021-11-30 Luke Kenneth... move sim call before core run in test_core.py
2021-11-30 Luke Kenneth... getting formerly unused test_core.py operational
2021-11-29 Luke Kenneth... whoops missed make_hazard_vec test
2021-11-29 Luke Kenneth... whoops do the set/get of the write-vector at a single...
2021-11-29 Luke Kenneth... always set fwd_bus_mode=False on regfiles
2021-11-29 Luke Kenneth... add MMU and SPR to list of FUs that must report "busy...
2021-11-29 Luke Kenneth... disallow overlap in core on LDST, Branch, and Trap.
2021-11-29 Luke Kenneth... use dict style not setattr on submodules
2021-11-28 Tobias Platenupdate loadstore1 testcase
2021-11-27 Luke Kenneth... code-comments
2021-11-27 Luke Kenneth... fix instructions of the type "read-reg-is-same-as-write"
2021-11-27 Tobias Platenloadstore testcase: read at random addresses
2021-11-27 Luke Kenneth... FU-Regs matrix tidyup and comments
2021-11-27 Luke Kenneth... minor tidyup on FU-Regs Matrix
2021-11-27 Luke Kenneth... update FURegDepMatrix to multi-dest
2021-11-27 Luke Kenneth... update naming on Reg_Rsv signals
2021-11-27 Luke Kenneth... add copyright and attribution notices
2021-11-27 Luke Kenneth... update FU_RW_Pending vectors to multi-dest
2021-11-27 Luke Kenneth... convert DependencyRow to multiple destination latches
2021-11-27 Luke Kenneth... add copyright and attribution notices to dependence_cell.py
2021-11-27 Luke Kenneth... update license and attribution in fu_reg_matrix.py
2021-11-26 Luke Kenneth... convert score6600_multi over to using RegSpecs (in...
2021-11-26 Luke Kenneth... early use of Array unnecessarily (all uses are static...
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