soc.git
2020-07-09 Luke Kenneth... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-09 Cesar StraussDefine ports for a simple sequential Shifter
2020-07-09 Luke Kenneth... irony comment on how one line creates a massive array...
2020-07-09 Luke Kenneth... add new stages etc. to get multiply working without...
2020-07-09 Luke Kenneth... create new DivMulOutputData which does not have CA...
2020-07-09 Luke Kenneth... make carry output handling optional in common output...
2020-07-09 Luke Kenneth... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth... resolving bigendian/littleendian modes in qemu sim
2020-07-08 Luke Kenneth... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth... resolving old and new behaviour for lookup of SPRs
2020-07-08 Luke Kenneth... adding in ALU test back in, debugging SPR setup
2020-07-08 Luke Kenneth... sorting out setting of XER
2020-07-08 Luke Kenneth... add spr to fast reg converter
2020-07-08 Luke Kenneth... got test_issuer operational on one unit test
2020-07-08 Luke Kenneth... switch assembler to little-endian
2020-07-08 Luke Kenneth... stashing current state of investigation whilst looking...
2020-07-08 Luke Kenneth... add test trap simulator unit test
2020-07-08 Luke Kenneth... allow qemu to stop at specified end point
2020-07-08 Luke Kenneth... add mtspr and bcctrl instructions to helloworld test
2020-07-08 Luke Kenneth... add option to qemu to break at known alternate address
2020-07-08 Luke Kenneth... add to/from spr test (mtspr, mfspr)
2020-07-08 Luke Kenneth... add code-fragment from microwatt helloworld
2020-07-08 Luke Kenneth... add a simple addis test (regression)
2020-07-08 Luke Kenneth... copy binary loaded from disk into data memory as well
2020-07-08 Cesar StraussStart the FSM-based ALU example.
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-08 Jacob Lifshayadd WIP pipeline loop demo
2020-07-07 Luke Kenneth... add hello world binary test
2020-07-07 Luke Kenneth... whoops error in test of dynamic parameter
2020-07-07 Luke Kenneth... sort-of got binary execution test working
2020-07-07 Luke Kenneth... code-shuffle on testing to prepare loading large files...
2020-07-07 Cesar StraussClear input data along with valid_i
2020-07-07 Luke Kenneth... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth... whoops got Function.NONE test wrong in PowerDecode2
2020-07-07 Luke Kenneth... remove unneeded record field from logical_input_record
2020-07-07 Luke Kenneth... debugging termination (OP_ATTN)
2020-07-07 Luke Kenneth... update opcode map for OP_ATTN
2020-07-07 Luke Kenneth... add halted condition in ISACaller, when attn instructio...
2020-07-07 Luke Kenneth... debugging termination / OP_ATTN
2020-07-07 Luke Kenneth... add ATTN unit test
2020-07-07 Luke Kenneth... add core start/stop capability, and OP_ATTN support
2020-07-07 Luke Kenneth... add in SPR test cases into test_issuer.py
2020-07-06 Luke Kenneth... use ComMULOpSubset in mul pipeline
2020-07-06 Luke Kenneth... remove alu unneeded op record data
2020-07-06 Luke Kenneth... remove alu unneeded op record data
2020-07-06 Luke Kenneth... remove alu unneeded op record data
2020-07-06 Luke Kenneth... add mul unit to test_issuer
2020-07-06 Luke Kenneth... add mul compunit
2020-07-06 Luke Kenneth... whoops forgot that the mul pipeline is actually a pipel...
2020-07-06 Luke Kenneth... do abs slightly differently in SelectableInt
2020-07-06 Luke Kenneth... continue mul unit test debugging
2020-07-06 Luke Kenneth... add MULS (signed) version of multiply
2020-07-06 Luke Kenneth... improve debug for test_sim.py
2020-07-06 Luke Kenneth... add mullw test to qemu sim
2020-07-06 Luke Kenneth... fix SelectableInt abs
2020-07-06 Luke Kenneth... add first simulator mul test
2020-07-06 Luke Kenneth... investigating mul pipeline
2020-07-06 Luke Kenneth... SelectableInt: make __mul__ return enough space to...
2020-07-06 Luke Kenneth... first cut at mul test pipeline
2020-07-06 Luke Kenneth... add first cut at fu mul pipeline
2020-07-06 Luke Kenneth... adding mtspr tests
2020-07-06 Luke Kenneth... adding OP_MTMSR test
2020-07-06 Luke Kenneth... add mtmsr internal op
2020-07-06 Luke Kenneth... add mtmsr internal op
2020-07-06 Luke Kenneth... sort out initialisation of TstL0CacheBuffer in ldst...
2020-07-06 Cesar StraussAssert n.ready_i at the beginning of the cycle
2020-07-06 Cesar StraussRemove wait state to demonstrate zero-delay reception.
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussFinally add some well needed comments
2020-07-06 Cesar StraussSimplify waiting loops
2020-07-06 Cesar StraussAdd some wait states in each process
2020-07-06 Cesar StraussNegate inputs after use
2020-07-06 Cesar StraussAdd other tests
2020-07-06 Cesar StraussImplement receiver
2020-07-06 Cesar StraussImplement sender.
2020-07-06 Cesar StraussBegin a new parallel test
2020-07-05 Luke Kenneth... add mtmsr tests (fail)
2020-07-05 Luke Kenneth... check trap compunit output properly
2020-07-05 Luke Kenneth... check msr in trap test, fix OP_RFID
2020-07-05 Luke Kenneth... add an illegal instruction trap test
2020-07-05 Luke Kenneth... set up a trap function for microcode override
2020-07-05 Luke Kenneth... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth... stop debug output in power_decoder
2020-07-05 Luke Kenneth... comments in power_regspec_map.py
2020-07-05 Luke Kenneth... comment on spr2, not needed
2020-07-05 Luke Kenneth... check xer_out not xer_in
2020-07-05 Luke Kenneth... split out Decode2ToExecuteType fields involving registers
2020-07-05 Luke Kenneth... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth... check spr1 in test spr compunit
2020-07-05 Luke Kenneth... get/set slow spr in spr test_pipe_caller
2020-07-05 Luke Kenneth... add first spr compunit test (not working yet)
2020-07-05 Luke Kenneth... add SPR test case, commented out for now
2020-07-05 Luke Kenneth... move valid signal out of Decode2ToExecute1Type and...
2020-07-05 Luke Kenneth... add slow spr regfile regspec support
2020-07-05 Luke Kenneth... remap SPR PowerISA numbers to internal SPR enum
2020-07-05 Luke Kenneth... comment out SPR for now, needs SPR regfile
2020-07-05 Luke Kenneth... add SPR compunit
2020-07-05 Luke Kenneth... missing initialisation of disasm_start
2020-07-05 Luke Kenneth... check NIA on trap fu test
2020-07-05 Luke Kenneth... OP_RFID needs to read SRR0/1, OP_SC needs to write
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