2020-07-15 |
Luke Kenneth... | use case statement in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | select RA based on LDSTMode.update in PowerDecode2 |
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2020-07-15 |
Luke Kenneth... | add cache cx to LDSTMode |
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2020-07-15 |
Luke Kenneth... | remove unused class XerBits |
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2020-07-15 |
Luke Kenneth... | use Record Assert and also check muxid |
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2020-07-15 |
Luke Kenneth... | no need to check individual port members, just check... |
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2020-07-14 |
Luke Kenneth... | cookie-cut setup from alu proof_main_stage.py |
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2020-07-14 |
Luke Kenneth... | reduce code size by using CompOpSubsetBase for ALU... |
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2020-07-14 |
Luke Kenneth... | split out CompOpSubsetBase (meaning to do for a while) |
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2020-07-14 |
Luke Kenneth... | update docstrings |
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2020-07-14 |
Luke Kenneth... | adding MSR.PR unit test intended to activate privileged... |
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2020-07-14 |
Luke Kenneth... | attempting to access self.msr directly |
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2020-07-14 |
Samuel A. Falvo II | SPR: FV that should fail currently passes |
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2020-07-14 |
Luke Kenneth... | set up masks for OP_RL* formal proof |
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2020-07-14 |
Luke Kenneth... | add priv instruction checking to ISACaller simulator |
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2020-07-14 |
Luke Kenneth... | add in privileged instruction decision-making in PowerD... |
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2020-07-14 |
Luke Kenneth... | add MSR reading to issue FSM |
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2020-07-14 |
Luke Kenneth... | comments on PowerDecode2 |
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2020-07-14 |
Luke Kenneth... | add MSR to PowerDecoder2 |
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2020-07-14 |
Luke Kenneth... | disable cxxsim test |
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2020-07-14 |
Luke Kenneth... | attempting running cxxsim on ALU pipeline test |
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2020-07-14 |
Luke Kenneth... | first attempt running cxxsim |
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2020-07-14 |
Tobias Platen | fix path to nmigen-soc.git |
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2020-07-13 |
Luke Kenneth... | whitespace |
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2020-07-13 |
Luke Kenneth... | formal proof of OP_EXTSWSLI |
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2020-07-13 |
Luke Kenneth... | quick test showing how left/right mask work |
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2020-07-13 |
Tobias Platen | add nmigen-soc to .gitlab-ci.yml |
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2020-07-13 |
Luke Kenneth... | add mtmsrd instruction and unit test |
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2020-07-13 |
Luke Kenneth... | comments |
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2020-07-13 |
Luke Kenneth... | attempting formal proof of OP_EXTSWSLI |
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2020-07-13 |
Luke Kenneth... | reduce rotl module to one line (use bit_select) |
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2020-07-13 |
Luke Kenneth... | document rb as sh |
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2020-07-13 |
Luke Kenneth... | increase range of test values for extswsli |
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2020-07-13 |
Luke Kenneth... | add EXTSWSLI "pass" to formal shift_rot proof |
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2020-07-13 |
Luke Kenneth... | remove unneeded spec patching |
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2020-07-13 |
Luke Kenneth... | enable extswsli tests, fix spec-patching |
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2020-07-13 |
Luke Kenneth... | add regression test, simulator is wrong |
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2020-07-13 |
Luke Kenneth... | add simulator test against qemu for extswsli |
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2020-07-13 |
Luke Kenneth... | fix read of sliced register |
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2020-07-13 |
Luke Kenneth... | not perfect but close enough: add read registers RA... |
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2020-07-13 |
Luke Kenneth... | add extswsli unit test |
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2020-07-13 |
Luke Kenneth... | add link to rotator, sign-extend mode OP_EXTSWSLI |
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2020-07-12 |
Luke Kenneth... | rename InternalOp to MicrOp |
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2020-07-12 |
Luke Kenneth... | attempting to get test_trap_sim working, seems to switc... |
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2020-07-12 |
Luke Kenneth... | submodule update |
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2020-07-12 |
Luke Kenneth... | add OP_ATTN test back in |
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2020-07-12 |
Luke Kenneth... | exit FSM when termination detected |
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2020-07-12 |
Luke Kenneth... | code-morph on core connect_instruction |
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2020-07-12 |
Luke Kenneth... | modify PowerDecoder to read LDSTMode correctly |
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2020-07-12 |
Luke Kenneth... | change CSV LD/ST update field to LDSTMode (support... |
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2020-07-12 |
Luke Kenneth... | return unsigned int from binary reading |
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2020-07-12 |
Luke Kenneth... | update submodule |
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2020-07-12 |
Luke Kenneth... | missed setting of link register on OP_BC in PowerDecoder2 |
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2020-07-12 |
Luke Kenneth... | msb of instruction causing sign-overflow |
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2020-07-12 |
Luke Kenneth... | add std and stdu ldst unit tests |
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2020-07-12 |
Luke Kenneth... | update-mode request write signalled too early |
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2020-07-11 |
Luke Kenneth... | sort out core write latching: gate by busy, and use... |
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2020-07-11 |
Luke Kenneth... | * clarifying core function unit enable |
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2020-07-11 |
Luke Kenneth... | add bigendian flag |
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2020-07-11 |
Luke Kenneth... | add endian |
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2020-07-11 |
Luke Kenneth... | fix spr setting, set endianness |
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2020-07-11 |
Luke Kenneth... | sigh spelling |
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2020-07-11 |
Luke Kenneth... | add bigendian |
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2020-07-11 |
Luke Kenneth... | more setting bigendian |
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2020-07-11 |
Luke Kenneth... | add bigendian mode to helloworld test |
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2020-07-11 |
Luke Kenneth... | sort out big/little endian startup on qemu |
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2020-07-11 |
Luke Kenneth... | sorting out bigendian/littleendian including in qemu |
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2020-07-11 |
Luke Kenneth... | whoops output trunc_divs not trunc_div |
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2020-07-11 |
Luke Kenneth... | add random mulhd and mulld tests |
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2020-07-11 |
Luke Kenneth... | enable mul tests after sorting pseudo-code mul overflow |
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2020-07-11 |
Luke Kenneth... | special test for mul hw to cope with ignoring OE flag |
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2020-07-10 |
Luke Kenneth... | add a DIVS function as separate and discrete from floor_div |
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2020-07-10 |
Luke Kenneth... | add random unsigned div tests |
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2020-07-10 |
Luke Kenneth... | add overflow div tests |
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2020-07-10 |
Luke Kenneth... | propagate missing parameters from div |
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2020-07-10 |
Luke Kenneth... | code comments |
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2020-07-10 |
Luke Kenneth... | do not set div result if overflow occurs |
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2020-07-10 |
Luke Kenneth... | re-enable div random tests and other regressions |
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2020-07-10 |
Luke Kenneth... | check for div_overflow equal to None rather than == 1 |
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2020-07-10 |
Luke Kenneth... | re-add rc/oe back into LDST input record |
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2020-07-10 |
Luke Kenneth... | whew panic over, missed a bigendian argument in test_co... |
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2020-07-10 |
Luke Kenneth... | add test7 div regression |
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2020-07-10 |
Luke Kenneth... | add more debug output for #425 |
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2020-07-10 |
Luke Kenneth... | add debugging chain for #425 |
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2020-07-10 |
Luke Kenneth... | update submodule |
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2020-07-10 |
Luke Kenneth... | cut/paste error writing to wrong vcd file |
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2020-07-10 |
Jacob Lifshay | switch to using Signal.width instead of Signal.shape... |
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2020-07-10 |
Jacob Lifshay | format file |
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2020-07-10 |
Jacob Lifshay | update libreriscv submodule |
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2020-07-09 |
Luke Kenneth... | add regression test for div overflow case |
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2020-07-09 |
Luke Kenneth... | slightly different so handling in common output stage |
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2020-07-09 |
Luke Kenneth... | also set so only if OE requires it |
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2020-07-09 |
Luke Kenneth... | debug information related to 32/64 bit mode |
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2020-07-09 |
Luke Kenneth... | bug #424 - 32/64 bit is a *global* flag not a per-op one |
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2020-07-09 |
Luke Kenneth... | test top bit 31 in 32-bit mode for CR0 creation |
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2020-07-09 |
Luke Kenneth... | ha ha very funny. pipelines being pipelines, you have... |
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2020-07-09 |
Luke Kenneth... | whoops test gets copied 4 times on the If. |
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2020-07-09 |
Luke Kenneth... | ALU output stage, change logic slightly |
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2020-07-09 |
Luke Kenneth... | set xer_ov.ok = 1 |
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2020-07-09 |
Luke Kenneth... | remove unneeded xer.ca in MulOutputData |
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next |