2021-01-26 |
Tobias Platen | [Bug 580] redirect MMU SPRs to the MMU |
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2021-01-25 |
Luke Kenneth... | extra comments in svp64 |
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2021-01-24 |
Luke Kenneth... | changing svp64 asm syntax to use / instead of . as... 24jan2021_ls180 |
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2021-01-23 |
Luke Kenneth... | move sanity-checks, add mode into svp64_rm |
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2021-01-23 |
Luke Kenneth... | cleanup on aisle 3 - simplify sv_mode svp64 |
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2021-01-23 |
Luke Kenneth... | check src/dest mask exist if zeroing, svp64 |
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2021-01-23 |
Luke Kenneth... | add predicate-result svp64 decoding |
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2021-01-23 |
Luke Kenneth... | add svp64 saturation decoding |
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2021-01-23 |
Luke Kenneth... | start decoding modes in svp64 |
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2021-01-23 |
Luke Kenneth... | and now for something completely different... |
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2021-01-23 |
Luke Kenneth... | add elwidth encoding svp64, add more debug-print |
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2021-01-23 |
Luke Kenneth... | add svp64 subvl encoding |
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2021-01-23 |
Luke Kenneth... | add in svp64 predicate mask encoding |
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2021-01-23 |
Luke Kenneth... | capture CR 3 and 5 bit sv encodings |
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2021-01-23 |
Luke Kenneth... | start decoding EXTRA2/3 |
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2021-01-23 |
Luke Kenneth... | start decoding sv EXTRAs and identifying them |
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2021-01-23 |
Luke Kenneth... | start to read RM CSV files |
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2021-01-23 |
Luke Kenneth... | add beginnings of svp64 assembly translator |
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2021-01-22 |
Luke Kenneth... | add example on how to access regs list for cmp |
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2021-01-19 |
Tobias Platen | test_issuer_mmu_data_path.py: test both ld and st instr... |
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2021-01-19 |
Tobias Platen | connect LDSTException to MMU and DCache |
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2021-01-19 |
Tobias Platen | connect wishbone bus to test memory |
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2021-01-18 |
Tobias Platen | uncomment #FIXME in unit_test |
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2021-01-18 |
Tobias Platen | fu/mmu/fsm.py: connect valid and load signals |
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2021-01-17 |
Tobias Platen | add test memory for simulation |
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2021-01-17 |
Tobias Platen | cleanup test_issuer_mmu_data_path.py |
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2021-01-16 |
Tobias Platen | clean up test case for tlbie and dcbz |
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2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
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2021-01-16 |
Tobias Platen | add new unittest: test_issuer_mmu_data_path.py |
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2021-01-15 |
Tobias Platen | cleanup test_non_production_core.py |
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2021-01-15 |
Tobias Platen | add microwatt_mmu boolean variable to core and compunits |
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2021-01-15 |
Tobias Platen | test_non_production_core.py: fix hanging test |
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2021-01-15 |
Tobias Platen | test_non_production_core.py: wire instruction decoder... |
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2021-01-14 |
Tobias Platen | add test case for mmu+NonProductionCore |
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2021-01-10 |
Tobias Platen | add microwatt mmu config option to compunits.py |
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2021-01-08 |
Tobias Platen | fix broken testcase for simple core |
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2021-01-07 |
Tobias Platen | set initial_sprs, cleanup mfspr testprog |
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2021-01-07 |
Tobias Platen | mfspr is RT, SPR |
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2021-01-06 |
Tobias Platen | first testcase for mmu: case_mfspr_after_invalid_load |
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2021-01-06 |
Tobias Platen | fu/mmu/fsm.py: mfspr!=mtspr |
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2021-01-04 |
Tobias Platen | test_countzero.py: rename output files |
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2021-01-01 |
Cesar Strauss | Add zero CR test case and fix comments |
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2021-01-01 |
Cesar Strauss | Add test cases with rc=1 |
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2021-01-01 |
Cesar Strauss | Make all ports the same size, on the test ALU |
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2021-01-01 |
Cesar Strauss | Add CR output port to test cases |
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2021-01-01 |
Cesar Strauss | Add CR to the output data port |
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2021-01-01 |
Cesar Strauss | Make output write enables independent of valid_o |
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2021-01-01 |
Cesar Strauss | Move NOP test case earlier |
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2021-01-01 |
Cesar Strauss | Disable data value output on NOP |
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2021-01-01 |
Cesar Strauss | Add condition register (CR) output |
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2020-12-31 |
Cesar Strauss | Implement and test NOP in the test ALU |
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2020-12-31 |
Cesar Strauss | Don't use OP_NOP for zero-delay subtraction |
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2020-12-31 |
Cesar Strauss | Test first input port being masked out |
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2020-12-31 |
Cesar Strauss | Sign extend the second input port |
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2020-12-31 |
Cesar Strauss | Test masked-out second input port |
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2020-12-31 |
Cesar Strauss | Add sign extend to the Test ALU |
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2020-12-31 |
Cesar Strauss | Show rdmaskn and wrmask in GTKWave |
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2020-12-31 |
Cesar Strauss | Use the increment operator |
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2020-12-31 |
Cesar Strauss | Add support for masked write operations |
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2020-12-31 |
Cesar Strauss | Clarify reason for holding rdmaskn valid during the... |
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2020-12-31 |
Cesar Strauss | Remove previous version of the CompUnit parallel unit... |
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2020-12-31 |
Cesar Strauss | Only hold the decoder signals for one cycle, along... |
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2020-12-30 |
Cesar Strauss | Test the rdmaskn control signal |
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2020-12-29 |
Cesar Strauss | Remove left-over comments. |
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2020-12-28 |
Luke Kenneth... | add CR1 to power_enums |
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2020-12-20 |
Cesar Strauss | Add support for CXXSim simulation |
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2020-12-13 |
Cesar Strauss | Ignore formal verification output in the source directory |
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2020-12-13 |
Cesar Strauss | Allow more test cases to be run with CXXSim |
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2020-12-12 |
Luke Kenneth... | skip madd, not implemented |
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2020-12-09 |
Luke Kenneth... | update submodules |
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2020-12-09 |
Luke Kenneth... | update submodules |
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2020-12-07 |
Cesar Strauss | Display the instruction type as a vector on cxxsim |
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2020-12-06 |
Luke Kenneth... | attempt to split into two separate GPIO banks due to... |
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2020-12-06 |
Cesar Strauss | Whitespace |
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2020-12-06 |
Cesar Strauss | Update GTKWave documents to work with latest cxxsim |
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2020-12-05 |
Cesar Strauss | Write a GTKWave document to investigate why the proof... |
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2020-12-05 |
Cesar Strauss | Use the DummyALU regspec and its corresponding OpSubset |
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2020-12-03 |
Luke Kenneth... | put ls180 litex bus width back to 32 bit temporarily |
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2020-12-03 |
Luke Kenneth... | argh issue with yosys ABC |
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2020-12-03 |
Luke Kenneth... | add 3 more 4k SRAMs, change WB bus width to 64 in ls180... |
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2020-11-28 |
Cesar Strauss | Fix signal names: go/rel -> go_i/rel_o |
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2020-11-24 |
Cesar Strauss | Fix some typos and whitespace |
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2020-11-24 |
Cesar Strauss | Port the DummyALU test case to the new parallel issuer |
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2020-11-23 |
Cesar Strauss | Results are now a list, so "expected" should follow... |
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2020-11-23 |
Cesar Strauss | Parameterize the issuer on the number of operands and... |
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2020-11-22 |
Cesar Strauss | Refactor the ALU operation issuer into a class |
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2020-11-22 |
Cesar Strauss | Port the ALU test case to the new parallel test style |
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2020-11-22 |
Cesar Strauss | Add a GTKWave document to the ALU test case |
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2020-11-22 |
Luke Kenneth... | simplify litex-core wishbone interfaces |
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2020-11-19 |
Cesar Strauss | Separate input and output ports by color |
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2020-11-19 |
Cesar Strauss | Explain the test cases |
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2020-11-18 |
Cesar Strauss | Separate individual traces for each rel_o/go_i port |
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2020-11-17 |
Tobias Platen | testcase for dcbz |
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2020-11-16 |
Cesar Strauss | Add a transaction counter to producers and consumers |
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2020-11-16 |
Tobias Platen | add class LoadStore1(PortInterfaceBase) |
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2020-11-15 |
Cesar Strauss | Implement ResultConsumer and port the Shifter unit... |
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2020-11-14 |
Cesar Strauss | Move the DUT driver to within the test case process |
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2020-11-14 |
Cesar Strauss | Fix and enable the regspec test for the Shifter |
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2020-11-14 |
Luke Kenneth... | sigh, direction wrong in IOtypes litex core |
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2020-11-13 |
Luke Kenneth... | reduce number of nc in ls180 to 24 |
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