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soc.git
2020-08-12 Cole PoirierRevert "Remove mmu dir and associated mmu/test/ dir... commit | commitdiff | tree
2020-08-12 Cole PoirierRemove mmu dir and associated mmu/test/ dir commit | commitdiff | tree
2020-08-12 Cole PoirierRemove rst signals, fix len of hex Consts, fix variable... commit | commitdiff | tree
2020-08-12 Cole PoirierCreate dir experiment/mmu then mmu/test with skeleton... commit | commitdiff | tree
2020-08-12 Cole Poiriermmu.py add RecordObject classes from common.vhdl input... commit | commitdiff | tree
2020-08-12 Cole Poiriermmu.py remove TODOs for vhdl (others => '0') as they... commit | commitdiff | tree
2020-08-12 Cole Poiriermmu.py fix or(block of logic) to be (block of logic... commit | commitdiff | tree
2020-08-12 Cole Poiriermmu.py fix length of hex const https://bugs.libre-soc... commit | commitdiff | tree
2020-08-12 Cole Poiriermmu.py remove class AddrShifter commit | commitdiff | tree
2020-08-12 Cole PoirierFix typo in mmu.py commit | commitdiff | tree
2020-08-11 Cole Poiriermmu.py fix formatting, use Cat() where '&' in mmu.vhdl commit | commitdiff | tree
2020-08-11 Tobias Plateninitial version of L0CacheBuffer2 commit | commitdiff | tree
2020-08-11 Luke Kenneth... sigh, remove yet another int regfile read port commit | commitdiff | tree
2020-08-11 Luke Kenneth... massive reduction in gate count by using alternative... commit | commitdiff | tree
2020-08-11 Luke Kenneth... reduce regfile port usage for INT and FAST commit | commitdiff | tree
2020-08-11 Luke Kenneth... prepare write ports to be shared commit | commitdiff | tree
2020-08-11 Luke Kenneth... move write regfile picker creation to new function commit | commitdiff | tree
2020-08-11 Luke Kenneth... reduce regfile ports by creating separate STATE regfile commit | commitdiff | tree
2020-08-11 Luke Kenneth... whoops fix change of variable (state) msr/pc commit | commitdiff | tree
2020-08-11 Luke Kenneth... reducing regfile port usage by sharing read ports commit | commitdiff | tree
2020-08-10 Samuel A. Falvo IIWIP!! Make MUL pipeline proof run again. commit | commitdiff | tree
2020-08-10 Cole PoirierFix typo in mmu.py commit | commitdiff | tree
2020-08-10 Cole PoirierFix typo mmu.py commit | commitdiff | tree
2020-08-10 Cole PoirierGlobal search and replace (^, |), fixes bug 450 comment... commit | commitdiff | tree
2020-08-10 Cole Poirierfix bug 450 comments 8,9,10 commit | commitdiff | tree
2020-08-10 Cole PoirierFix bug 450 comment 7 commit | commitdiff | tree
2020-08-10 Cole Poiriermmu.py add line I forgot to translate from mmu.vhdl commit | commitdiff | tree
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-10 Cole Poiriermmu.vhdl translation to mmu.py 95 percent complete commit | commitdiff | tree
2020-08-09 Luke Kenneth... stop combinatorial loop in pi2ls commit | commitdiff | tree
2020-08-09 Luke Kenneth... write pulse in issuer commit | commitdiff | tree
2020-08-09 Luke Kenneth... fix combinatorial loop in ldst compunit commit | commitdiff | tree
2020-08-09 Luke Kenneth... use rising edge detection on st go_i/rel_o commit | commitdiff | tree
2020-08-09 Luke Kenneth... add logical test issuer case commit | commitdiff | tree
2020-08-09 Luke Kenneth... get rid of MSR read combinatorial loop commit | commitdiff | tree
2020-08-09 Luke Kenneth... delay go_st by one cycle, break combinatorial loop commit | commitdiff | tree
2020-08-09 Luke Kenneth... divwo case makes test_issuer stay busy! commit | commitdiff | tree
2020-08-09 Luke Kenneth... add extra divwo regression test commit | commitdiff | tree
2020-08-09 Luke Kenneth... compalu combinatorial loop detected commit | commitdiff | tree
2020-08-08 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-08 Cole PoirierUpdate test case_mulli commit | commitdiff | tree
2020-08-08 Tobias Platenaddr_split.py: shift bytes not bits commit | commitdiff | tree
2020-08-07 Cole PoirierUpdate test case_mulli commit | commitdiff | tree
2020-08-07 Cole PoirierUpdate test case_mulli, I think it now works correctly commit | commitdiff | tree
2020-08-07 Cole PoirierUpdate mulli to try to use immediates not registers commit | commitdiff | tree
2020-08-06 Cole PoirierFix mmu.py formatting commit | commitdiff | tree
2020-08-06 Cole PoirierFix formatting commit | commitdiff | tree
2020-08-06 Cole PoirierInitial commit of translation of microwatt mmu.vhdl... commit | commitdiff | tree
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov commit | commitdiff | tree
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov commit | commitdiff | tree
2020-08-06 Luke Kenneth... fix LDST PortInterface FSM interaction commit | commitdiff | tree
2020-08-06 Luke Kenneth... MULS on parameter b needed to check whether it was... commit | commitdiff | tree
2020-08-06 Cole PoirierAdd special test for case_mulli, apply autopep8 commit | commitdiff | tree
2020-08-05 Cole PoirierAdd test case_all_rb_close_to_ov commit | commitdiff | tree
2020-08-05 Cole PoirierRemove mulli from instrs in test case_all*, add TODO... commit | commitdiff | tree
2020-08-05 Cole PoirierAdd new test_values to tests case_all and case_all_rb_r... commit | commitdiff | tree
2020-08-05 Cole PoirierAdd second case_all test where rb is randint commit | commitdiff | tree
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-08-05 Tobias Platenundo changes that fix unit test, but do not solve anything commit | commitdiff | tree
2020-08-05 Luke Kenneth... rename ibus/dbus (shorten) commit | commitdiff | tree
2020-08-05 Luke Kenneth... clear sel on loadstore commit | commitdiff | tree
2020-08-05 Tobias Platenfix LDSTSplitter commit | commitdiff | tree
2020-08-05 Cole PoirierRemove madd* isns, added madd* isns test TODO commit | commitdiff | tree
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-05 Luke Kenneth... adding bus data width of 64 in litex sim doesnt work commit | commitdiff | tree
2020-08-05 Luke Kenneth... add div test cases into test_issuer.py commit | commitdiff | tree
2020-08-05 Luke Kenneth... add div FSM as default for test_issuer in verilog and... commit | commitdiff | tree
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-05 Jacob LifshayFixed div pipe with FSM commit | commitdiff | tree
2020-08-05 Cole PoirierFix pysim deprecation warning commit | commitdiff | tree
2020-08-05 Cole PoirierAdd case_all to MUL unit tests, remove duplicate test... commit | commitdiff | tree
2020-08-04 Luke Kenneth... read/set pc outside of FSM so that DMI interface can... commit | commitdiff | tree
2020-08-04 Luke Kenneth... swap over byte-reverse if/else in LDSTCompUnit commit | commitdiff | tree
2020-08-04 Luke Kenneth... tracked down byte-reversal in LDST ISACaller and LDSTCo... commit | commitdiff | tree
2020-08-04 Luke Kenneth... whitespace after autopep8 messed up commit | commitdiff | tree
2020-08-04 Luke Kenneth... msr and pc moved to "state" in PowerDecode2 commit | commitdiff | tree
2020-08-04 Luke Kenneth... whoops must output NIA not PC to debug DMI query in... commit | commitdiff | tree
2020-08-04 Luke Kenneth... allow instruction to run if initiated whilst "stopped... commit | commitdiff | tree
2020-08-04 Luke Kenneth... cycle through INT regs, read and debug in litex sim commit | commitdiff | tree
2020-08-04 Luke Kenneth... add DMI debug interface to libresoc litex sim commit | commitdiff | tree
2020-08-04 Luke Kenneth... single-step and print out PC using DMI in litex sim commit | commitdiff | tree
2020-08-04 Luke Kenneth... get litex sim to kick off a "STEP" via the DMI interfac... commit | commitdiff | tree
2020-08-04 Luke Kenneth... connect up a DMI FSM to litex sim commit | commitdiff | tree
2020-08-04 Luke Kenneth... more remove wildcard imports commit | commitdiff | tree
2020-08-04 Luke Kenneth... do not use wildcard imports commit | commitdiff | tree
2020-08-04 Luke Kenneth... adding litex sim experimentation. commit | commitdiff | tree
2020-08-04 Samuel A. Falvo IIRemove XXX; this seems done otherwise. commit | commitdiff | tree
2020-08-03 Luke Kenneth... add quick demo/test of reading DMI reg 9 commit | commitdiff | tree
2020-08-03 Luke Kenneth... add extra port for debug read of int regs via DMI commit | commitdiff | tree
2020-08-03 Luke Kenneth... pass state (MSR/PC) around between PowerDecode2, DMI... commit | commitdiff | tree
2020-08-03 Luke Kenneth... https://bugs.libre-soc.org/show_bug.cgi?id=446 commit | commitdiff | tree
2020-08-03 Luke Kenneth... use new soc.config.state CoreState class in DMI and... commit | commitdiff | tree
2020-08-03 Tobias PlatenLDSTSplitter: report exception commit | commitdiff | tree
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-08-03 Tobias PlatenTstDataMerger2 commit | commitdiff | tree
2020-08-03 Luke Kenneth... change over to DMI debug start/stop interface commit | commitdiff | tree
2020-08-03 Luke Kenneth... move debug to record commit | commitdiff | tree
2020-08-03 Samuel A. Falvo IIWIP: check MB > ME and select mask appropriately commit | commitdiff | tree
2020-08-02 Luke Kenneth... convert microwatt core_debug.vhdl to nmigen commit | commitdiff | tree
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