soc.git
2020-05-24 Luke Kenneth... add OP_CMPB formal proof
2020-05-24 Michael NolanAssert that ctr is only written when needed
2020-05-24 Luke Kenneth... split out Popcount into separate module: visually it...
2020-05-24 Luke Kenneth... copy code for MTMSR from microwatt into comments
2020-05-24 Luke Kenneth... add links for trap main stage
2020-05-24 Luke Kenneth... add untested OP_MTMSR and OP_MFMSR
2020-05-24 Luke Kenneth... update to new CSV files in submodule
2020-05-24 Luke Kenneth... add MFMSR and MTMSRD enums to Function
2020-05-24 Luke Kenneth... comment and add links to branch formal proof
2020-05-24 Luke Kenneth... add copy of bpermd proof to logical formal proof (not...
2020-05-24 Luke Kenneth... track down overwrite of variable b
2020-05-24 Michael NolanFix proof of bpermd module
2020-05-24 Michael NolanFix bpermd and make tests pass
2020-05-24 Michael NolanFix test_pipe_caller to conform to new Data() interface...
2020-05-24 Luke Kenneth... add stub regfiles.py
2020-05-24 Luke Kenneth... hmm...
2020-05-24 Luke Kenneth... add very rapid DummyALU for test purposes in MultiCompUnit
2020-05-24 Luke Kenneth... comments on branch pipeline
2020-05-24 Luke Kenneth... convert CR pipeline to Data.ok
2020-05-24 Luke Kenneth... convert ALU to output Data on int reg
2020-05-24 Luke Kenneth... convert logical to output Data on int reg
2020-05-24 Luke Kenneth... start using Data in pipelines
2020-05-24 Luke Kenneth... cleanup/code-munge on ALU main stage proof
2020-05-24 Luke Kenneth... error in alu output stage formal proof setup
2020-05-24 Luke Kenneth... output registers need to be Data type (consistently)
2020-05-24 Luke Kenneth... spelling mistake in variable
2020-05-24 Luke Kenneth... TODO mention OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth... add RA to trap pipeline, for OP_MTMSR/OP_MFMSR
2020-05-24 Luke Kenneth... move docstring to wiki for compunit
2020-05-23 colepoirierAdded branch and shift_rot imports to fu/compunits...
2020-05-23 Cesar StraussAdd a few test cases with zero_a set, in combination...
2020-05-23 Cesar StraussAllow zero_a to be set when simulating an operation
2020-05-23 Luke Kenneth... add input / output stage missing modules
2020-05-23 Luke Kenneth... common function for op zero and op immed
2020-05-23 Cesar StraussChoose between RA (src1) and zero immediate, conditione...
2020-05-23 Luke Kenneth... update docs on compunits
2020-05-23 Luke Kenneth... remove extraneous test_isel
2020-05-23 Luke Kenneth... add comments
2020-05-23 Luke Kenneth... document purpose of regspec module
2020-05-23 Luke Kenneth... split out RegSpecs into separate module
2020-05-23 Luke Kenneth... add TODO on multi-in multi-out Function Units
2020-05-23 Luke Kenneth... split out RegSpec API into separate class (TODO: move...
2020-05-23 Luke Kenneth... add notes on FunctionUnit API
2020-05-23 Luke Kenneth... make MultiCompUnit and testing ALU use regspec API...
2020-05-23 Luke Kenneth... remove unneeded imports
2020-05-23 Luke Kenneth... make demo/test ALU look like nmigen pipeline API
2020-05-23 Luke Kenneth... add stub DataMerger class
2020-05-23 Luke Kenneth... add link to regspecs on wiki
2020-05-23 Luke Kenneth... add regspec capability to MultiCompUnit
2020-05-23 Michael NolanModify proof of isel to use full CR register
2020-05-23 Michael NolanAdd test_isel
2020-05-23 Luke Kenneth... make immediate-or-RA selection optional based on awaren...
2020-05-23 Luke Kenneth... start to morph MultiCompUnit to take "regspec" as the...
2020-05-23 Luke Kenneth... add CR_ISEL formal proof to CR pipeline
2020-05-23 Luke Kenneth... add CR_ISEL (and unit test) to CR pipeline
2020-05-23 Luke Kenneth... update to (corrected) csv files for CR_ISEL
2020-05-23 Luke Kenneth... select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
2020-05-23 Luke Kenneth... add gitignore
2020-05-23 Luke Kenneth... CR field on Br input data is specd as 0:3 range
2020-05-23 Luke Kenneth... add b to CR pipe input data, for isel
2020-05-22 Luke Kenneth... add TODO and link to SHIFT_ROT formal bugreport
2020-05-22 Luke Kenneth... remove xer.so from ShiftRot formal proof
2020-05-22 Luke Kenneth... remove sticky overflow from Shift Rot pipeline
2020-05-22 Luke Kenneth... test branch ctr ok flag
2020-05-22 Luke Kenneth... cleaner way to test link register ok
2020-05-22 Luke Kenneth... whitespace
2020-05-22 Michael NolanFix link handling in branch proof
2020-05-22 Michael NolanUpdate to latest wiki version - fix cr0 input for OP_CNTZ
2020-05-22 Luke Kenneth... variable-name munging for branch formal
2020-05-22 Michael NolanAdd formal proof for branch unit, fix bug with bcreg
2020-05-22 Luke Kenneth... cleanup logical pipe formal proof
2020-05-22 Luke Kenneth... split out Logical Input and Output stages to common...
2020-05-22 Luke Kenneth... div probably uses ALU not Logical, needs double-checkin...
2020-05-22 Luke Kenneth... update comments for ALUCompUnit
2020-05-22 Luke Kenneth... soc.fu.logical.input_stage no different from ALU: delete
2020-05-22 Luke Kenneth... covert ALU FU to CommonInputStage
2020-05-22 Luke Kenneth... create common input pipe spec to avoid code-duplication
2020-05-22 Luke Kenneth... move CR over to CompCROpSubset
2020-05-22 Michael NolanConvert branch unit to new CR interface
2020-05-22 Michael NolanComplete CR proof
2020-05-22 Luke Kenneth... increase fu-fu test matrix size
2020-05-22 Luke Kenneth... remove unneeded code
2020-05-22 Luke Kenneth... rename ShiftRot to Mul in fu mul test
2020-05-22 Luke Kenneth... rename Logical to Div in fu div test
2020-05-22 Luke Kenneth... cookie-cut start on div pipe
2020-05-22 Luke Kenneth... add cookie-cut mul pipeline template
2020-05-22 Luke Kenneth... whitespace
2020-05-22 Luke Kenneth... over 80 chars
2020-05-22 Luke Kenneth... comment tidyup
2020-05-22 Luke Kenneth... use CompBROpSubset and reduce it down in size (remove...
2020-05-22 Luke Kenneth... code-shuffle
2020-05-22 Luke Kenneth... remove accidentally added branch input stage
2020-05-22 Tobias Platenfix ModuleNotFoundError
2020-05-21 Luke Kenneth... add fu logical_input_record.py
2020-05-21 Luke Kenneth... update CROutputData to use Data()
2020-05-21 Luke Kenneth... update comments
2020-05-21 Luke Kenneth... whitespace cleanup
2020-05-21 Luke Kenneth... whitespace cleanup
2020-05-21 Luke Kenneth... remove input_cr, output_cr and is_32bit from CompCROpSubset
2020-05-21 Luke Kenneth... add read_cr_whole and write_cr_whole to CompCROpSubset
next