Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / config /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 80 endian.py
-rw-r--r-- 1274 ifetch.py
-rw-r--r-- 2236 loadstore.py
-rw-r--r-- 4608 pinouts.py
-rw-r--r-- 165 state.py
drwxr-xr-x - test