Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / alu /
drwxr-xr-x   ..
-rw-r--r-- 0 __init__.py
-rw-r--r-- 1162 alu_input_record.py
drwxr-xr-x - formal
-rw-r--r-- 833 input_stage.py
-rw-r--r-- 8419 main_stage.py
-rw-r--r-- 1408 output_stage.py
-rw-r--r-- 1130 pipe_data.py
-rw-r--r-- 1802 pipeline.py
drwxr-xr-x - test