c4m/vhdl/jtag/c4m_jtag_pkg.vhdl

   1 -- Package of jtag support code from the Chips4Makers project
   2 library ieee;
   3 use ieee.std_logic_1164.ALL;
   4
   5 package c4m_jtag is
   6   type SRIOMODE_TYPE is (
   7     SR_Through, -- Connect core signal to pad signals
   8     SR_2Pad,    -- Connect BD to pad
   9     SR_2Core,   -- Connect BD to core
  10     SR_Z        -- pad is high impedance
  11   );
  12   type SRSAMPLEMODE_TYPE is (
  13     SR_Normal,  -- No sampling or shifting
  14     SR_Sample,  -- Sample IO state in BD SR on rising edge of TCK
  15     SR_Update,  -- Update BD from SR on falling edge of TCK
  16     SR_Shift    -- Shift the BD SR
  17   );
  18
  19   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
  20   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
  21   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
  22   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
  23
  24   component c4m_jtag_tap_fsm is
  25     port (
  26       -- The TAP signals
  27       TCK:      in std_logic;
  28       TMS:      in std_logic;
  29       TRST_N:   in std_logic;
  30
  31       -- The state outputs
  32       RESET:    out std_logic;
  33       ISDR:     out std_logic;
  34       ISIR:     out std_logic;
  35       CAPTURE:  out std_logic;
  36       SHIFT:    out std_logic;
  37       UPDATE:   out std_logic
  38     );
  39   end component c4m_jtag_tap_fsm;
  40
  41   component c4m_jtag_irblock is
  42     generic (
  43       IR_WIDTH: integer := 2
  44     );
  45     port (
  46       -- needed TAP signals
  47       TCK:      in std_logic;
  48       TDI:      in std_logic;
  49       TDO:      out std_logic;
  50       TDO_EN:   out std_logic;
  51
  52       -- instruction register
  53       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
  54
  55       -- actions
  56       RESET:    in std_logic;
  57       CAPTURE:  in std_logic;
  58       SHIFT:    in std_logic;
  59       UPDATE:   in std_logic
  60     );
  61   end component c4m_jtag_irblock;
  62
  63   component c4m_jtag_idblock is
  64     generic (
  65       IR_WIDTH:         integer := 2;
  66
  67       -- The default MANUFACTURING ID is not representing a valid
  68       -- manufacturer according to the JTAG standard
  69       MANUFACTURER:     std_logic_vector(10 downto 0) := "10001111111";
  70       PART_NUMBER:      std_logic_vector(15 downto 0) := "0000000000000001";
  71       VERSION:          std_logic_vector(3 downto 0) := "0000"
  72     );
  73     port (
  74       -- needed TAP signals
  75       TCK:      in std_logic;
  76       TDI:      in std_logic;
  77       TDO:      out std_logic;
  78       TDO_EN:   out std_logic;
  79
  80       -- The instruction
  81       IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
  82
  83       -- actions
  84       CAPTURE:  in std_logic;
  85       SHIFT:    in std_logic;
  86       UPDATE:   in std_logic
  87     );
  88   end component c4m_jtag_idblock;
  89
  90   component c4m_jtag_iocell is
  91     port (
  92       -- core connections
  93       CORE_IN:  out std_logic;
  94       CORE_OUT: in std_logic;
  95       CORE_EN:  in std_logic;
  96
  97       -- pad connections
  98       PAD_IN:   in std_logic;
  99       PAD_OUT:  out std_logic;
 100       PAD_EN:   out std_logic;
 101
 102       -- BD shift register
 103       BDSR_IN:  in std_logic;
 104       BDSR_OUT: out std_logic;
 105
 106       -- Mode of I/O cell
 107       IOMODE:   in SRIOMODE_TYPE;
 108       SAMPLEMODE: in SRSAMPLEMODE_TYPE;
 109       TCK:      in std_logic
 110     );
 111   end component c4m_jtag_iocell;
 112
 113   component c4m_jtag_ioblock is
 114     generic (
 115       IR_WIDTH: integer := 2;
 116       IOS:      integer := 1
 117     );
 118     port (
 119       -- needed TAP signals
 120       TCK:      in std_logic;
 121       TDI:      in std_logic;
 122       TDO:      out std_logic;
 123       TDO_EN:   out std_logic;
 124
 125       -- The instruction
 126       IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
 127
 128       -- What action to perform
 129       CAPTURE:  in std_logic;
 130       SHIFT:    in std_logic;
 131       UPDATE:   in std_logic;
 132
 133       -- The I/O access ports
 134       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 135       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 136       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 137
 138       -- The pad connections
 139       PAD_OUT:  out std_logic_vector(IOS-1 downto 0);
 140       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 141       PAD_EN:   out std_logic_vector(IOS-1 downto 0)
 142     );
 143   end component c4m_jtag_ioblock;
 144
 145   component c4m_jtag_tap_controller is
 146     generic (
 147       DEBUG:            boolean := false;
 148
 149       IR_WIDTH:         integer := 2;
 150       IOS:              integer := 1;
 151
 152       -- The default MANUFACTURING ID is not representing a valid
 153       -- manufacturer according to the JTAG standard
 154       MANUFACTURER:     std_logic_vector(10 downto 0) := "10001111111";
 155       PART_NUMBER:      std_logic_vector(15 downto 0) := "0000000000000001";
 156       VERSION:          std_logic_vector(3 downto 0) := "0000"
 157     );
 158     port (
 159       -- The TAP signals
 160       TCK:      in std_logic;
 161       TMS:      in std_logic;
 162       TDI:      in std_logic;
 163       TDO:      out std_logic;
 164       TRST_N:   in std_logic;
 165
 166       -- The Instruction Register
 167       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
 168
 169       -- The FSM state indicators
 170       RESET:    out std_logic; -- In reset state
 171       CAPTURE:  out std_logic; -- In DR_Capture state
 172       SHIFT:    out std_logic; -- In DR_Shift state
 173       UPDATE:   out std_logic; -- In DR_Update state
 174       -- The I/O access ports
 175       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 176       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 177       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 178
 179       -- The pad connections
 180       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 181       PAD_EN:   out std_logic_vector(IOS-1 downto 0);
 182       PAD_OUT:  out std_logic_vector(IOS-1 downto 0)
 183     );
 184   end component c4m_jtag_tap_controller;
 185 end c4m_jtag;
 186
 187 package body c4m_jtag is
 188   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
 189     variable return_vector: std_logic_vector(width-1 downto 0);
 190   begin
 191     return_vector := (others => '1');
 192     return return_vector;
 193   end;
 194
 195   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
 196     variable return_vector: std_logic_vector(width-1 downto 0);
 197   begin
 198     return_vector := (0 => '1', others => '0');
 199     return return_vector;
 200   end;
 201
 202   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
 203     variable return_vector: std_logic_vector(width-1 downto 0);
 204   begin
 205     return_vector := (1 => '1', others => '0');
 206     return return_vector;
 207   end;
 208
 209   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
 210     variable return_vector: std_logic_vector(width-1 downto 0);
 211   begin
 212     return_vector := (others => '0');
 213     return return_vector;
 214   end;
 215 end package body;