src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  37         #m.submodules.get_op_in = self.in_op
  38         m.submodules.get_op_out = self.out_op
  39         with m.If(self.out_decode):
  40             m.d.comb += [
  41                 self.out_op.decode(self.in_op.v),
  42             ]
  43         return m
  44
  45
  46 class FPGetOp(FPState):
  47     """ gets operand
  48     """
  49
  50     def __init__(self, in_state, out_state, in_op, width):
  51         FPState.__init__(self, in_state)
  52         self.out_state = out_state
  53         self.mod = FPGetOpMod(width)
  54         self.in_op = in_op
  55         self.out_op = FPNumIn(in_op, width)
  56         self.out_decode = Signal(reset_less=True)
  57
  58     def setup(self, m, in_op):
  59         """ links module to inputs and outputs
  60         """
  61         setattr(m.submodules, self.state_from, self.mod)
  62         m.d.comb += self.mod.in_op.copy(in_op)
  63         m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
  64         m.d.comb += self.out_decode.eq(self.mod.out_decode)
  65
  66     def action(self, m):
  67         with m.If(self.out_decode):
  68             m.next = self.out_state
  69             m.d.sync += [
  70                 self.in_op.ack.eq(0),
  71                 self.out_op.copy(self.mod.out_op)
  72             ]
  73         with m.Else():
  74             m.d.sync += self.in_op.ack.eq(1)
  75
  76
  77 class FPAddSpecialCasesMod:
  78     """ special cases: NaNs, infs, zeros, denormalised
  79         NOTE: some of these are unique to add.  see "Special Operations"
  80         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  81     """
  82
  83     def __init__(self, width):
  84         self.in_a = FPNumBase(width)
  85         self.in_b = FPNumBase(width)
  86         self.out_z = FPNumOut(width, False)
  87         self.out_do_z = Signal(reset_less=True)
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91
  92         m.submodules.sc_in_a = self.in_a
  93         m.submodules.sc_in_b = self.in_b
  94         m.submodules.sc_out_z = self.out_z
  95
  96         s_nomatch = Signal()
  97         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
  98
  99         m_match = Signal()
 100         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 101
 102         # if a is NaN or b is NaN return NaN
 103         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 104             m.d.comb += self.out_do_z.eq(1)
 105             m.d.comb += self.out_z.nan(0)
 106
 107         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 108         # under review
 109
 110         ## if a is zero and b is NaN return -b
 111         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 112         #    m.d.comb += self.out_do_z.eq(1)
 113         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 114
 115         ## if b is zero and a is NaN return -a
 116         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 117         #    m.d.comb += self.out_do_z.eq(1)
 118         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 119
 120         ## if a is -zero and b is NaN return -b
 121         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 122         #    m.d.comb += self.out_do_z.eq(1)
 123         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 124
 125         ## if b is -zero and a is NaN return -a
 126         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 127         #    m.d.comb += self.out_do_z.eq(1)
 128         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 129
 130         # if a is inf return inf (or NaN)
 131         with m.Elif(self.in_a.is_inf):
 132             m.d.comb += self.out_do_z.eq(1)
 133             m.d.comb += self.out_z.inf(self.in_a.s)
 134             # if a is inf and signs don't match return NaN
 135             with m.If(self.in_b.exp_128 & s_nomatch):
 136                 m.d.comb += self.out_z.nan(0)
 137
 138         # if b is inf return inf
 139         with m.Elif(self.in_b.is_inf):
 140             m.d.comb += self.out_do_z.eq(1)
 141             m.d.comb += self.out_z.inf(self.in_b.s)
 142
 143         # if a is zero and b zero return signed-a/b
 144         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 145             m.d.comb += self.out_do_z.eq(1)
 146             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 147                                           self.in_b.e,
 148                                           self.in_b.m[3:-1])
 149
 150         # if a is zero return b
 151         with m.Elif(self.in_a.is_zero):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 154                                       self.in_b.m[3:-1])
 155
 156         # if b is zero return a
 157         with m.Elif(self.in_b.is_zero):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 160                                       self.in_a.m[3:-1])
 161
 162         # if a equal to -b return zero (+ve zero)
 163         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.zero(0)
 166
 167         # Denormalised Number checks
 168         with m.Else():
 169             m.d.comb += self.out_do_z.eq(0)
 170
 171         return m
 172
 173
 174 class FPID:
 175     def __init__(self, id_wid):
 176         self.id_wid = id_wid
 177         if self.id_wid:
 178             self.in_mid = Signal(width, reset_less)
 179             self.out_mid = Signal(width, reset_less)
 180         else:
 181             self.in_mid = None
 182             self.out_mid = None
 183
 184     def idsync(self, m):
 185         if self.id_wid:
 186             m.d.sync += self.out_mid.eq(self.in_mid)
 187
 188
 189 class FPAddSpecialCases(FPState, FPID):
 190     """ special cases: NaNs, infs, zeros, denormalised
 191         NOTE: some of these are unique to add.  see "Special Operations"
 192         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 193     """
 194
 195     def __init__(self, width, id_wid):
 196         FPState.__init__(self, "special_cases")
 197         FPID.__init__(self, id_wid)
 198         self.mod = FPAddSpecialCasesMod(width)
 199         self.out_z = FPNumOut(width, False)
 200         self.out_do_z = Signal(reset_less=True)
 201
 202     def setup(self, m, in_a, in_b, in_mid):
 203         """ links module to inputs and outputs
 204         """
 205         m.submodules.specialcases = self.mod
 206         m.d.comb += self.mod.in_a.copy(in_a)
 207         m.d.comb += self.mod.in_b.copy(in_b)
 208         #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
 209         m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
 210         if self.in_mid:
 211             m.d.comb += self.in_mid.eq(in_mid)
 212
 213     def action(self, m):
 214         self.idsync(m)
 215         with m.If(self.out_do_z):
 216             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 217             m.next = "put_z"
 218         with m.Else():
 219             m.next = "denormalise"
 220
 221
 222 class FPAddDeNormMod(FPState):
 223
 224     def __init__(self, width):
 225         self.in_a = FPNumBase(width)
 226         self.in_b = FPNumBase(width)
 227         self.out_a = FPNumBase(width)
 228         self.out_b = FPNumBase(width)
 229
 230     def elaborate(self, platform):
 231         m = Module()
 232         m.submodules.denorm_in_a = self.in_a
 233         m.submodules.denorm_in_b = self.in_b
 234         m.submodules.denorm_out_a = self.out_a
 235         m.submodules.denorm_out_b = self.out_b
 236         # hmmm, don't like repeating identical code
 237         m.d.comb += self.out_a.copy(self.in_a)
 238         with m.If(self.in_a.exp_n127):
 239             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 240         with m.Else():
 241             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 242
 243         m.d.comb += self.out_b.copy(self.in_b)
 244         with m.If(self.in_b.exp_n127):
 245             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 246         with m.Else():
 247             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 248
 249         return m
 250
 251
 252 class FPAddDeNorm(FPState, FPID):
 253
 254     def __init__(self, width, id_wid):
 255         FPState.__init__(self, "denormalise")
 256         FPID.__init__(self, id_wid)
 257         self.mod = FPAddDeNormMod(width)
 258         self.out_a = FPNumBase(width)
 259         self.out_b = FPNumBase(width)
 260
 261     def setup(self, m, in_a, in_b, in_mid):
 262         """ links module to inputs and outputs
 263         """
 264         m.submodules.denormalise = self.mod
 265         m.d.comb += self.mod.in_a.copy(in_a)
 266         m.d.comb += self.mod.in_b.copy(in_b)
 267         if self.in_mid:
 268             m.d.comb += self.in_mid.eq(in_mid)
 269
 270     def action(self, m):
 271         self.idsync(m)
 272         # Denormalised Number checks
 273         m.next = "align"
 274         m.d.sync += self.out_a.copy(self.mod.out_a)
 275         m.d.sync += self.out_b.copy(self.mod.out_b)
 276
 277
 278 class FPAddAlignMultiMod(FPState):
 279
 280     def __init__(self, width):
 281         self.in_a = FPNumBase(width)
 282         self.in_b = FPNumBase(width)
 283         self.out_a = FPNumIn(None, width)
 284         self.out_b = FPNumIn(None, width)
 285         self.exp_eq = Signal(reset_less=True)
 286
 287     def elaborate(self, platform):
 288         # This one however (single-cycle) will do the shift
 289         # in one go.
 290
 291         m = Module()
 292
 293         m.submodules.align_in_a = self.in_a
 294         m.submodules.align_in_b = self.in_b
 295         m.submodules.align_out_a = self.out_a
 296         m.submodules.align_out_b = self.out_b
 297
 298         # NOTE: this does *not* do single-cycle multi-shifting,
 299         #       it *STAYS* in the align state until exponents match
 300
 301         # exponent of a greater than b: shift b down
 302         m.d.comb += self.exp_eq.eq(0)
 303         m.d.comb += self.out_a.copy(self.in_a)
 304         m.d.comb += self.out_b.copy(self.in_b)
 305         agtb = Signal(reset_less=True)
 306         altb = Signal(reset_less=True)
 307         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 308         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 309         with m.If(agtb):
 310             m.d.comb += self.out_b.shift_down(self.in_b)
 311         # exponent of b greater than a: shift a down
 312         with m.Elif(altb):
 313             m.d.comb += self.out_a.shift_down(self.in_a)
 314         # exponents equal: move to next stage.
 315         with m.Else():
 316             m.d.comb += self.exp_eq.eq(1)
 317         return m
 318
 319
 320 class FPAddAlignMulti(FPState, FPID):
 321
 322     def __init__(self, width, id_wid):
 323         FPID.__init__(self, id_wid)
 324         FPState.__init__(self, "align")
 325         self.mod = FPAddAlignMultiMod(width)
 326         self.out_a = FPNumIn(None, width)
 327         self.out_b = FPNumIn(None, width)
 328         self.exp_eq = Signal(reset_less=True)
 329
 330     def setup(self, m, in_a, in_b, in_mid):
 331         """ links module to inputs and outputs
 332         """
 333         m.submodules.align = self.mod
 334         m.d.comb += self.mod.in_a.copy(in_a)
 335         m.d.comb += self.mod.in_b.copy(in_b)
 336         #m.d.comb += self.out_a.copy(self.mod.out_a)
 337         #m.d.comb += self.out_b.copy(self.mod.out_b)
 338         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 339         if self.in_mid:
 340             m.d.comb += self.in_mid.eq(in_mid)
 341
 342     def action(self, m):
 343         self.idsync(m)
 344         m.d.sync += self.out_a.copy(self.mod.out_a)
 345         m.d.sync += self.out_b.copy(self.mod.out_b)
 346         with m.If(self.exp_eq):
 347             m.next = "add_0"
 348
 349
 350 class FPAddAlignSingleMod:
 351
 352     def __init__(self, width):
 353         self.width = width
 354         self.in_a = FPNumBase(width)
 355         self.in_b = FPNumBase(width)
 356         self.out_a = FPNumIn(None, width)
 357         self.out_b = FPNumIn(None, width)
 358
 359     def elaborate(self, platform):
 360         """ Aligns A against B or B against A, depending on which has the
 361             greater exponent.  This is done in a *single* cycle using
 362             variable-width bit-shift
 363
 364             the shifter used here is quite expensive in terms of gates.
 365             Mux A or B in (and out) into temporaries, as only one of them
 366             needs to be aligned against the other
 367         """
 368         m = Module()
 369
 370         m.submodules.align_in_a = self.in_a
 371         m.submodules.align_in_b = self.in_b
 372         m.submodules.align_out_a = self.out_a
 373         m.submodules.align_out_b = self.out_b
 374
 375         # temporary (muxed) input and output to be shifted
 376         t_inp = FPNumBase(self.width)
 377         t_out = FPNumIn(None, self.width)
 378         espec = (len(self.in_a.e), True)
 379         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 380         m.submodules.align_t_in = t_inp
 381         m.submodules.align_t_out = t_out
 382         m.submodules.multishift_r = msr
 383
 384         ediff = Signal(espec, reset_less=True)
 385         ediffr = Signal(espec, reset_less=True)
 386         tdiff = Signal(espec, reset_less=True)
 387         elz = Signal(reset_less=True)
 388         egz = Signal(reset_less=True)
 389
 390         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 391         m.d.comb += msr.inp.eq(t_inp.m)
 392         m.d.comb += msr.diff.eq(tdiff)
 393         m.d.comb += t_out.m.eq(msr.m)
 394         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 395         m.d.comb += t_out.s.eq(t_inp.s)
 396
 397         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 398         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 399         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 400         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 401
 402         # default: A-exp == B-exp, A and B untouched (fall through)
 403         m.d.comb += self.out_a.copy(self.in_a)
 404         m.d.comb += self.out_b.copy(self.in_b)
 405         # only one shifter (muxed)
 406         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 407         # exponent of a greater than b: shift b down
 408         with m.If(egz):
 409             m.d.comb += [t_inp.copy(self.in_b),
 410                          tdiff.eq(ediff),
 411                          self.out_b.copy(t_out),
 412                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 413                         ]
 414         # exponent of b greater than a: shift a down
 415         with m.Elif(elz):
 416             m.d.comb += [t_inp.copy(self.in_a),
 417                          tdiff.eq(ediffr),
 418                          self.out_a.copy(t_out),
 419                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 420                         ]
 421         return m
 422
 423
 424 class FPAddAlignSingle(FPState, FPID):
 425
 426     def __init__(self, width, id_wid):
 427         FPState.__init__(self, "align")
 428         FPID.__init__(self, id_wid)
 429         self.mod = FPAddAlignSingleMod(width)
 430         self.out_a = FPNumIn(None, width)
 431         self.out_b = FPNumIn(None, width)
 432
 433     def setup(self, m, in_a, in_b, in_mid):
 434         """ links module to inputs and outputs
 435         """
 436         m.submodules.align = self.mod
 437         m.d.comb += self.mod.in_a.copy(in_a)
 438         m.d.comb += self.mod.in_b.copy(in_b)
 439         if self.in_mid:
 440             m.d.comb += self.in_mid.eq(in_mid)
 441
 442     def action(self, m):
 443         self.idsync(m)
 444         # NOTE: could be done as comb
 445         m.d.sync += self.out_a.copy(self.mod.out_a)
 446         m.d.sync += self.out_b.copy(self.mod.out_b)
 447         m.next = "add_0"
 448
 449
 450 class FPAddStage0Mod:
 451
 452     def __init__(self, width):
 453         self.in_a = FPNumBase(width)
 454         self.in_b = FPNumBase(width)
 455         self.in_z = FPNumBase(width, False)
 456         self.out_z = FPNumBase(width, False)
 457         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 458
 459     def elaborate(self, platform):
 460         m = Module()
 461         m.submodules.add0_in_a = self.in_a
 462         m.submodules.add0_in_b = self.in_b
 463         m.submodules.add0_out_z = self.out_z
 464
 465         m.d.comb += self.out_z.e.eq(self.in_a.e)
 466
 467         # store intermediate tests (and zero-extended mantissas)
 468         seq = Signal(reset_less=True)
 469         mge = Signal(reset_less=True)
 470         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 471         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 472         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 473                      mge.eq(self.in_a.m >= self.in_b.m),
 474                      am0.eq(Cat(self.in_a.m, 0)),
 475                      bm0.eq(Cat(self.in_b.m, 0))
 476                     ]
 477         # same-sign (both negative or both positive) add mantissas
 478         with m.If(seq):
 479             m.d.comb += [
 480                 self.out_tot.eq(am0 + bm0),
 481                 self.out_z.s.eq(self.in_a.s)
 482             ]
 483         # a mantissa greater than b, use a
 484         with m.Elif(mge):
 485             m.d.comb += [
 486                 self.out_tot.eq(am0 - bm0),
 487                 self.out_z.s.eq(self.in_a.s)
 488             ]
 489         # b mantissa greater than a, use b
 490         with m.Else():
 491             m.d.comb += [
 492                 self.out_tot.eq(bm0 - am0),
 493                 self.out_z.s.eq(self.in_b.s)
 494         ]
 495         return m
 496
 497
 498 class FPAddStage0(FPState, FPID):
 499     """ First stage of add.  covers same-sign (add) and subtract
 500         special-casing when mantissas are greater or equal, to
 501         give greatest accuracy.
 502     """
 503
 504     def __init__(self, width, id_wid):
 505         FPState.__init__(self, "add_0")
 506         FPID.__init__(self, id_wid)
 507         self.mod = FPAddStage0Mod(width)
 508         self.out_z = FPNumBase(width, False)
 509         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 510
 511     def setup(self, m, in_a, in_b, in_mid):
 512         """ links module to inputs and outputs
 513         """
 514         m.submodules.add0 = self.mod
 515         m.d.comb += self.mod.in_a.copy(in_a)
 516         m.d.comb += self.mod.in_b.copy(in_b)
 517         if self.in_mid:
 518             m.d.comb += self.in_mid.eq(in_mid)
 519
 520     def action(self, m):
 521         self.idsync(m)
 522         # NOTE: these could be done as combinatorial (merge add0+add1)
 523         m.d.sync += self.out_z.copy(self.mod.out_z)
 524         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 525         m.next = "add_1"
 526
 527
 528 class FPAddStage1Mod(FPState):
 529     """ Second stage of add: preparation for normalisation.
 530         detects when tot sum is too big (tot[27] is kinda a carry bit)
 531     """
 532
 533     def __init__(self, width):
 534         self.out_norm = Signal(reset_less=True)
 535         self.in_z = FPNumBase(width, False)
 536         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 537         self.out_z = FPNumBase(width, False)
 538         self.out_of = Overflow()
 539
 540     def elaborate(self, platform):
 541         m = Module()
 542         #m.submodules.norm1_in_overflow = self.in_of
 543         #m.submodules.norm1_out_overflow = self.out_of
 544         #m.submodules.norm1_in_z = self.in_z
 545         #m.submodules.norm1_out_z = self.out_z
 546         m.d.comb += self.out_z.copy(self.in_z)
 547         # tot[27] gets set when the sum overflows. shift result down
 548         with m.If(self.in_tot[-1]):
 549             m.d.comb += [
 550                 self.out_z.m.eq(self.in_tot[4:]),
 551                 self.out_of.m0.eq(self.in_tot[4]),
 552                 self.out_of.guard.eq(self.in_tot[3]),
 553                 self.out_of.round_bit.eq(self.in_tot[2]),
 554                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 555                 self.out_z.e.eq(self.in_z.e + 1)
 556         ]
 557         # tot[27] zero case
 558         with m.Else():
 559             m.d.comb += [
 560                 self.out_z.m.eq(self.in_tot[3:]),
 561                 self.out_of.m0.eq(self.in_tot[3]),
 562                 self.out_of.guard.eq(self.in_tot[2]),
 563                 self.out_of.round_bit.eq(self.in_tot[1]),
 564                 self.out_of.sticky.eq(self.in_tot[0])
 565         ]
 566         return m
 567
 568
 569 class FPAddStage1(FPState, FPID):
 570
 571     def __init__(self, width, id_wid):
 572         FPState.__init__(self, "add_1")
 573         FPID.__init__(self, id_wid)
 574         self.mod = FPAddStage1Mod(width)
 575         self.out_z = FPNumBase(width, False)
 576         self.out_of = Overflow()
 577         self.norm_stb = Signal()
 578
 579     def setup(self, m, in_tot, in_z, in_mid):
 580         """ links module to inputs and outputs
 581         """
 582         m.submodules.add1 = self.mod
 583         m.submodules.add1_out_overflow = self.out_of
 584
 585         m.d.comb += self.mod.in_z.copy(in_z)
 586         m.d.comb += self.mod.in_tot.eq(in_tot)
 587
 588         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 589
 590         if self.in_mid:
 591             m.d.comb += self.in_mid.eq(in_mid)
 592
 593     def action(self, m):
 594         self.idsync(m)
 595         m.d.sync += self.out_of.copy(self.mod.out_of)
 596         m.d.sync += self.out_z.copy(self.mod.out_z)
 597         m.d.sync += self.norm_stb.eq(1)
 598         m.next = "normalise_1"
 599
 600
 601 class FPNorm1ModSingle:
 602
 603     def __init__(self, width):
 604         self.width = width
 605         self.in_select = Signal(reset_less=True)
 606         self.out_norm = Signal(reset_less=True)
 607         self.in_z = FPNumBase(width, False)
 608         self.in_of = Overflow()
 609         self.temp_z = FPNumBase(width, False)
 610         self.temp_of = Overflow()
 611         self.out_z = FPNumBase(width, False)
 612         self.out_of = Overflow()
 613
 614     def elaborate(self, platform):
 615         m = Module()
 616
 617         mwid = self.out_z.m_width+2
 618         pe = PriorityEncoder(mwid)
 619         m.submodules.norm_pe = pe
 620
 621         m.submodules.norm1_out_z = self.out_z
 622         m.submodules.norm1_out_overflow = self.out_of
 623         m.submodules.norm1_temp_z = self.temp_z
 624         m.submodules.norm1_temp_of = self.temp_of
 625         m.submodules.norm1_in_z = self.in_z
 626         m.submodules.norm1_in_overflow = self.in_of
 627
 628         in_z = FPNumBase(self.width, False)
 629         in_of = Overflow()
 630         m.submodules.norm1_insel_z = in_z
 631         m.submodules.norm1_insel_overflow = in_of
 632
 633         espec = (len(in_z.e), True)
 634         ediff_n126 = Signal(espec, reset_less=True)
 635         msr = MultiShiftRMerge(mwid, espec)
 636         m.submodules.multishift_r = msr
 637
 638         # select which of temp or in z/of to use
 639         with m.If(self.in_select):
 640             m.d.comb += in_z.copy(self.in_z)
 641             m.d.comb += in_of.copy(self.in_of)
 642         with m.Else():
 643             m.d.comb += in_z.copy(self.temp_z)
 644             m.d.comb += in_of.copy(self.temp_of)
 645         # initialise out from in (overridden below)
 646         m.d.comb += self.out_z.copy(in_z)
 647         m.d.comb += self.out_of.copy(in_of)
 648         # normalisation increase/decrease conditions
 649         decrease = Signal(reset_less=True)
 650         increase = Signal(reset_less=True)
 651         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 652         m.d.comb += increase.eq(in_z.exp_lt_n126)
 653         m.d.comb += self.out_norm.eq(0) # loop-end condition
 654         # decrease exponent
 655         with m.If(decrease):
 656             # *sigh* not entirely obvious: count leading zeros (clz)
 657             # with a PriorityEncoder: to find from the MSB
 658             # we reverse the order of the bits.
 659             temp_m = Signal(mwid, reset_less=True)
 660             temp_s = Signal(mwid+1, reset_less=True)
 661             clz = Signal((len(in_z.e), True), reset_less=True)
 662             # make sure that the amount to decrease by does NOT
 663             # go below the minimum non-INF/NaN exponent
 664             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 665                          in_z.exp_sub_n126)
 666             m.d.comb += [
 667                 # cat round and guard bits back into the mantissa
 668                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 669                 pe.i.eq(temp_m[::-1]),          # inverted
 670                 clz.eq(limclz),                 # count zeros from MSB down
 671                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 672                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 673                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 674                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 675                 # overflow in bits 0..1: got shifted too (leave sticky)
 676                 self.out_of.guard.eq(temp_s[1]),     # guard
 677                 self.out_of.round_bit.eq(temp_s[0]), # round
 678             ]
 679         # increase exponent
 680         with m.Elif(increase):
 681             temp_m = Signal(mwid+1, reset_less=True)
 682             m.d.comb += [
 683                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 684                               in_z.m)),
 685                 ediff_n126.eq(in_z.N126 - in_z.e),
 686                 # connect multi-shifter to inp/out mantissa (and ediff)
 687                 msr.inp.eq(temp_m),
 688                 msr.diff.eq(ediff_n126),
 689                 self.out_z.m.eq(msr.m[3:]),
 690                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 691                 # overflow in bits 0..1: got shifted too (leave sticky)
 692                 self.out_of.guard.eq(temp_s[2]),     # guard
 693                 self.out_of.round_bit.eq(temp_s[1]), # round
 694                 self.out_of.sticky.eq(temp_s[0]), # sticky
 695                 self.out_z.e.eq(in_z.e + ediff_n126),
 696             ]
 697
 698         return m
 699
 700
 701 class FPNorm1ModMulti:
 702
 703     def __init__(self, width, single_cycle=True):
 704         self.width = width
 705         self.in_select = Signal(reset_less=True)
 706         self.out_norm = Signal(reset_less=True)
 707         self.in_z = FPNumBase(width, False)
 708         self.in_of = Overflow()
 709         self.temp_z = FPNumBase(width, False)
 710         self.temp_of = Overflow()
 711         self.out_z = FPNumBase(width, False)
 712         self.out_of = Overflow()
 713
 714     def elaborate(self, platform):
 715         m = Module()
 716
 717         m.submodules.norm1_out_z = self.out_z
 718         m.submodules.norm1_out_overflow = self.out_of
 719         m.submodules.norm1_temp_z = self.temp_z
 720         m.submodules.norm1_temp_of = self.temp_of
 721         m.submodules.norm1_in_z = self.in_z
 722         m.submodules.norm1_in_overflow = self.in_of
 723
 724         in_z = FPNumBase(self.width, False)
 725         in_of = Overflow()
 726         m.submodules.norm1_insel_z = in_z
 727         m.submodules.norm1_insel_overflow = in_of
 728
 729         # select which of temp or in z/of to use
 730         with m.If(self.in_select):
 731             m.d.comb += in_z.copy(self.in_z)
 732             m.d.comb += in_of.copy(self.in_of)
 733         with m.Else():
 734             m.d.comb += in_z.copy(self.temp_z)
 735             m.d.comb += in_of.copy(self.temp_of)
 736         # initialise out from in (overridden below)
 737         m.d.comb += self.out_z.copy(in_z)
 738         m.d.comb += self.out_of.copy(in_of)
 739         # normalisation increase/decrease conditions
 740         decrease = Signal(reset_less=True)
 741         increase = Signal(reset_less=True)
 742         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 743         m.d.comb += increase.eq(in_z.exp_lt_n126)
 744         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 745         # decrease exponent
 746         with m.If(decrease):
 747             m.d.comb += [
 748                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 749                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 750                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 751                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 752                 self.out_of.round_bit.eq(0),        # reset round bit
 753                 self.out_of.m0.eq(in_of.guard),
 754             ]
 755         # increase exponent
 756         with m.Elif(increase):
 757             m.d.comb += [
 758                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 759                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 760                 self.out_of.guard.eq(in_z.m[0]),
 761                 self.out_of.m0.eq(in_z.m[1]),
 762                 self.out_of.round_bit.eq(in_of.guard),
 763                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 764             ]
 765
 766         return m
 767
 768
 769 class FPNorm1(FPState, FPID):
 770
 771     def __init__(self, width, id_wid, single_cycle=True):
 772         FPID.__init__(self, id_wid)
 773         FPState.__init__(self, "normalise_1")
 774         if single_cycle:
 775             self.mod = FPNorm1ModSingle(width)
 776         else:
 777             self.mod = FPNorm1ModMulti(width)
 778         self.stb = Signal(reset_less=True)
 779         self.ack = Signal(reset=0, reset_less=True)
 780         self.out_norm = Signal(reset_less=True)
 781         self.in_accept = Signal(reset_less=True)
 782         self.temp_z = FPNumBase(width)
 783         self.temp_of = Overflow()
 784         self.out_z = FPNumBase(width)
 785         self.out_roundz = Signal(reset_less=True)
 786
 787     def setup(self, m, in_z, in_of, norm_stb, in_mid):
 788         """ links module to inputs and outputs
 789         """
 790         m.submodules.normalise_1 = self.mod
 791
 792         m.d.comb += self.mod.in_z.copy(in_z)
 793         m.d.comb += self.mod.in_of.copy(in_of)
 794
 795         m.d.comb += self.mod.in_select.eq(self.in_accept)
 796         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 797         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 798
 799         m.d.comb += self.out_z.copy(self.mod.out_z)
 800         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 801
 802         m.d.comb += self.stb.eq(norm_stb)
 803         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 804
 805         if self.in_mid:
 806             m.d.comb += self.in_mid.eq(in_mid)
 807
 808     def action(self, m):
 809         self.idsync(m)
 810         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 811         m.d.sync += self.temp_of.copy(self.mod.out_of)
 812         m.d.sync += self.temp_z.copy(self.out_z)
 813         with m.If(self.out_norm):
 814             with m.If(self.in_accept):
 815                 m.d.sync += [
 816                     self.ack.eq(1),
 817                 ]
 818             with m.Else():
 819                 m.d.sync += self.ack.eq(0)
 820         with m.Else():
 821             # normalisation not required (or done).
 822             m.next = "round"
 823             m.d.sync += self.ack.eq(1)
 824             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 825
 826
 827 class FPRoundMod:
 828
 829     def __init__(self, width):
 830         self.in_roundz = Signal(reset_less=True)
 831         self.in_z = FPNumBase(width, False)
 832         self.out_z = FPNumBase(width, False)
 833
 834     def elaborate(self, platform):
 835         m = Module()
 836         m.d.comb += self.out_z.copy(self.in_z)
 837         with m.If(self.in_roundz):
 838             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 839             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 840                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 841         return m
 842
 843
 844 class FPRound(FPState, FPID):
 845
 846     def __init__(self, width, id_wid):
 847         FPState.__init__(self, "round")
 848         FPID.__init__(self, id_wid)
 849         self.mod = FPRoundMod(width)
 850         self.out_z = FPNumBase(width)
 851
 852     def setup(self, m, in_z, roundz, in_mid):
 853         """ links module to inputs and outputs
 854         """
 855         m.submodules.roundz = self.mod
 856
 857         m.d.comb += self.mod.in_z.copy(in_z)
 858         m.d.comb += self.mod.in_roundz.eq(roundz)
 859         if self.in_mid:
 860             m.d.comb += self.in_mid.eq(in_mid)
 861
 862     def action(self, m):
 863         self.idsync(m)
 864         m.d.sync += self.out_z.copy(self.mod.out_z)
 865         m.next = "corrections"
 866
 867
 868 class FPCorrectionsMod:
 869
 870     def __init__(self, width):
 871         self.in_z = FPNumOut(width, False)
 872         self.out_z = FPNumOut(width, False)
 873
 874     def elaborate(self, platform):
 875         m = Module()
 876         m.submodules.corr_in_z = self.in_z
 877         m.submodules.corr_out_z = self.out_z
 878         m.d.comb += self.out_z.copy(self.in_z)
 879         with m.If(self.in_z.is_denormalised):
 880             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 881         return m
 882
 883
 884 class FPCorrections(FPState):
 885
 886     def __init__(self, width):
 887         FPState.__init__(self, "corrections")
 888         self.mod = FPCorrectionsMod(width)
 889         self.out_z = FPNumBase(width)
 890
 891     def setup(self, m, in_z):
 892         """ links module to inputs and outputs
 893         """
 894         m.submodules.corrections = self.mod
 895         m.d.comb += self.mod.in_z.copy(in_z)
 896
 897     def action(self, m):
 898         m.d.sync += self.out_z.copy(self.mod.out_z)
 899         m.next = "pack"
 900
 901
 902 class FPPackMod:
 903
 904     def __init__(self, width):
 905         self.in_z = FPNumOut(width, False)
 906         self.out_z = FPNumOut(width, False)
 907
 908     def elaborate(self, platform):
 909         m = Module()
 910         m.submodules.pack_in_z = self.in_z
 911         with m.If(self.in_z.is_overflowed):
 912             m.d.comb += self.out_z.inf(self.in_z.s)
 913         with m.Else():
 914             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 915         return m
 916
 917
 918 class FPPack(FPState):
 919
 920     def __init__(self, width):
 921         FPState.__init__(self, "pack")
 922         self.mod = FPPackMod(width)
 923         self.out_z = FPNumOut(width, False)
 924
 925     def setup(self, m, in_z):
 926         """ links module to inputs and outputs
 927         """
 928         m.submodules.pack = self.mod
 929         m.d.comb += self.mod.in_z.copy(in_z)
 930
 931     def action(self, m):
 932         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 933         m.next = "pack_put_z"
 934
 935
 936 class FPPutZ(FPState):
 937
 938     def __init__(self, state, in_z, out_z):
 939         FPState.__init__(self, state)
 940         self.in_z = in_z
 941         self.out_z = out_z
 942
 943     def action(self, m):
 944         m.d.sync += [
 945           self.out_z.v.eq(self.in_z.v)
 946         ]
 947         with m.If(self.out_z.stb & self.out_z.ack):
 948             m.d.sync += self.out_z.stb.eq(0)
 949             m.next = "get_a"
 950         with m.Else():
 951             m.d.sync += self.out_z.stb.eq(1)
 952
 953
 954 class FPADD(FPID):
 955
 956     def __init__(self, width, id_wid=None, single_cycle=False):
 957         """ IEEE754 FP Add
 958
 959             * width: bit-width of IEEE754.  supported: 16, 32, 64
 960             * id_wid: an identifier that is sync-connected to the input
 961             * single_cycle: True indicates each stage to complete in 1 clock
 962         """
 963         FPID.__init__(self, id_wid)
 964         self.width = width
 965         self.single_cycle = single_cycle
 966
 967         self.in_a  = FPOp(width)
 968         self.in_b  = FPOp(width)
 969         self.out_z = FPOp(width)
 970
 971         self.states = []
 972
 973     def add_state(self, state):
 974         self.states.append(state)
 975         return state
 976
 977     def get_fragment(self, platform=None):
 978         """ creates the HDL code-fragment for FPAdd
 979         """
 980         m = Module()
 981         m.submodules.in_a = self.in_a
 982         m.submodules.in_b = self.in_b
 983         m.submodules.out_z = self.out_z
 984
 985         geta = self.add_state(FPGetOp("get_a", "get_b",
 986                                       self.in_a, self.width))
 987         geta.setup(m, self.in_a)
 988         a = geta.out_op
 989
 990         getb = self.add_state(FPGetOp("get_b", "special_cases",
 991                                       self.in_b, self.width))
 992         getb.setup(m, self.in_b)
 993         b = getb.out_op
 994
 995         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
 996         sc.setup(m, a, b, self.in_mid)
 997
 998         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
 999         dn.setup(m, a, b, sc.in_mid)
1000
1001         if self.single_cycle:
1002             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1003             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1004         else:
1005             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1006             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1007
1008         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1009         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1010
1011         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1012         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1013
1014         n1 = self.add_state(FPNorm1(self.width, self.id_wid))
1015         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1016
1017         rn = self.add_state(FPRound(self.width, self.id_wid))
1018         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1019
1020         cor = self.add_state(FPCorrections(self.width))
1021         cor.setup(m, rn.out_z)
1022
1023         pa = self.add_state(FPPack(self.width))
1024         pa.setup(m, cor.out_z)
1025
1026         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
1027
1028         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
1029
1030         with m.FSM() as fsm:
1031
1032             for state in self.states:
1033                 with m.State(state.state_from):
1034                     state.action(m)
1035
1036         return m
1037
1038
1039 if __name__ == "__main__":
1040     alu = FPADD(width=32, single_cycle=True)
1041     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
1042
1043
1044     # works... but don't use, just do "python fname.py convert -t v"
1045     #print (verilog.convert(alu, ports=[
1046     #                        ports=alu.in_a.ports() + \
1047     #                              alu.in_b.ports() + \
1048     #                              alu.out_z.ports())