src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27 def applyop(op1, op2, op):
  28     if isinstance(op1, PartitionedSignal):
  29         op1 = op1.sig
  30     if isinstance(op2, PartitionedSignal):
  31         op2 = op2.sig
  32     return op(op1, op2)
  33
  34
  35 class PartitionedSignal:
  36     def __init__(self, mask, *args, **kwargs):
  37         self.sig = Signal(*args, **kwargs)
  38         width = self.sig.shape()[0] # get signal width
  39         self.partpoints = make_partition(mask, width) # create partition points
  40         self.modnames = {}
  41         for name in ['add', 'eq', 'gt', 'ge']:
  42             self.modnames[name] = 0
  43
  44     def set_module(self, m):
  45         self.m = m
  46
  47     def get_modname(self, category):
  48         self.modnames[category] += 1
  49         return "%s%d" % (category, self.modnames[category])
  50
  51     def eq(self, val):
  52         return self.sig.eq(val)
  53
  54     # unary  ops that require partitioning
  55
  56     def __invert__(self):
  57         return Operator("~", [self])
  58     def __neg__(self):
  59         return Operator("-", [self])
  60
  61     # binary ops that don't require partitioning
  62
  63     def __and__(self, other):
  64         return applyop(self, other, and_)
  65
  66     def __rand__(self, other):
  67         return applyop(other, self, and_)
  68
  69     def __or__(self, other):
  70         return applyop(self, other, or_)
  71
  72     def __ror__(self, other):
  73         return applyop(other, self, or_)
  74
  75     def __xor__(self, other):
  76         return applyop(self, other, xor)
  77
  78     def __rxor__(self, other):
  79         return applyop(other, self, xor)
  80
  81     # binary ops that need partitioning
  82
  83     def __add__(self, other):
  84         shape = self.sig.shape()
  85         pa = PartitionedAdder(shape[0], self.partpoints)
  86         setattr(self.m.submodules, self.get_modname('add'), pa)
  87         comb = self.m.d.comb
  88         comb += pa.a.eq(self.sig)
  89         if isinstance(other, PartitionedSignal):
  90             comb += pa.b.eq(other.sig)
  91         else:
  92             comb += pa.b.eq(other)
  93         return pa.output
  94
  95     def __radd__(self, other):
  96         return Operator("+", [other, self])
  97     def __sub__(self, other):
  98         return Operator("-", [self, other])
  99     def __rsub__(self, other):
 100         return Operator("-", [other, self])
 101
 102     def __mul__(self, other):
 103         return Operator("*", [self, other])
 104     def __rmul__(self, other):
 105         return Operator("*", [other, self])
 106
 107     def __check_divisor(self):
 108         width, signed = self.shape()
 109         if signed:
 110             # Python's division semantics and Verilog's division semantics
 111             # differ for negative divisors (Python uses div/mod, Verilog
 112             # uses quo/rem); for now, avoid the issue
 113             # completely by prohibiting such division operations.
 114             raise NotImplementedError(
 115                     "Division by a signed value is not supported")
 116     def __mod__(self, other):
 117         other = Value.cast(other)
 118         other.__check_divisor()
 119         return Operator("%", [self, other])
 120     def __rmod__(self, other):
 121         self.__check_divisor()
 122         return Operator("%", [other, self])
 123     def __floordiv__(self, other):
 124         other = Value.cast(other)
 125         other.__check_divisor()
 126         return Operator("//", [self, other])
 127     def __rfloordiv__(self, other):
 128         self.__check_divisor()
 129         return Operator("//", [other, self])
 130
 131     def __lshift__(self, other):
 132         return Operator("<<", [self, other])
 133     def __rlshift__(self, other):
 134         return Operator("<<", [other, self])
 135     def __rshift__(self, other):
 136         return Operator(">>", [self, other])
 137
 138     # binary comparison ops that need partitioning
 139
 140     def _compare(self, width, op1, op2, opname, optype):
 141         #print (opname, op1, op2)
 142         pa = PartitionedEqGtGe(width, self.partpoints)
 143         setattr(self.m.submodules, self.get_modname(opname), pa)
 144         comb = self.m.d.comb
 145         comb += pa.opcode.eq(optype) # set opcode
 146         if isinstance(op1, PartitionedSignal):
 147             comb += pa.a.eq(op1.sig)
 148         else:
 149             comb += pa.a.eq(op1)
 150         if isinstance(op2, PartitionedSignal):
 151             comb += pa.b.eq(op2.sig)
 152         else:
 153             comb += pa.b.eq(op2)
 154         return pa.output
 155
 156     def __eq__(self, other):
 157         width = self.sig.shape()[0]
 158         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 159
 160     def __ne__(self, other):
 161         width = self.sig.shape()[0]
 162         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 163         ne = Signal(eq.width)
 164         self.m.d.comb += ne.eq(~eq)
 165         return ne
 166
 167     def __gt__(self, other):
 168         width = self.sig.shape()[0]
 169         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 170
 171     def __lt__(self, other):
 172         width = self.sig.shape()[0]
 173         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 174
 175     def __ge__(self, other):
 176         width = self.sig.shape()[0]
 177         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 178
 179     def __le__(self, other):
 180         width = self.sig.shape()[0]
 181         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 182
 183     # useful operators
 184
 185     def bool(self):
 186         """Conversion to boolean.
 187
 188         Returns
 189         -------
 190         Value, out
 191             ``1`` if any bits are set, ``0`` otherwise.
 192         """
 193         return Operator("b", [self])
 194
 195     def any(self):
 196         """Check if any bits are ``1``.
 197
 198         Returns
 199         -------
 200         Value, out
 201             ``1`` if any bits are set, ``0`` otherwise.
 202         """
 203         return Operator("r|", [self])
 204
 205     def all(self):
 206         """Check if all bits are ``1``.
 207
 208         Returns
 209         -------
 210         Value, out
 211             ``1`` if all bits are set, ``0`` otherwise.
 212         """
 213         return Operator("r&", [self])
 214
 215     def xor(self):
 216         """Compute pairwise exclusive-or of every bit.
 217
 218         Returns
 219         -------
 220         Value, out
 221             ``1`` if an odd number of bits are set, ``0`` if an
 222                   even number of bits are set.
 223         """
 224         return Operator("r^", [self])
 225
 226     def implies(premise, conclusion):
 227         """Implication.
 228
 229         Returns
 230         -------
 231         Value, out
 232             ``0`` if ``premise`` is true and ``conclusion`` is not,
 233             ``1`` otherwise.
 234         """
 235         return ~premise | conclusion
 236
 237