split out add1 to separate module

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 4b359c8d17befcee6f151d507b33f25303e8dd03..bffd4b22c0c53582fca80368b58b25b6cd214019 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -32,6 +32,7 @@ from fpadd.specialcases import (FPAddSpecialCasesMod, FPAddSpecialCases,
 from fpadd.align import (FPAddAlignMulti, FPAddAlignMultiMod, FPNumIn2Ops,
                          FPAddAlignSingleMod, FPAddAlignSingle)
 from fpadd.add0 import (FPAddStage0Data, FPAddStage0Mod, FPAddStage0)
+from fpadd.add1 import (FPAddStage1Mod, FPAddStage1)
 
 
 class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
@@ -71,93 +72,6 @@ class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
         m.next = "normalise_1"
 
 
-
-
-class FPAddStage1Mod(FPState):
-    """ Second stage of add: preparation for normalisation.
-        detects when tot sum is too big (tot[27] is kinda a carry bit)
-    """
-
-    def __init__(self, width, id_wid):
-        self.width = width
-        self.id_wid = id_wid
-        self.i = self.ispec()
-        self.o = self.ospec()
-
-    def ispec(self):
-        return FPAddStage0Data(self.width, self.id_wid)
-
-    def ospec(self):
-        return FPAddStage1Data(self.width, self.id_wid)
-
-    def process(self, i):
-        return self.o
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.add1 = self
-        m.submodules.add1_out_overflow = self.o.of
-
-        m.d.comb += self.i.eq(i)
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.comb += self.o.z.eq(self.i.z)
-        # tot[-1] (MSB) gets set when the sum overflows. shift result down
-        with m.If(~self.i.out_do_z):
-            with m.If(self.i.tot[-1]):
-                m.d.comb += [
-                    self.o.z.m.eq(self.i.tot[4:]),
-                    self.o.of.m0.eq(self.i.tot[4]),
-                    self.o.of.guard.eq(self.i.tot[3]),
-                    self.o.of.round_bit.eq(self.i.tot[2]),
-                    self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
-                    self.o.z.e.eq(self.i.z.e + 1)
-            ]
-            # tot[-1] (MSB) zero case
-            with m.Else():
-                m.d.comb += [
-                    self.o.z.m.eq(self.i.tot[3:]),
-                    self.o.of.m0.eq(self.i.tot[3]),
-                    self.o.of.guard.eq(self.i.tot[2]),
-                    self.o.of.round_bit.eq(self.i.tot[1]),
-                    self.o.of.sticky.eq(self.i.tot[0])
-            ]
-
-        m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.oz.eq(self.i.oz)
-        m.d.comb += self.o.mid.eq(self.i.mid)
-
-        return m
-
-
-class FPAddStage1(FPState):
-
-    def __init__(self, width, id_wid):
-        FPState.__init__(self, "add_1")
-        self.mod = FPAddStage1Mod(width)
-        self.out_z = FPNumBase(width, False)
-        self.out_of = Overflow()
-        self.norm_stb = Signal()
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        self.mod.setup(m, i)
-
-        m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
-
-        m.d.sync += self.out_of.eq(self.mod.out_of)
-        m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.norm_stb.eq(1)
-
-    def action(self, m):
-        m.next = "normalise_1"
-
-
-
-
 class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOp(width)