format code

[ieee754fpu.git] / src / ieee754 / fcvt / test / test_fcvt_int_pipe_16_32.py

diff --git a/src/ieee754/fcvt/test/test_fcvt_int_pipe_16_32.py b/src/ieee754/fcvt/test/test_fcvt_int_pipe_16_32.py
index 5f9a21a696f1ad3ea60ce7a75e21612ebc88a5d6..674daa35452cd2e99e8706ea35a019b660e0cb4e 100644 (file)
--- a/src/ieee754/fcvt/test/test_fcvt_int_pipe_16_32.py
+++ b/src/ieee754/fcvt/test/test_fcvt_int_pipe_16_32.py
@@ -5,7 +5,7 @@
     of sense, but hey.
 """
 
-from ieee754.fcvt.pipeline import (FPCVTIntMuxInOut,)
+from ieee754.fcvt.pipeline import FPCVTIntMuxInOut
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_half
 from ieee754.fcvt.test.up_fcvt_data_16_32 import regressions
@@ -13,24 +13,29 @@ from ieee754.fcvt.test.up_fcvt_data_16_32 import regressions
 import sfpy
 from sfpy import Float64, Float32, Float16
 
+
 def to_uint16(x):
     return x
 
+
 def to_uint32(x):
     return x
 
+
 def fcvt_64(x):
     return sfpy.float.ui32_to_f64(x)
 
+
 def fcvt_32(x):
     return sfpy.float.ui32_to_f32(x)
 
+
 def test_int_pipe_fp16_32():
     dut = FPCVTIntMuxInOut(16, 32, 4)
     run_pipe_fp(dut, 16, "int_16_32", unit_test_half, to_uint16,
                 regressions, fcvt_32, 100, True)
 
+
 if __name__ == '__main__':
     for i in range(200):
         test_int_pipe_fp16_32()
-