multiply mask width for concurrent pipeline

[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 9bfcb49eb1d4e56957475c2dc654b376b834d3d3..8b9e108639bdcfcde975ec2fb49777f7129c2c38 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -177,7 +177,7 @@ class FPDIVMuxInOut(ReservationStations):
         cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
 
         self.pspec.pipekls = MaskCancellableRedir
-        self.pspec.maskwid = maskwid
+        self.pspec.maskwid = maskwid * num_rows # RS gets just maskwid
         self.pspec.fpformat = fmt
         self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg