fix tests/mark as expected failure

[ieee754fpu.git] / src / ieee754 / part / test / test_partsig_scope.py

diff --git a/src/ieee754/part/test/test_partsig_scope.py b/src/ieee754/part/test/test_partsig_scope.py
index 1da4e3720f40bf1096526702103e2ca9590bed19..2a295013aa21a95fa1aa4be8f08460ba4a6fc4e5 100644 (file)
--- a/src/ieee754/part/test/test_partsig_scope.py
+++ b/src/ieee754/part/test/test_partsig_scope.py
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: LGPL-2.1-or-later
 # See Notices.txt for copyright information
 
-from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl
+from nmigen import Signal, Module, Elaboratable, Mux, Cat, Shape, Repl, Value
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.cli import rtlil
 
@@ -47,6 +47,7 @@ class TestCatMod(Elaboratable):
         return m
 
 
+@unittest.skipUnless(hasattr(Value, "__Cat__"), "missing nmigen simd support")
 class TestCat(unittest.TestCase):
     def test(self):
         width = 16