README.md

   1 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png"></p>
   2
   3 ```
   4                           Copyright 2012-2020 / Enjoy-Digital
   5 ```
   6 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
   7 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
   8
   9 > **Note:** In release 2020.04, LiteX switched to Python modules instead of Git submodules. Existing users will have to reinstall LiteX following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation#litex-installation-guide).
  10
  11 # Welcome to LiteX!
  12
  13 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
  14 The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
  15
  16 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
  17 SoC builder to create/develop/debug FPGA SoCs in Python.
  18
  19 **A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)**
  20
  21 # Typical LiteX design flow:
  22 ```
  23                                       +---------------+
  24                                       |FPGA toolchains|
  25                                       +----^-----+----+
  26                                            |     |
  27                                         +--+-----v--+
  28                        +-------+        |           |
  29                        | Migen +-------->           |
  30                        +-------+        |           |        Your design
  31                                         |   LiteX   +---> ready to be used!
  32                                         |           |
  33               +----------------------+  |           |
  34               |LiteX Cores Ecosystem +-->           |
  35               +----------------------+  +-^-------^-+
  36                (Eth, SATA, DRAM, USB,     |       |
  37                 PCIe, Video, etc...)      +       +
  38                                          board   target
  39                                          file    file
  40 ```
  41 LiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32 and is compatible with the LiteX's Cores Ecosystem:
  42
  43 | Name                                                         | Build Status                                                            | Description                   |
  44 | ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
  45 | [LiteDRAM](http://github.com/enjoy-digital/litedram)         | [![](https://travis-ci.com/enjoy-digital/litedram.svg?branch=master)](https://travis-ci.com/enjoy-digital/litedram)     | DRAM        |
  46 | [LiteEth](http://github.com/enjoy-digital/liteeth)           | [![](https://travis-ci.com/enjoy-digital/liteeth.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteeth)       | Ethernet                      |
  47 | [LitePCIe](http://github.com/enjoy-digital/litepcie)         | [![](https://travis-ci.com/enjoy-digital/litepcie.svg?branch=master)](https://travis-ci.com/enjoy-digital/litepcie)     | PCIe                          |
  48 | [LiteSATA](http://github.com/enjoy-digital/litesata)         | [![](https://travis-ci.com/enjoy-digital/litesata.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesata)     | SATA                          |
  49 | [LiteSDCard](http://github.com/enjoy-digital/litesdcard)     | [![](https://travis-ci.com/enjoy-digital/litesdcard.svg?branch=master)](https://travis-ci.com/enjoy-digital/litesdcard)   | SD card                       |
  50 | [LiteICLink](http://github.com/enjoy-digital/liteiclink)     | [![](https://travis-ci.com/enjoy-digital/liteiclink.svg?branch=master)](https://travis-ci.com/enjoy-digital/liteiclink)   | Inter-Chip communication      |
  51 | [LiteJESD204B](http://github.com/enjoy-digital/litejesd204b) | [![](https://travis-ci.com/enjoy-digital/litejesd204b.svg?branch=master)](https://travis-ci.com/enjoy-digital/litejesd204b) | JESD204B                      |
  52 | [LiteVideo](http://github.com/enjoy-digital/litevideo)       | [![](https://travis-ci.com/enjoy-digital/litevideo.svg?branch=master)](https://travis-ci.com/enjoy-digital/litevideo)    | VGA, DVI, HDMI                     |
  53 | [LiteScope](http://github.com/enjoy-digital/litescope)       | [![](https://travis-ci.com/enjoy-digital/litescope.svg?branch=master)](https://travis-ci.com/enjoy-digital/litescope)    | Logic analyzer  |
  54
  55 Combining LiteX with the ecosystem of cores allows the creation of complex SoCs such as the one below
  56 created for the NeTV2 board to do HDMI capture/playback over PCIe:
  57
  58 <p align="center"><img width="800" src="https://raw.githubusercontent.com/enjoy-digital/netv2/master/doc/architecture.png"></p>
  59
  60 # Papers, Presentations, Tutorials, Links
  61 **FPGA lessons/tutorials:**
  62 - https://github.com/enjoy-digital/fpga_101
  63
  64 **Migen tutorial:**
  65 - https://m-labs.hk/migen/manual
  66
  67 **OSDA 2019 paper/slides:**
  68 - https://osda.gitlab.io/19/1.1.pdf
  69 - https://osda.gitlab.io/19/1.1-slides.pdf
  70
  71 **Linux on LiteX-Vexriscv:**
  72 - https://github.com/litex-hub/linux-on-litex-vexriscv
  73
  74 **RISC-V Getting Started Guide:**
  75 - https://risc-v-getting-started-guide.readthedocs.io/en/latest/
  76
  77 **LiteX vs. Vivado First Impressions:**
  78 - https://www.bunniestudios.com/blog/?p=5018
  79
  80 **35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:**
  81 - https://www.youtube.com/watch?v=AlmVxR0417c
  82
  83 **Tim has to many projects - LatchUp Edition:**
  84 https://www.youtube.com/watch?v=v7WrTmexod0
  85
  86
  87 # Sub-packages
  88 **litex.gen**
  89 Provides specific or experimental modules to generate HDL that are not integrated in Migen.
  90
  91 **litex.build:**
  92 Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.
  93
  94 **litex.soc:**
  95 Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.
  96
  97 **litex.boards:**
  98 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
  99
 100 # Quick start guide
 101 1. Install Python 3.6+ and FPGA vendor's development tools and/or [Verilator](http://www.veripool.org/).
 102 2. Install Migen/LiteX and the LiteX's cores:
 103
 104 ```sh
 105 $ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
 106 $ chmod +x litex_setup.py
 107 $ ./litex_setup.py init install --user (--user to install to user directory)
 108 ```
 109   Later, if you need to update all repositories:
 110 ```sh
 111 $ ./litex_setup.py update
 112 ```
 113
 114 > **Note:** On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
 115
 116 > **Note:** On Windows, it's possible you'll have to set `SHELL` environment variable to `SHELL=cmd.exe`.
 117
 118 3. Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):
 119 ```sh
 120 $ ./litex_setup.py gcc
 121 ```
 122
 123 4. Build the target of your board...:
 124
 125 Go to litex-boards/litex_boards/targets and execute the target you want to build.
 126
 127 5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX directly on your computer without any FPGA board:
 128
 129 On Linux (Ubuntu):
 130 ```sh
 131 $ sudo apt install libevent-dev libjson-c-dev verilator
 132 $ lxsim --cpu-type=vexriscv
 133 ```
 134
 135 On MacOS:
 136 ```sh
 137 $ brew install json-c verilator libevent
 138 $ brew cask install tuntap
 139 $ lxsim --cpu-type=vexriscv
 140 ```
 141
 142 6. Run a terminal program on the board's serial port at 115200 8-N-1.
 143
 144   You should get the BIOS prompt like the one below.
 145
 146 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
 147
 148 # Community
 149
 150 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex-hub.png" width="400"></p>
 151
 152 LiteX has been initially developed by EnjoyDigital to create custom SoCs/Systems for our clients
 153 (and we are still using it for that purpose :)); but over the years a friendly community has grown
 154 around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved
 155 the project, EnjoyDigital still leads the development but it is now a community project and collaborative
 156 projects created around/with LiteX can be found at https://github.com/litex-hub.
 157
 158 # Contact
 159 E-mail: florent@enjoy-digital.fr