soc/integration/csr_bridge: use registered version only when SDRAM is present.
[litex.git] / setup.py
1 #!/usr/bin/env python3
2
3 from setuptools import setup
4 from setuptools import find_packages
5
6
7 setup(
8 name="litex",
9 description="Python SoC/Core builder for building FPGA based systems.",
10 author="Florent Kermarrec",
11 author_email="florent@enjoy-digital.fr",
12 url="http://enjoy-digital.fr",
13 download_url="https://github.com/enjoy-digital/litex",
14 test_suite="test",
15 license="BSD",
16 python_requires="~=3.6",
17 install_requires=[
18 "migen",
19 "pyserial",
20 "requests",
21 "pythondata-software-compiler_rt",
22 ],
23 packages=find_packages(exclude=("test*", "sim*", "doc*")),
24 include_package_data=True,
25 platforms=["Any"],
26 keywords="HDL ASIC FPGA hardware design",
27 classifiers=[
28 "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
29 "Environment :: Console",
30 "Development Status :: Alpha",
31 "Intended Audience :: Developers",
32 "License :: OSI Approved :: BSD License",
33 "Operating System :: OS Independent",
34 "Programming Language :: Python",
35 ],
36 entry_points={
37 "console_scripts": [
38 # full names
39 "litex_term=litex.tools.litex_term:main",
40 "litex_server=litex.tools.litex_server:main",
41 "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
42 "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
43 "litex_sim=litex.tools.litex_sim:main",
44 "litex_read_verilog=litex.tools.litex_read_verilog:main",
45 "litex_simple=litex.boards.targets.simple:main",
46 "litex_json2dts=litex.tools.litex_json2dts:main",
47 # short names
48 "lxterm=litex.tools.litex_term:main",
49 "lxserver=litex.tools.litex_server:main",
50 "lxsim=litex.tools.litex_sim:main",
51 ],
52 },
53 )