2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
43 /* Emit IB that preloads the descriptors that the shader uses */
46 emit_load_state(struct tu_cs
*cs
, unsigned opcode
, enum a6xx_state_type st
,
47 enum a6xx_state_block sb
, unsigned base
, unsigned offset
,
50 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
51 * clear if emitting more packets will even help anything. Presumably the
52 * descriptor cache is relatively small, and these packets stop doing
53 * anything when there are too many descriptors.
55 tu_cs_emit_pkt7(cs
, opcode
, 3);
57 CP_LOAD_STATE6_0_STATE_TYPE(st
) |
58 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS
) |
59 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
60 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count
, 1024-1)));
61 tu_cs_emit_qw(cs
, offset
| (base
<< 28));
65 tu6_load_state_size(struct tu_pipeline_layout
*layout
, bool compute
)
67 const unsigned load_state_size
= 4;
69 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
70 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
71 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
72 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
74 /* Note: some users, like amber for example, pass in
75 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
76 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
78 VkShaderStageFlags stages
= compute
?
79 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
80 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
81 unsigned stage_count
= util_bitcount(stages
);
82 switch (binding
->type
) {
83 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
84 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
85 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
86 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
87 /* IBO-backed resources only need one packet for all graphics stages */
88 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
)
90 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
)
93 case VK_DESCRIPTOR_TYPE_SAMPLER
:
94 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
95 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
96 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
97 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
98 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
99 /* Textures and UBO's needs a packet for each stage */
102 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
103 /* Because of how we pack combined images and samplers, we
104 * currently can't use one packet for the whole array.
106 count
= stage_count
* binding
->array_size
* 2;
109 unreachable("bad descriptor type");
111 size
+= count
* load_state_size
;
118 tu6_emit_load_state(struct tu_pipeline
*pipeline
, bool compute
)
120 unsigned size
= tu6_load_state_size(pipeline
->layout
, compute
);
125 tu_cs_begin_sub_stream(&pipeline
->cs
, size
, &cs
);
127 struct tu_pipeline_layout
*layout
= pipeline
->layout
;
128 for (unsigned i
= 0; i
< layout
->num_sets
; i
++) {
129 /* From 13.2.7. Descriptor Set Binding:
131 * A compatible descriptor set must be bound for all set numbers that
132 * any shaders in a pipeline access, at the time that a draw or
133 * dispatch command is recorded to execute using that pipeline.
134 * However, if none of the shaders in a pipeline statically use any
135 * bindings with a particular set number, then no descriptor set need
136 * be bound for that set number, even if the pipeline layout includes
137 * a non-trivial descriptor set layout for that set number.
139 * This means that descriptor sets unused by the pipeline may have a
140 * garbage or 0 BINDLESS_BASE register, which will cause context faults
141 * when prefetching descriptors from these sets. Skip prefetching for
142 * descriptors from them to avoid this. This is also an optimization,
143 * since these prefetches would be useless.
145 if (!(pipeline
->active_desc_sets
& (1u << i
)))
148 struct tu_descriptor_set_layout
*set_layout
= layout
->set
[i
].layout
;
149 for (unsigned j
= 0; j
< set_layout
->binding_count
; j
++) {
150 struct tu_descriptor_set_binding_layout
*binding
= &set_layout
->binding
[j
];
152 unsigned offset
= binding
->offset
/ 4;
153 /* Note: some users, like amber for example, pass in
154 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
155 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
157 VkShaderStageFlags stages
= compute
?
158 binding
->shader_stages
& VK_SHADER_STAGE_COMPUTE_BIT
:
159 binding
->shader_stages
& VK_SHADER_STAGE_ALL_GRAPHICS
;
160 unsigned count
= binding
->array_size
;
161 if (count
== 0 || stages
== 0)
163 switch (binding
->type
) {
164 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
166 offset
= (layout
->set
[i
].dynamic_offset_start
+
167 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
169 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
170 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
:
171 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
172 /* IBO-backed resources only need one packet for all graphics stages */
173 if (stages
& ~VK_SHADER_STAGE_COMPUTE_BIT
) {
174 emit_load_state(&cs
, CP_LOAD_STATE6
, ST6_SHADER
, SB6_IBO
,
175 base
, offset
, count
);
177 if (stages
& VK_SHADER_STAGE_COMPUTE_BIT
) {
178 emit_load_state(&cs
, CP_LOAD_STATE6_FRAG
, ST6_IBO
, SB6_CS_SHADER
,
179 base
, offset
, count
);
182 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
183 /* nothing - input attachment doesn't use bindless */
185 case VK_DESCRIPTOR_TYPE_SAMPLER
:
186 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
187 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
: {
188 tu_foreach_stage(stage
, stages
) {
189 emit_load_state(&cs
, tu6_stage2opcode(stage
),
190 binding
->type
== VK_DESCRIPTOR_TYPE_SAMPLER
?
191 ST6_SHADER
: ST6_CONSTANTS
,
192 tu6_stage2texsb(stage
), base
, offset
, count
);
196 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
198 offset
= (layout
->set
[i
].dynamic_offset_start
+
199 binding
->dynamic_offset_offset
) * A6XX_TEX_CONST_DWORDS
;
201 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
: {
202 tu_foreach_stage(stage
, stages
) {
203 emit_load_state(&cs
, tu6_stage2opcode(stage
), ST6_UBO
,
204 tu6_stage2shadersb(stage
), base
, offset
, count
);
208 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
: {
209 tu_foreach_stage(stage
, stages
) {
210 /* TODO: We could emit less CP_LOAD_STATE6 if we used
211 * struct-of-arrays instead of array-of-structs.
213 for (unsigned i
= 0; i
< count
; i
++) {
214 unsigned tex_offset
= offset
+ 2 * i
* A6XX_TEX_CONST_DWORDS
;
215 unsigned sam_offset
= offset
+ (2 * i
+ 1) * A6XX_TEX_CONST_DWORDS
;
216 emit_load_state(&cs
, tu6_stage2opcode(stage
),
217 ST6_CONSTANTS
, tu6_stage2texsb(stage
),
218 base
, tex_offset
, 1);
219 emit_load_state(&cs
, tu6_stage2opcode(stage
),
220 ST6_SHADER
, tu6_stage2texsb(stage
),
221 base
, sam_offset
, 1);
227 unreachable("bad descriptor type");
232 pipeline
->load_state
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
235 struct tu_pipeline_builder
237 struct tu_device
*device
;
238 struct tu_pipeline_cache
*cache
;
239 struct tu_pipeline_layout
*layout
;
240 const VkAllocationCallbacks
*alloc
;
241 const VkGraphicsPipelineCreateInfo
*create_info
;
243 struct tu_shader
*shaders
[MESA_SHADER_STAGES
];
244 struct ir3_shader_variant
*variants
[MESA_SHADER_STAGES
];
245 struct ir3_shader_variant
*binning_variant
;
246 uint64_t shader_iova
[MESA_SHADER_STAGES
];
247 uint64_t binning_vs_iova
;
249 bool rasterizer_discard
;
250 /* these states are affectd by rasterizer_discard */
251 VkSampleCountFlagBits samples
;
252 bool use_color_attachments
;
253 bool use_dual_src_blend
;
254 uint32_t color_attachment_count
;
255 VkFormat color_attachment_formats
[MAX_RTS
];
256 VkFormat depth_attachment_format
;
257 uint32_t render_components
;
261 tu_logic_op_reads_dst(VkLogicOp op
)
264 case VK_LOGIC_OP_CLEAR
:
265 case VK_LOGIC_OP_COPY
:
266 case VK_LOGIC_OP_COPY_INVERTED
:
267 case VK_LOGIC_OP_SET
:
275 tu_blend_factor_no_dst_alpha(VkBlendFactor factor
)
277 /* treat dst alpha as 1.0 and avoid reading it */
279 case VK_BLEND_FACTOR_DST_ALPHA
:
280 return VK_BLEND_FACTOR_ONE
;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
282 return VK_BLEND_FACTOR_ZERO
;
288 static bool tu_blend_factor_is_dual_src(VkBlendFactor factor
)
291 case VK_BLEND_FACTOR_SRC1_COLOR
:
292 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
293 case VK_BLEND_FACTOR_SRC1_ALPHA
:
294 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
302 tu_blend_state_is_dual_src(const VkPipelineColorBlendStateCreateInfo
*info
)
307 for (unsigned i
= 0; i
< info
->attachmentCount
; i
++) {
308 const VkPipelineColorBlendAttachmentState
*blend
= &info
->pAttachments
[i
];
309 if (tu_blend_factor_is_dual_src(blend
->srcColorBlendFactor
) ||
310 tu_blend_factor_is_dual_src(blend
->dstColorBlendFactor
) ||
311 tu_blend_factor_is_dual_src(blend
->srcAlphaBlendFactor
) ||
312 tu_blend_factor_is_dual_src(blend
->dstAlphaBlendFactor
))
320 tu6_emit_xs_config(struct tu_cs
*cs
,
321 gl_shader_stage stage
, /* xs->type, but xs may be NULL */
322 const struct ir3_shader_variant
*xs
,
323 uint64_t binary_iova
)
325 static const struct xs_config
{
326 uint16_t reg_sp_xs_ctrl
;
327 uint16_t reg_sp_xs_config
;
328 uint16_t reg_hlsq_xs_ctrl
;
329 uint16_t reg_sp_vs_obj_start
;
331 [MESA_SHADER_VERTEX
] = {
332 REG_A6XX_SP_VS_CTRL_REG0
,
333 REG_A6XX_SP_VS_CONFIG
,
334 REG_A6XX_HLSQ_VS_CNTL
,
335 REG_A6XX_SP_VS_OBJ_START_LO
,
337 [MESA_SHADER_TESS_CTRL
] = {
338 REG_A6XX_SP_HS_CTRL_REG0
,
339 REG_A6XX_SP_HS_CONFIG
,
340 REG_A6XX_HLSQ_HS_CNTL
,
341 REG_A6XX_SP_HS_OBJ_START_LO
,
343 [MESA_SHADER_TESS_EVAL
] = {
344 REG_A6XX_SP_DS_CTRL_REG0
,
345 REG_A6XX_SP_DS_CONFIG
,
346 REG_A6XX_HLSQ_DS_CNTL
,
347 REG_A6XX_SP_DS_OBJ_START_LO
,
349 [MESA_SHADER_GEOMETRY
] = {
350 REG_A6XX_SP_GS_CTRL_REG0
,
351 REG_A6XX_SP_GS_CONFIG
,
352 REG_A6XX_HLSQ_GS_CNTL
,
353 REG_A6XX_SP_GS_OBJ_START_LO
,
355 [MESA_SHADER_FRAGMENT
] = {
356 REG_A6XX_SP_FS_CTRL_REG0
,
357 REG_A6XX_SP_FS_CONFIG
,
358 REG_A6XX_HLSQ_FS_CNTL
,
359 REG_A6XX_SP_FS_OBJ_START_LO
,
361 [MESA_SHADER_COMPUTE
] = {
362 REG_A6XX_SP_CS_CTRL_REG0
,
363 REG_A6XX_SP_CS_CONFIG
,
364 REG_A6XX_HLSQ_CS_CNTL
,
365 REG_A6XX_SP_CS_OBJ_START_LO
,
368 const struct xs_config
*cfg
= &xs_config
[stage
];
371 /* shader stage disabled */
372 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 1);
375 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
380 bool is_fs
= xs
->type
== MESA_SHADER_FRAGMENT
;
381 enum a3xx_threadsize threadsize
= FOUR_QUADS
;
384 * the "threadsize" field may have nothing to do with threadsize,
385 * use a value that matches the blob until it is figured out
387 if (xs
->type
== MESA_SHADER_GEOMETRY
)
388 threadsize
= TWO_QUADS
;
390 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_ctrl
, 1);
392 A6XX_SP_VS_CTRL_REG0_THREADSIZE(threadsize
) |
393 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(xs
->info
.max_reg
+ 1) |
394 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(xs
->info
.max_half_reg
+ 1) |
395 COND(xs
->mergedregs
, A6XX_SP_VS_CTRL_REG0_MERGEDREGS
) |
396 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(xs
->branchstack
) |
397 COND(xs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
398 COND(xs
->need_fine_derivatives
, A6XX_SP_VS_CTRL_REG0_DIFF_FINE
) |
399 /* only fragment shader sets VARYING bit */
400 COND(xs
->total_in
&& is_fs
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
401 /* unknown bit, seems unnecessary */
402 COND(is_fs
, 0x1000000));
404 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_xs_config
, 2);
405 tu_cs_emit(cs
, A6XX_SP_VS_CONFIG_ENABLED
|
406 COND(xs
->bindless_tex
, A6XX_SP_VS_CONFIG_BINDLESS_TEX
) |
407 COND(xs
->bindless_samp
, A6XX_SP_VS_CONFIG_BINDLESS_SAMP
) |
408 COND(xs
->bindless_ibo
, A6XX_SP_VS_CONFIG_BINDLESS_IBO
) |
409 COND(xs
->bindless_ubo
, A6XX_SP_VS_CONFIG_BINDLESS_UBO
) |
410 A6XX_SP_VS_CONFIG_NTEX(xs
->num_samp
) |
411 A6XX_SP_VS_CONFIG_NSAMP(xs
->num_samp
));
412 tu_cs_emit(cs
, xs
->instrlen
);
414 tu_cs_emit_pkt4(cs
, cfg
->reg_hlsq_xs_ctrl
, 1);
415 tu_cs_emit(cs
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs
->constlen
, 4)) |
416 A6XX_HLSQ_VS_CNTL_ENABLED
);
418 /* emit program binary
419 * binary_iova should be aligned to 1 instrlen unit (128 bytes)
422 assert((binary_iova
& 0x7f) == 0);
424 tu_cs_emit_pkt4(cs
, cfg
->reg_sp_vs_obj_start
, 2);
425 tu_cs_emit_qw(cs
, binary_iova
);
427 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3);
428 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
429 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
430 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
431 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
432 CP_LOAD_STATE6_0_NUM_UNIT(xs
->instrlen
));
433 tu_cs_emit_qw(cs
, binary_iova
);
435 /* emit immediates */
437 const struct ir3_const_state
*const_state
= ir3_const_state(xs
);
438 uint32_t base
= const_state
->offsets
.immediate
;
439 int size
= const_state
->immediates_count
;
441 /* truncate size to avoid writing constants that shader
444 size
= MIN2(size
+ base
, xs
->constlen
) - base
;
449 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(stage
), 3 + size
* 4);
450 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
451 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
452 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
453 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(stage
)) |
454 CP_LOAD_STATE6_0_NUM_UNIT(size
));
455 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
456 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
458 for (unsigned i
= 0; i
< size
; i
++) {
459 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[0]);
460 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[1]);
461 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[2]);
462 tu_cs_emit(cs
, const_state
->immediates
[i
].val
[3]);
467 tu6_emit_cs_config(struct tu_cs
*cs
, const struct tu_shader
*shader
,
468 const struct ir3_shader_variant
*v
,
469 uint32_t binary_iova
)
471 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
472 tu_cs_emit(cs
, 0xff);
474 tu6_emit_xs_config(cs
, MESA_SHADER_COMPUTE
, v
, binary_iova
);
476 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
477 tu_cs_emit(cs
, 0x41);
479 uint32_t local_invocation_id
=
480 ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
481 uint32_t work_group_id
=
482 ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
484 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
486 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
487 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
488 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
489 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
490 tu_cs_emit(cs
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
494 tu6_emit_vs_system_values(struct tu_cs
*cs
,
495 const struct ir3_shader_variant
*vs
,
496 const struct ir3_shader_variant
*hs
,
497 const struct ir3_shader_variant
*ds
,
498 const struct ir3_shader_variant
*gs
,
499 bool primid_passthru
)
501 const uint32_t vertexid_regid
=
502 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
503 const uint32_t instanceid_regid
=
504 ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
505 const uint32_t tess_coord_x_regid
= hs
?
506 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
) :
508 const uint32_t tess_coord_y_regid
= VALIDREG(tess_coord_x_regid
) ?
509 tess_coord_x_regid
+ 1 :
511 const uint32_t hs_patch_regid
= hs
?
512 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
514 const uint32_t ds_patch_regid
= hs
?
515 ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
) :
517 const uint32_t hs_invocation_regid
= hs
?
518 ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
) :
520 const uint32_t primitiveid_regid
= gs
?
521 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
) :
523 const uint32_t gsheader_regid
= gs
?
524 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
) :
527 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_CONTROL_1
, 6);
528 tu_cs_emit(cs
, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid
) |
529 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid
) |
530 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid
) |
532 tu_cs_emit(cs
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
533 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
534 tu_cs_emit(cs
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
535 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
536 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
538 tu_cs_emit(cs
, 0x000000fc); /* VFD_CONTROL_4 */
539 tu_cs_emit(cs
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid
) |
540 0xfc00); /* VFD_CONTROL_5 */
541 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
544 /* Add any missing varyings needed for stream-out. Otherwise varyings not
545 * used by fragment shader will be stripped out.
548 tu6_link_streamout(struct ir3_shader_linkage
*l
,
549 const struct ir3_shader_variant
*v
)
551 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
554 * First, any stream-out varyings not already in linkage map (ie. also
555 * consumed by frag shader) need to be added:
557 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
558 const struct ir3_stream_output
*out
= &info
->output
[i
];
560 (1 << (out
->num_components
+ out
->start_component
)) - 1;
561 unsigned k
= out
->register_index
;
562 unsigned idx
, nextloc
= 0;
564 /* psize/pos need to be the last entries in linkage map, and will
565 * get added link_stream_out, so skip over them:
567 if (v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
||
568 v
->outputs
[k
].slot
== VARYING_SLOT_POS
)
571 for (idx
= 0; idx
< l
->cnt
; idx
++) {
572 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
574 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
577 /* add if not already in linkage map: */
579 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
581 /* expand component-mask if needed, ie streaming out all components
582 * but frag shader doesn't consume all components:
584 if (compmask
& ~l
->var
[idx
].compmask
) {
585 l
->var
[idx
].compmask
|= compmask
;
586 l
->max_loc
= MAX2(l
->max_loc
, l
->var
[idx
].loc
+
587 util_last_bit(l
->var
[idx
].compmask
));
593 tu6_setup_streamout(struct tu_cs
*cs
,
594 const struct ir3_shader_variant
*v
,
595 struct ir3_shader_linkage
*l
)
597 const struct ir3_stream_output_info
*info
= &v
->shader
->stream_output
;
598 uint32_t prog
[IR3_MAX_SO_OUTPUTS
* 2] = {};
599 uint32_t ncomp
[IR3_MAX_SO_BUFFERS
] = {};
600 uint32_t prog_count
= align(l
->max_loc
, 2) / 2;
602 /* TODO: streamout state should be in a non-GMEM draw state */
605 if (info
->num_outputs
== 0) {
606 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 4);
607 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
609 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
614 /* is there something to do with info->stride[i]? */
616 for (unsigned i
= 0; i
< info
->num_outputs
; i
++) {
617 const struct ir3_stream_output
*out
= &info
->output
[i
];
618 unsigned k
= out
->register_index
;
621 /* Skip it, if there's an unused reg in the middle of outputs. */
622 if (v
->outputs
[k
].regid
== INVALID_REG
)
625 ncomp
[out
->output_buffer
] += out
->num_components
;
627 /* linkage map sorted by order frag shader wants things, so
628 * a bit less ideal here..
630 for (idx
= 0; idx
< l
->cnt
; idx
++)
631 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
634 debug_assert(idx
< l
->cnt
);
636 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
637 unsigned c
= j
+ out
->start_component
;
638 unsigned loc
= l
->var
[idx
].loc
+ c
;
639 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
642 prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
643 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
644 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
646 prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
647 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
648 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
653 tu_cs_emit_pkt7(cs
, CP_CONTEXT_REG_BUNCH
, 12 + 2 * prog_count
);
654 tu_cs_emit(cs
, REG_A6XX_VPC_SO_BUF_CNTL
);
655 tu_cs_emit(cs
, A6XX_VPC_SO_BUF_CNTL_ENABLE
|
656 COND(ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
657 COND(ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
658 COND(ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
659 COND(ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
));
660 for (uint32_t i
= 0; i
< 4; i
++) {
661 tu_cs_emit(cs
, REG_A6XX_VPC_SO_NCOMP(i
));
662 tu_cs_emit(cs
, ncomp
[i
]);
664 /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
665 tu_cs_emit(cs
, REG_A6XX_VPC_SO_CNTL
);
666 tu_cs_emit(cs
, A6XX_VPC_SO_CNTL_ENABLE
);
667 for (uint32_t i
= 0; i
< prog_count
; i
++) {
668 tu_cs_emit(cs
, REG_A6XX_VPC_SO_PROG
);
669 tu_cs_emit(cs
, prog
[i
]);
674 tu6_emit_const(struct tu_cs
*cs
, uint32_t opcode
, uint32_t base
,
675 enum a6xx_state_block block
, uint32_t offset
,
676 uint32_t size
, uint32_t *dwords
) {
677 assert(size
% 4 == 0);
679 tu_cs_emit_pkt7(cs
, opcode
, 3 + size
);
680 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(base
) |
681 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
682 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
683 CP_LOAD_STATE6_0_STATE_BLOCK(block
) |
684 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 4));
686 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
687 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
688 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
690 tu_cs_emit_array(cs
, dwords
, size
);
694 tu6_emit_link_map(struct tu_cs
*cs
,
695 const struct ir3_shader_variant
*producer
,
696 const struct ir3_shader_variant
*consumer
,
697 enum a6xx_state_block sb
)
699 const struct ir3_const_state
*const_state
= ir3_const_state(consumer
);
700 uint32_t base
= const_state
->offsets
.primitive_map
;
701 uint32_t patch_locs
[MAX_VARYING
] = { }, num_loc
;
702 num_loc
= ir3_link_geometry_stages(producer
, consumer
, patch_locs
);
703 int size
= DIV_ROUND_UP(num_loc
, 4);
705 size
= (MIN2(size
+ base
, consumer
->constlen
) - base
) * 4;
709 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, base
, sb
, 0, size
,
714 gl_primitive_to_tess(uint16_t primitive
) {
720 case GL_TRIANGLE_STRIP
:
728 tu6_emit_vpc(struct tu_cs
*cs
,
729 const struct ir3_shader_variant
*vs
,
730 const struct ir3_shader_variant
*hs
,
731 const struct ir3_shader_variant
*ds
,
732 const struct ir3_shader_variant
*gs
,
733 const struct ir3_shader_variant
*fs
)
735 const struct ir3_shader_variant
*last_shader
;
743 struct ir3_shader_linkage linkage
= { .primid_loc
= 0xff };
745 ir3_link_shaders(&linkage
, last_shader
, fs
, true);
747 if (last_shader
->shader
->stream_output
.num_outputs
)
748 tu6_link_streamout(&linkage
, last_shader
);
750 /* We do this after linking shaders in order to know whether PrimID
751 * passthrough needs to be enabled.
753 bool primid_passthru
= linkage
.primid_loc
!= 0xff;
754 tu6_emit_vs_system_values(cs
, vs
, hs
, ds
, gs
, primid_passthru
);
756 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
757 tu_cs_emit(cs
, ~linkage
.varmask
[0]);
758 tu_cs_emit(cs
, ~linkage
.varmask
[1]);
759 tu_cs_emit(cs
, ~linkage
.varmask
[2]);
760 tu_cs_emit(cs
, ~linkage
.varmask
[3]);
762 /* a6xx finds position/pointsize at the end */
763 const uint32_t position_regid
=
764 ir3_find_output_regid(last_shader
, VARYING_SLOT_POS
);
765 const uint32_t pointsize_regid
=
766 ir3_find_output_regid(last_shader
, VARYING_SLOT_PSIZ
);
767 const uint32_t layer_regid
= gs
?
768 ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
) : regid(63, 0);
770 uint32_t pointsize_loc
= 0xff, position_loc
= 0xff, layer_loc
= 0xff;
771 if (layer_regid
!= regid(63, 0)) {
772 layer_loc
= linkage
.max_loc
;
773 ir3_link_add(&linkage
, layer_regid
, 0x1, linkage
.max_loc
);
775 if (position_regid
!= regid(63, 0)) {
776 position_loc
= linkage
.max_loc
;
777 ir3_link_add(&linkage
, position_regid
, 0xf, linkage
.max_loc
);
779 if (pointsize_regid
!= regid(63, 0)) {
780 pointsize_loc
= linkage
.max_loc
;
781 ir3_link_add(&linkage
, pointsize_regid
, 0x1, linkage
.max_loc
);
784 tu6_setup_streamout(cs
, last_shader
, &linkage
);
786 /* map outputs of the last shader to VPC */
787 assert(linkage
.cnt
<= 32);
788 const uint32_t sp_out_count
= DIV_ROUND_UP(linkage
.cnt
, 2);
789 const uint32_t sp_vpc_dst_count
= DIV_ROUND_UP(linkage
.cnt
, 4);
791 uint32_t sp_vpc_dst
[8];
792 for (uint32_t i
= 0; i
< linkage
.cnt
; i
++) {
793 ((uint16_t *) sp_out
)[i
] =
794 A6XX_SP_VS_OUT_REG_A_REGID(linkage
.var
[i
].regid
) |
795 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage
.var
[i
].compmask
);
796 ((uint8_t *) sp_vpc_dst
)[i
] =
797 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage
.var
[i
].loc
);
801 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count
);
803 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_OUT_REG(0), sp_out_count
);
805 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count
);
806 tu_cs_emit_array(cs
, sp_out
, sp_out_count
);
809 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count
);
811 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_VPC_DST_REG(0), sp_vpc_dst_count
);
813 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count
);
814 tu_cs_emit_array(cs
, sp_vpc_dst
, sp_vpc_dst_count
);
816 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMID_CNTL
, 1);
817 tu_cs_emit(cs
, COND(primid_passthru
, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU
));
819 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_CNTL_0
, 1);
820 tu_cs_emit(cs
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
? fs
->total_in
: 0) |
821 COND(fs
&& fs
->total_in
, A6XX_VPC_CNTL_0_VARYING
) |
822 A6XX_VPC_CNTL_0_PRIMIDLOC(linkage
.primid_loc
) |
823 A6XX_VPC_CNTL_0_UNKLOC(0xff));
825 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
826 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
827 A6XX_VPC_PACK_PSIZELOC(pointsize_loc
) |
828 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
831 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
832 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
833 tu_cs_emit(cs
, hs_info
->tess
.tcs_vertices_out
);
835 /* Total attribute slots in HS incoming patch. */
836 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9801
, 1);
838 hs_info
->tess
.tcs_vertices_out
* vs
->output_size
/ 4);
840 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
841 tu_cs_emit(cs
, vs
->output_size
);
842 /* In SPIR-V generated from GLSL, the tessellation primitive params are
843 * are specified in the tess eval shader, but in SPIR-V generated from
844 * HLSL, they are specified in the tess control shader. */
845 shader_info
*tess_info
=
846 ds
->shader
->nir
->info
.tess
.spacing
== TESS_SPACING_UNSPECIFIED
?
847 &hs
->shader
->nir
->info
: &ds
->shader
->nir
->info
;
848 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESS_CNTL
, 1);
850 if (tess_info
->tess
.point_mode
)
851 output
= TESS_POINTS
;
852 else if (tess_info
->tess
.primitive_mode
== GL_ISOLINES
)
854 else if (tess_info
->tess
.ccw
)
855 output
= TESS_CCW_TRIS
;
857 output
= TESS_CW_TRIS
;
859 enum a6xx_tess_spacing spacing
;
860 switch (tess_info
->tess
.spacing
) {
861 case TESS_SPACING_EQUAL
:
862 spacing
= TESS_EQUAL
;
864 case TESS_SPACING_FRACTIONAL_ODD
:
865 spacing
= TESS_FRACTIONAL_ODD
;
867 case TESS_SPACING_FRACTIONAL_EVEN
:
868 spacing
= TESS_FRACTIONAL_EVEN
;
870 case TESS_SPACING_UNSPECIFIED
:
872 unreachable("invalid tess spacing");
874 tu_cs_emit(cs
, A6XX_PC_TESS_CNTL_SPACING(spacing
) |
875 A6XX_PC_TESS_CNTL_OUTPUT(output
));
877 /* xxx: Misc tess unknowns: */
878 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9103
, 1);
879 tu_cs_emit(cs
, 0x00ffff00);
881 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9106
, 1);
882 tu_cs_emit(cs
, 0x0000ffff);
884 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809D
, 1);
887 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8002
, 1);
890 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK
, 1);
891 tu_cs_emit(cs
, A6XX_VPC_PACK_POSITIONLOC(position_loc
) |
892 A6XX_VPC_PACK_PSIZELOC(255) |
893 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage
.max_loc
));
895 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_3
, 1);
896 tu_cs_emit(cs
, A6XX_VPC_PACK_3_POSITIONLOC(position_loc
) |
897 A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc
) |
898 A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage
.max_loc
));
900 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_DS_PRIMITIVE_CNTL
, 1);
901 tu_cs_emit(cs
, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage
.cnt
));
903 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_4
, 1);
904 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage
.max_loc
) |
905 CONDREG(pointsize_regid
, 0x100));
907 tu6_emit_link_map(cs
, vs
, hs
, SB6_HS_SHADER
);
908 tu6_emit_link_map(cs
, hs
, ds
, SB6_DS_SHADER
);
913 uint32_t vertices_out
, invocations
, output
, vec4_size
;
914 /* this detects the tu_clear_blit path, which doesn't set ->nir */
915 if (gs
->shader
->nir
) {
917 tu6_emit_link_map(cs
, ds
, gs
, SB6_GS_SHADER
);
919 tu6_emit_link_map(cs
, vs
, gs
, SB6_GS_SHADER
);
921 vertices_out
= gs
->shader
->nir
->info
.gs
.vertices_out
- 1;
922 output
= gl_primitive_to_tess(gs
->shader
->nir
->info
.gs
.output_primitive
);
923 invocations
= gs
->shader
->nir
->info
.gs
.invocations
- 1;
924 /* Size of per-primitive alloction in ldlw memory in vec4s. */
925 vec4_size
= gs
->shader
->nir
->info
.gs
.vertices_in
*
926 DIV_ROUND_UP(vs
->output_size
, 4);
929 output
= TESS_CW_TRIS
;
934 uint32_t primitive_regid
=
935 ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
936 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_PACK_GS
, 1);
937 tu_cs_emit(cs
, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc
) |
938 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc
) |
939 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage
.max_loc
));
941 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
942 tu_cs_emit(cs
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
944 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
945 tu_cs_emit(cs
, CONDREG(layer_regid
,
946 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
948 uint32_t flags_regid
= ir3_find_output_regid(gs
,
949 VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
951 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
952 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage
.cnt
) |
953 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
955 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
956 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage
.max_loc
) |
957 CONDREG(pointsize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
958 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
959 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
961 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
963 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out
) |
964 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
965 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations
));
967 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
970 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
973 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
974 tu_cs_emit(cs
, 0xff);
976 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
977 tu_cs_emit(cs
, 0xffff00);
979 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
980 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
982 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
985 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
986 tu_cs_emit(cs
, vs
->output_size
);
989 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
990 tu_cs_emit(cs
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage
.cnt
));
992 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
993 tu_cs_emit(cs
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage
.max_loc
) |
994 (last_shader
->writes_psize
? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
: 0));
998 tu6_vpc_varying_mode(const struct ir3_shader_variant
*fs
,
1000 uint8_t *interp_mode
,
1001 uint8_t *ps_repl_mode
)
1015 PS_REPL_ONE_MINUS_T
= 3,
1018 const uint32_t compmask
= fs
->inputs
[index
].compmask
;
1020 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1021 * fourth component occupy three consecutive varying slots
1026 if (fs
->inputs
[index
].slot
== VARYING_SLOT_PNTC
) {
1027 if (compmask
& 0x1) {
1028 *ps_repl_mode
|= PS_REPL_S
<< shift
;
1031 if (compmask
& 0x2) {
1032 *ps_repl_mode
|= PS_REPL_T
<< shift
;
1035 if (compmask
& 0x4) {
1036 *interp_mode
|= INTERP_ZERO
<< shift
;
1039 if (compmask
& 0x8) {
1040 *interp_mode
|= INTERP_ONE
<< 6;
1043 } else if ((fs
->inputs
[index
].interpolate
== INTERP_MODE_FLAT
) ||
1044 fs
->inputs
[index
].rasterflat
) {
1045 for (int i
= 0; i
< 4; i
++) {
1046 if (compmask
& (1 << i
)) {
1047 *interp_mode
|= INTERP_FLAT
<< shift
;
1057 tu6_emit_vpc_varying_modes(struct tu_cs
*cs
,
1058 const struct ir3_shader_variant
*fs
)
1060 uint32_t interp_modes
[8] = { 0 };
1061 uint32_t ps_repl_modes
[8] = { 0 };
1065 (i
= ir3_next_varying(fs
, i
)) < (int) fs
->inputs_count
;) {
1067 /* get the mode for input i */
1068 uint8_t interp_mode
;
1069 uint8_t ps_repl_mode
;
1071 tu6_vpc_varying_mode(fs
, i
, &interp_mode
, &ps_repl_mode
);
1073 /* OR the mode into the array */
1074 const uint32_t inloc
= fs
->inputs
[i
].inloc
* 2;
1075 uint32_t n
= inloc
/ 32;
1076 uint32_t shift
= inloc
% 32;
1077 interp_modes
[n
] |= interp_mode
<< shift
;
1078 ps_repl_modes
[n
] |= ps_repl_mode
<< shift
;
1079 if (shift
+ bits
> 32) {
1083 interp_modes
[n
] |= interp_mode
>> shift
;
1084 ps_repl_modes
[n
] |= ps_repl_mode
>> shift
;
1089 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1090 tu_cs_emit_array(cs
, interp_modes
, 8);
1092 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1093 tu_cs_emit_array(cs
, ps_repl_modes
, 8);
1097 tu6_emit_fs_inputs(struct tu_cs
*cs
, const struct ir3_shader_variant
*fs
)
1099 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
1100 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
1101 uint32_t smask_in_regid
;
1103 bool sample_shading
= fs
->per_samp
| fs
->key
.sample_shading
;
1104 bool enable_varyings
= fs
->total_in
> 0;
1106 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
1107 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
1108 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
1109 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
1110 zwcoord_regid
= VALIDREG(coord_regid
) ? coord_regid
+ 2 : regid(63, 0);
1111 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1112 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1113 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1114 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1116 if (fs
->num_sampler_prefetch
> 0) {
1117 assert(VALIDREG(ij_pix_regid
));
1118 /* also, it seems like ij_pix is *required* to be r0.x */
1119 assert(ij_pix_regid
== regid(0, 0));
1122 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
1123 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
1124 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1126 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1127 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1128 tu_cs_emit(cs
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
1129 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
1130 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
1131 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
1132 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
1133 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
1134 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
1137 if (fs
->num_sampler_prefetch
> 0) {
1138 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs
->num_sampler_prefetch
);
1139 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
1140 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
1142 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_bindless_id
) |
1143 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch
->tex_bindless_id
));
1147 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
1148 tu_cs_emit(cs
, 0x7);
1149 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
1150 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
1151 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
1152 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
1153 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
1154 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
1156 tu_cs_emit(cs
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
1157 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
1158 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
1160 tu_cs_emit(cs
, 0xfc);
1162 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
1163 tu_cs_emit(cs
, enable_varyings
? 3 : 1);
1165 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CNTL
, 1);
1167 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
1168 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
1169 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
1170 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
1171 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
1172 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_SIZE
|
1173 A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)) |
1174 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
1176 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
1178 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
1179 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
1180 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
1181 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
1182 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
1183 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
1184 COND(fs
->fragcoord_compmask
!= 0, A6XX_RB_RENDER_CONTROL0_SIZE
|
1185 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)) |
1186 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
1188 /* these two bits (UNK4/UNK5) relate to fragcoord
1189 * without them, fragcoord is the same for all samples
1191 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK4
) |
1192 COND(sample_shading
, A6XX_RB_RENDER_CONTROL1_UNK5
) |
1193 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
1194 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
1195 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
1196 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
1198 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
1199 tu_cs_emit(cs
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
1201 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
1202 tu_cs_emit(cs
, COND(sample_shading
, 0x6)); // XXX
1204 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
1205 tu_cs_emit(cs
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
1209 tu6_emit_fs_outputs(struct tu_cs
*cs
,
1210 const struct ir3_shader_variant
*fs
,
1211 uint32_t mrt_count
, bool dual_src_blend
,
1212 uint32_t render_components
)
1214 uint32_t smask_regid
, posz_regid
;
1216 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
1217 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
1219 uint32_t fragdata_regid
[8];
1220 if (fs
->color0_mrt
) {
1221 fragdata_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
1222 for (uint32_t i
= 1; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1223 fragdata_regid
[i
] = fragdata_regid
[0];
1225 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++)
1226 fragdata_regid
[i
] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
+ i
);
1229 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 2);
1230 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
1231 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
1232 COND(dual_src_blend
, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
) |
1234 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1236 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1237 for (uint32_t i
= 0; i
< ARRAY_SIZE(fragdata_regid
); i
++) {
1238 // TODO we could have a mix of half and full precision outputs,
1239 // we really need to figure out half-precision from IR3_REG_HALF
1240 tu_cs_emit(cs
, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid
[i
]) |
1241 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
: 0));
1245 A6XX_SP_FS_RENDER_COMPONENTS(.dword
= render_components
));
1247 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 2);
1248 tu_cs_emit(cs
, COND(fs
->writes_pos
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z
) |
1249 COND(fs
->writes_smask
, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK
) |
1250 COND(dual_src_blend
, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE
));
1251 tu_cs_emit(cs
, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count
));
1254 A6XX_RB_RENDER_COMPONENTS(.dword
= render_components
));
1256 enum a6xx_ztest_mode zmode
;
1258 if (fs
->no_earlyz
|| fs
->has_kill
|| fs
->writes_pos
) {
1259 zmode
= A6XX_LATE_Z
;
1261 zmode
= A6XX_EARLY_Z
;
1264 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
1265 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1267 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
1268 tu_cs_emit(cs
, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode
));
1272 tu6_emit_geom_tess_consts(struct tu_cs
*cs
,
1273 const struct ir3_shader_variant
*vs
,
1274 const struct ir3_shader_variant
*hs
,
1275 const struct ir3_shader_variant
*ds
,
1276 const struct ir3_shader_variant
*gs
,
1277 uint32_t cps_per_patch
)
1279 uint32_t num_vertices
=
1280 hs
? cps_per_patch
: gs
->shader
->nir
->info
.gs
.vertices_in
;
1282 uint32_t vs_params
[4] = {
1283 vs
->output_size
* num_vertices
* 4, /* vs primitive stride */
1284 vs
->output_size
* 4, /* vs vertex stride */
1288 uint32_t vs_base
= ir3_const_state(vs
)->offsets
.primitive_param
;
1289 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, vs_base
, SB6_VS_SHADER
, 0,
1290 ARRAY_SIZE(vs_params
), vs_params
);
1293 assert(ds
->type
!= MESA_SHADER_NONE
);
1294 uint32_t hs_params
[4] = {
1295 vs
->output_size
* num_vertices
* 4, /* hs primitive stride */
1296 vs
->output_size
* 4, /* hs vertex stride */
1301 uint32_t hs_base
= hs
->const_state
->offsets
.primitive_param
;
1302 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, hs_base
, SB6_HS_SHADER
, 0,
1303 ARRAY_SIZE(hs_params
), hs_params
);
1305 num_vertices
= gs
->shader
->nir
->info
.gs
.vertices_in
;
1307 uint32_t ds_params
[4] = {
1308 ds
->output_size
* num_vertices
* 4, /* ds primitive stride */
1309 ds
->output_size
* 4, /* ds vertex stride */
1310 hs
->output_size
, /* hs vertex stride (dwords) */
1311 hs
->shader
->nir
->info
.tess
.tcs_vertices_out
1314 uint32_t ds_base
= ds
->const_state
->offsets
.primitive_param
;
1315 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, ds_base
, SB6_DS_SHADER
, 0,
1316 ARRAY_SIZE(ds_params
), ds_params
);
1320 const struct ir3_shader_variant
*prev
= ds
? ds
: vs
;
1321 uint32_t gs_params
[4] = {
1322 prev
->output_size
* num_vertices
* 4, /* gs primitive stride */
1323 prev
->output_size
* 4, /* gs vertex stride */
1327 uint32_t gs_base
= gs
->const_state
->offsets
.primitive_param
;
1328 tu6_emit_const(cs
, CP_LOAD_STATE6_GEOM
, gs_base
, SB6_GS_SHADER
, 0,
1329 ARRAY_SIZE(gs_params
), gs_params
);
1334 tu6_emit_program(struct tu_cs
*cs
,
1335 struct tu_pipeline_builder
*builder
,
1338 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
1339 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
1340 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
1341 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
1342 const struct ir3_shader_variant
*gs
= builder
->variants
[MESA_SHADER_GEOMETRY
];
1343 const struct ir3_shader_variant
*fs
= builder
->variants
[MESA_SHADER_FRAGMENT
];
1344 gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1346 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
1348 tu_cs_emit_pkt4(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
1349 tu_cs_emit(cs
, 0xff); /* XXX */
1351 /* Don't use the binning pass variant when GS is present because we don't
1352 * support compiling correct binning pass variants with GS.
1354 if (binning_pass
&& !gs
) {
1356 tu6_emit_xs_config(cs
, stage
, bs
, builder
->binning_vs_iova
);
1360 for (; stage
< ARRAY_SIZE(builder
->shaders
); stage
++) {
1361 const struct ir3_shader_variant
*xs
= builder
->variants
[stage
];
1363 if (stage
== MESA_SHADER_FRAGMENT
&& binning_pass
)
1366 tu6_emit_xs_config(cs
, stage
, xs
, builder
->shader_iova
[stage
]);
1369 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
1372 tu6_emit_vpc(cs
, vs
, hs
, ds
, gs
, fs
);
1373 tu6_emit_vpc_varying_modes(cs
, fs
);
1376 tu6_emit_fs_inputs(cs
, fs
);
1377 tu6_emit_fs_outputs(cs
, fs
, builder
->color_attachment_count
,
1378 builder
->use_dual_src_blend
,
1379 builder
->render_components
);
1381 /* TODO: check if these can be skipped if fs is disabled */
1382 struct ir3_shader_variant dummy_variant
= {};
1383 tu6_emit_fs_inputs(cs
, &dummy_variant
);
1384 tu6_emit_fs_outputs(cs
, &dummy_variant
, builder
->color_attachment_count
,
1385 builder
->use_dual_src_blend
,
1386 builder
->render_components
);
1390 uint32_t cps_per_patch
= builder
->create_info
->pTessellationState
?
1391 builder
->create_info
->pTessellationState
->patchControlPoints
: 0;
1392 tu6_emit_geom_tess_consts(cs
, vs
, hs
, ds
, gs
, cps_per_patch
);
1397 tu6_emit_vertex_input(struct tu_cs
*cs
,
1398 const struct ir3_shader_variant
*vs
,
1399 const VkPipelineVertexInputStateCreateInfo
*info
,
1400 uint32_t *bindings_used
)
1402 uint32_t vfd_decode_idx
= 0;
1403 uint32_t binding_instanced
= 0; /* bitmask of instanced bindings */
1405 for (uint32_t i
= 0; i
< info
->vertexBindingDescriptionCount
; i
++) {
1406 const VkVertexInputBindingDescription
*binding
=
1407 &info
->pVertexBindingDescriptions
[i
];
1410 A6XX_VFD_FETCH_STRIDE(binding
->binding
, binding
->stride
));
1412 if (binding
->inputRate
== VK_VERTEX_INPUT_RATE_INSTANCE
)
1413 binding_instanced
|= 1 << binding
->binding
;
1415 *bindings_used
|= 1 << binding
->binding
;
1418 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1420 for (uint32_t i
= 0; i
< info
->vertexAttributeDescriptionCount
; i
++) {
1421 const VkVertexInputAttributeDescription
*attr
=
1422 &info
->pVertexAttributeDescriptions
[i
];
1425 for (input_idx
= 0; input_idx
< vs
->inputs_count
; input_idx
++) {
1426 if ((vs
->inputs
[input_idx
].slot
- VERT_ATTRIB_GENERIC0
) == attr
->location
)
1430 /* attribute not used, skip it */
1431 if (input_idx
== vs
->inputs_count
)
1434 const struct tu_native_format format
= tu6_format_vtx(attr
->format
);
1436 A6XX_VFD_DECODE_INSTR(vfd_decode_idx
,
1437 .idx
= attr
->binding
,
1438 .offset
= attr
->offset
,
1439 .instanced
= binding_instanced
& (1 << attr
->binding
),
1440 .format
= format
.fmt
,
1441 .swap
= format
.swap
,
1443 ._float
= !vk_format_is_int(attr
->format
)),
1444 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx
, 1));
1447 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx
,
1448 .writemask
= vs
->inputs
[input_idx
].compmask
,
1449 .regid
= vs
->inputs
[input_idx
].regid
));
1456 .fetch_cnt
= vfd_decode_idx
, /* decode_cnt for binning pass ? */
1457 .decode_cnt
= vfd_decode_idx
));
1461 tu6_guardband_adj(uint32_t v
)
1464 return (uint32_t)(511.0 - 65.0 * (log2(v
) - 8.0));
1470 tu6_emit_viewport(struct tu_cs
*cs
, const VkViewport
*viewport
)
1474 scales
[0] = viewport
->width
/ 2.0f
;
1475 scales
[1] = viewport
->height
/ 2.0f
;
1476 scales
[2] = viewport
->maxDepth
- viewport
->minDepth
;
1477 offsets
[0] = viewport
->x
+ scales
[0];
1478 offsets
[1] = viewport
->y
+ scales
[1];
1479 offsets
[2] = viewport
->minDepth
;
1483 min
.x
= (int32_t) viewport
->x
;
1484 max
.x
= (int32_t) ceilf(viewport
->x
+ viewport
->width
);
1485 if (viewport
->height
>= 0.0f
) {
1486 min
.y
= (int32_t) viewport
->y
;
1487 max
.y
= (int32_t) ceilf(viewport
->y
+ viewport
->height
);
1489 min
.y
= (int32_t)(viewport
->y
+ viewport
->height
);
1490 max
.y
= (int32_t) ceilf(viewport
->y
);
1492 /* the spec allows viewport->height to be 0.0f */
1495 assert(min
.x
>= 0 && min
.x
< max
.x
);
1496 assert(min
.y
>= 0 && min
.y
< max
.y
);
1498 VkExtent2D guardband_adj
;
1499 guardband_adj
.width
= tu6_guardband_adj(max
.x
- min
.x
);
1500 guardband_adj
.height
= tu6_guardband_adj(max
.y
- min
.y
);
1502 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
1503 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets
[0]).value
);
1504 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_XSCALE_0(scales
[0]).value
);
1505 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets
[1]).value
);
1506 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_YSCALE_0(scales
[1]).value
);
1507 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets
[2]).value
);
1508 tu_cs_emit(cs
, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales
[2]).value
);
1510 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
1511 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min
.x
) |
1512 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min
.y
));
1513 tu_cs_emit(cs
, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max
.x
- 1) |
1514 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max
.y
- 1));
1516 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
, 1);
1518 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj
.width
) |
1519 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj
.height
));
1521 float z_clamp_min
= MIN2(viewport
->minDepth
, viewport
->maxDepth
);
1522 float z_clamp_max
= MAX2(viewport
->minDepth
, viewport
->maxDepth
);
1525 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min
),
1526 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max
));
1529 A6XX_RB_Z_CLAMP_MIN(z_clamp_min
),
1530 A6XX_RB_Z_CLAMP_MAX(z_clamp_max
));
1534 tu6_emit_scissor(struct tu_cs
*cs
, const VkRect2D
*scissor
)
1536 const VkOffset2D min
= scissor
->offset
;
1537 const VkOffset2D max
= {
1538 scissor
->offset
.x
+ scissor
->extent
.width
,
1539 scissor
->offset
.y
+ scissor
->extent
.height
,
1542 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
1543 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min
.x
) |
1544 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min
.y
));
1545 tu_cs_emit(cs
, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max
.x
- 1) |
1546 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max
.y
- 1));
1550 tu6_emit_sample_locations(struct tu_cs
*cs
, const VkSampleLocationsInfoEXT
*samp_loc
)
1553 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 1);
1556 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 1);
1559 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 1);
1564 assert(samp_loc
->sampleLocationsPerPixel
== samp_loc
->sampleLocationsCount
);
1565 assert(samp_loc
->sampleLocationGridSize
.width
== 1);
1566 assert(samp_loc
->sampleLocationGridSize
.height
== 1);
1568 uint32_t sample_config
=
1569 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE
;
1570 uint32_t sample_locations
= 0;
1571 for (uint32_t i
= 0; i
< samp_loc
->sampleLocationsCount
; i
++) {
1573 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc
->pSampleLocations
[i
].x
) |
1574 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc
->pSampleLocations
[i
].y
)) << i
*8;
1577 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SAMPLE_CONFIG
, 2);
1578 tu_cs_emit(cs
, sample_config
);
1579 tu_cs_emit(cs
, sample_locations
);
1581 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SAMPLE_CONFIG
, 2);
1582 tu_cs_emit(cs
, sample_config
);
1583 tu_cs_emit(cs
, sample_locations
);
1585 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_SAMPLE_CONFIG
, 2);
1586 tu_cs_emit(cs
, sample_config
);
1587 tu_cs_emit(cs
, sample_locations
);
1591 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo
*rast_info
,
1592 VkSampleCountFlagBits samples
)
1594 uint32_t gras_su_cntl
= 0;
1596 if (rast_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)
1597 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_FRONT
;
1598 if (rast_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)
1599 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_CULL_BACK
;
1601 if (rast_info
->frontFace
== VK_FRONT_FACE_CLOCKWISE
)
1602 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_FRONT_CW
;
1604 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1606 if (rast_info
->depthBiasEnable
)
1607 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_POLY_OFFSET
;
1609 if (samples
> VK_SAMPLE_COUNT_1_BIT
)
1610 gras_su_cntl
|= A6XX_GRAS_SU_CNTL_MSAA_ENABLE
;
1612 return gras_su_cntl
;
1616 tu6_emit_depth_bias(struct tu_cs
*cs
,
1617 float constant_factor
,
1621 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
1622 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor
).value
);
1623 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor
).value
);
1624 tu_cs_emit(cs
, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp
).value
);
1628 tu6_emit_depth_control(struct tu_cs
*cs
,
1629 const VkPipelineDepthStencilStateCreateInfo
*ds_info
,
1630 const VkPipelineRasterizationStateCreateInfo
*rast_info
)
1632 uint32_t rb_depth_cntl
= 0;
1633 if (ds_info
->depthTestEnable
) {
1635 A6XX_RB_DEPTH_CNTL_Z_ENABLE
|
1636 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info
->depthCompareOp
)) |
1637 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
; /* TODO: don't set for ALWAYS/NEVER */
1639 if (rast_info
->depthClampEnable
)
1640 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE
;
1642 if (ds_info
->depthWriteEnable
)
1643 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE
;
1646 if (ds_info
->depthBoundsTestEnable
)
1647 rb_depth_cntl
|= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE
| A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE
;
1649 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_CNTL
, 1);
1650 tu_cs_emit(cs
, rb_depth_cntl
);
1654 tu6_emit_stencil_control(struct tu_cs
*cs
,
1655 const VkPipelineDepthStencilStateCreateInfo
*ds_info
)
1657 uint32_t rb_stencil_control
= 0;
1658 if (ds_info
->stencilTestEnable
) {
1659 const VkStencilOpState
*front
= &ds_info
->front
;
1660 const VkStencilOpState
*back
= &ds_info
->back
;
1661 rb_stencil_control
|=
1662 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
1663 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF
|
1664 A6XX_RB_STENCIL_CONTROL_STENCIL_READ
|
1665 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front
->compareOp
)) |
1666 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front
->failOp
)) |
1667 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front
->passOp
)) |
1668 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front
->depthFailOp
)) |
1669 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back
->compareOp
)) |
1670 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back
->failOp
)) |
1671 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back
->passOp
)) |
1672 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back
->depthFailOp
));
1675 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_CONTROL
, 1);
1676 tu_cs_emit(cs
, rb_stencil_control
);
1680 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState
*att
,
1683 const enum a3xx_rb_blend_opcode color_op
= tu6_blend_op(att
->colorBlendOp
);
1684 const enum adreno_rb_blend_factor src_color_factor
= tu6_blend_factor(
1685 has_alpha
? att
->srcColorBlendFactor
1686 : tu_blend_factor_no_dst_alpha(att
->srcColorBlendFactor
));
1687 const enum adreno_rb_blend_factor dst_color_factor
= tu6_blend_factor(
1688 has_alpha
? att
->dstColorBlendFactor
1689 : tu_blend_factor_no_dst_alpha(att
->dstColorBlendFactor
));
1690 const enum a3xx_rb_blend_opcode alpha_op
= tu6_blend_op(att
->alphaBlendOp
);
1691 const enum adreno_rb_blend_factor src_alpha_factor
=
1692 tu6_blend_factor(att
->srcAlphaBlendFactor
);
1693 const enum adreno_rb_blend_factor dst_alpha_factor
=
1694 tu6_blend_factor(att
->dstAlphaBlendFactor
);
1696 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor
) |
1697 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op
) |
1698 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor
) |
1699 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor
) |
1700 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op
) |
1701 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor
);
1705 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState
*att
,
1706 uint32_t rb_mrt_control_rop
,
1710 uint32_t rb_mrt_control
=
1711 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att
->colorWriteMask
);
1713 /* ignore blending and logic op for integer attachments */
1715 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
1716 return rb_mrt_control
;
1719 rb_mrt_control
|= rb_mrt_control_rop
;
1721 if (att
->blendEnable
) {
1722 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND
;
1725 rb_mrt_control
|= A6XX_RB_MRT_CONTROL_BLEND2
;
1728 return rb_mrt_control
;
1732 tu6_emit_rb_mrt_controls(struct tu_cs
*cs
,
1733 const VkPipelineColorBlendStateCreateInfo
*blend_info
,
1734 const VkFormat attachment_formats
[MAX_RTS
],
1735 uint32_t *blend_enable_mask
)
1737 *blend_enable_mask
= 0;
1739 bool rop_reads_dst
= false;
1740 uint32_t rb_mrt_control_rop
= 0;
1741 if (blend_info
->logicOpEnable
) {
1742 rop_reads_dst
= tu_logic_op_reads_dst(blend_info
->logicOp
);
1743 rb_mrt_control_rop
=
1744 A6XX_RB_MRT_CONTROL_ROP_ENABLE
|
1745 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info
->logicOp
));
1748 for (uint32_t i
= 0; i
< blend_info
->attachmentCount
; i
++) {
1749 const VkPipelineColorBlendAttachmentState
*att
=
1750 &blend_info
->pAttachments
[i
];
1751 const VkFormat format
= attachment_formats
[i
];
1753 uint32_t rb_mrt_control
= 0;
1754 uint32_t rb_mrt_blend_control
= 0;
1755 if (format
!= VK_FORMAT_UNDEFINED
) {
1756 const bool is_int
= vk_format_is_int(format
);
1757 const bool has_alpha
= vk_format_has_alpha(format
);
1760 tu6_rb_mrt_control(att
, rb_mrt_control_rop
, is_int
, has_alpha
);
1761 rb_mrt_blend_control
= tu6_rb_mrt_blend_control(att
, has_alpha
);
1763 if (att
->blendEnable
|| rop_reads_dst
)
1764 *blend_enable_mask
|= 1 << i
;
1767 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_CONTROL(i
), 2);
1768 tu_cs_emit(cs
, rb_mrt_control
);
1769 tu_cs_emit(cs
, rb_mrt_blend_control
);
1774 tu6_emit_blend_control(struct tu_cs
*cs
,
1775 uint32_t blend_enable_mask
,
1776 bool dual_src_blend
,
1777 const VkPipelineMultisampleStateCreateInfo
*msaa_info
)
1779 const uint32_t sample_mask
=
1780 msaa_info
->pSampleMask
? (*msaa_info
->pSampleMask
& 0xffff)
1781 : ((1 << msaa_info
->rasterizationSamples
) - 1);
1784 A6XX_SP_BLEND_CNTL(.enabled
= blend_enable_mask
,
1785 .dual_color_in_enable
= dual_src_blend
,
1786 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1789 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1791 A6XX_RB_BLEND_CNTL(.enable_blend
= blend_enable_mask
,
1792 .independent_blend
= true,
1793 .sample_mask
= sample_mask
,
1794 .dual_color_in_enable
= dual_src_blend
,
1795 .alpha_to_coverage
= msaa_info
->alphaToCoverageEnable
,
1796 .alpha_to_one
= msaa_info
->alphaToOneEnable
));
1800 tu_pipeline_allocate_cs(struct tu_device
*dev
,
1801 struct tu_pipeline
*pipeline
,
1802 struct tu_pipeline_builder
*builder
,
1803 struct ir3_shader_variant
*compute
)
1805 uint32_t size
= 2048 + tu6_load_state_size(pipeline
->layout
, compute
);
1807 /* graphics case: */
1809 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
1810 if (builder
->variants
[i
])
1811 size
+= builder
->variants
[i
]->info
.sizedwords
;
1814 size
+= builder
->binning_variant
->info
.sizedwords
;
1816 size
+= compute
->info
.sizedwords
;
1819 tu_cs_init(&pipeline
->cs
, dev
, TU_CS_MODE_SUB_STREAM
, size
);
1821 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
1822 * that LOAD_STATE can potentially take up a large amount of space so we
1823 * calculate its size explicitly.
1825 return tu_cs_reserve_space(&pipeline
->cs
, size
);
1829 tu_pipeline_shader_key_init(struct ir3_shader_key
*key
,
1830 const VkGraphicsPipelineCreateInfo
*pipeline_info
)
1832 for (uint32_t i
= 0; i
< pipeline_info
->stageCount
; i
++) {
1833 if (pipeline_info
->pStages
[i
].stage
== VK_SHADER_STAGE_GEOMETRY_BIT
) {
1839 if (pipeline_info
->pRasterizationState
->rasterizerDiscardEnable
)
1842 const VkPipelineMultisampleStateCreateInfo
*msaa_info
= pipeline_info
->pMultisampleState
;
1843 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
1844 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1845 if (msaa_info
->rasterizationSamples
> 1 ||
1846 /* also set msaa key when sample location is not the default
1847 * since this affects varying interpolation */
1848 (sample_locations
&& sample_locations
->sampleLocationsEnable
)) {
1852 /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
1853 if (msaa_info
->sampleShadingEnable
)
1854 key
->sample_shading
= true;
1856 /* We set this after we compile to NIR because we need the prim mode */
1857 key
->tessellation
= IR3_TESS_NONE
;
1861 tu6_get_tessmode(struct tu_shader
* shader
)
1863 uint32_t primitive_mode
= shader
->ir3_shader
->nir
->info
.tess
.primitive_mode
;
1864 switch (primitive_mode
) {
1866 return IR3_TESS_ISOLINES
;
1868 return IR3_TESS_TRIANGLES
;
1870 return IR3_TESS_QUADS
;
1872 return IR3_TESS_NONE
;
1874 unreachable("bad tessmode");
1879 tu_upload_variant(struct tu_pipeline
*pipeline
,
1880 const struct ir3_shader_variant
*variant
)
1882 struct tu_cs_memory memory
;
1887 /* this expects to get enough alignment because shaders are allocated first
1888 * and sizedwords is always aligned correctly
1889 * note: an assert in tu6_emit_xs_config validates the alignment
1891 tu_cs_alloc(&pipeline
->cs
, variant
->info
.sizedwords
, 1, &memory
);
1893 memcpy(memory
.map
, variant
->bin
, sizeof(uint32_t) * variant
->info
.sizedwords
);
1898 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder
*builder
,
1899 struct tu_pipeline
*pipeline
)
1901 const VkPipelineShaderStageCreateInfo
*stage_infos
[MESA_SHADER_STAGES
] = {
1904 for (uint32_t i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
1905 gl_shader_stage stage
=
1906 vk_to_mesa_shader_stage(builder
->create_info
->pStages
[i
].stage
);
1907 stage_infos
[stage
] = &builder
->create_info
->pStages
[i
];
1910 struct ir3_shader_key key
= {};
1911 tu_pipeline_shader_key_init(&key
, builder
->create_info
);
1913 for (gl_shader_stage stage
= MESA_SHADER_VERTEX
;
1914 stage
< MESA_SHADER_STAGES
; stage
++) {
1915 const VkPipelineShaderStageCreateInfo
*stage_info
= stage_infos
[stage
];
1916 if (!stage_info
&& stage
!= MESA_SHADER_FRAGMENT
)
1919 struct tu_shader
*shader
=
1920 tu_shader_create(builder
->device
, stage
, stage_info
, builder
->layout
,
1923 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1925 /* In SPIR-V generated from GLSL, the primitive mode is specified in the
1926 * tessellation evaluation shader, but in SPIR-V generated from HLSL,
1927 * the mode is specified in the tessellation control shader. */
1928 if ((stage
== MESA_SHADER_TESS_EVAL
|| stage
== MESA_SHADER_TESS_CTRL
) &&
1929 key
.tessellation
== IR3_TESS_NONE
) {
1930 key
.tessellation
= tu6_get_tessmode(shader
);
1933 builder
->shaders
[stage
] = shader
;
1936 pipeline
->tess
.patch_type
= key
.tessellation
;
1938 for (gl_shader_stage stage
= MESA_SHADER_STAGES
- 1;
1939 stage
> MESA_SHADER_NONE
; stage
--) {
1940 if (!builder
->shaders
[stage
])
1944 builder
->variants
[stage
] =
1945 ir3_shader_get_variant(builder
->shaders
[stage
]->ir3_shader
,
1946 &key
, false, &created
);
1947 if (!builder
->variants
[stage
])
1948 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1951 const struct tu_shader
*vs
= builder
->shaders
[MESA_SHADER_VERTEX
];
1952 struct ir3_shader_variant
*variant
;
1954 if (vs
->ir3_shader
->stream_output
.num_outputs
) {
1955 variant
= builder
->variants
[MESA_SHADER_VERTEX
];
1958 variant
= ir3_shader_get_variant(vs
->ir3_shader
, &key
,
1961 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1964 builder
->binning_variant
= variant
;
1966 if (builder
->shaders
[MESA_SHADER_TESS_CTRL
]) {
1967 struct ir3_shader
*hs
=
1968 builder
->shaders
[MESA_SHADER_TESS_CTRL
]->ir3_shader
;
1969 assert(hs
->type
!= MESA_SHADER_NONE
);
1971 /* Calculate and store the per-vertex and per-patch HS-output sizes. */
1972 uint32_t per_vertex_output_size
= 0;
1973 uint32_t per_patch_output_size
= 0;
1974 nir_foreach_variable (output
, &hs
->nir
->outputs
) {
1975 switch (output
->data
.location
) {
1976 case VARYING_SLOT_TESS_LEVEL_OUTER
:
1977 case VARYING_SLOT_TESS_LEVEL_INNER
:
1980 uint32_t size
= glsl_count_attribute_slots(output
->type
, false) * 4;
1981 if (output
->data
.patch
)
1982 per_patch_output_size
+= size
;
1984 per_vertex_output_size
+= size
;
1986 pipeline
->tess
.per_vertex_output_size
= per_vertex_output_size
;
1987 pipeline
->tess
.per_patch_output_size
= per_patch_output_size
;
1994 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder
*builder
,
1995 struct tu_pipeline
*pipeline
)
1997 const VkPipelineDynamicStateCreateInfo
*dynamic_info
=
1998 builder
->create_info
->pDynamicState
;
2003 for (uint32_t i
= 0; i
< dynamic_info
->dynamicStateCount
; i
++) {
2004 VkDynamicState state
= dynamic_info
->pDynamicStates
[i
];
2006 case VK_DYNAMIC_STATE_VIEWPORT
... VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
2007 pipeline
->dynamic_state_mask
|= BIT(state
);
2009 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
2010 pipeline
->dynamic_state_mask
|= BIT(TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
);
2013 assert(!"unsupported dynamic state");
2020 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage
*link
,
2021 struct tu_shader
*shader
,
2022 struct ir3_shader_variant
*v
)
2024 link
->const_state
= *ir3_const_state(v
);
2025 link
->constlen
= v
->constlen
;
2026 link
->push_consts
= shader
->push_consts
;
2030 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder
*builder
,
2031 struct tu_pipeline
*pipeline
)
2033 struct tu_cs prog_cs
;
2034 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2035 tu6_emit_program(&prog_cs
, builder
, false);
2036 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2038 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2039 tu6_emit_program(&prog_cs
, builder
, true);
2040 pipeline
->program
.binning_state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2042 VkShaderStageFlags stages
= 0;
2043 for (unsigned i
= 0; i
< builder
->create_info
->stageCount
; i
++) {
2044 stages
|= builder
->create_info
->pStages
[i
].stage
;
2046 pipeline
->active_stages
= stages
;
2048 uint32_t desc_sets
= 0;
2049 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2050 if (!builder
->shaders
[i
])
2053 tu_pipeline_set_linkage(&pipeline
->program
.link
[i
],
2054 builder
->shaders
[i
],
2055 builder
->variants
[i
]);
2056 desc_sets
|= builder
->shaders
[i
]->active_desc_sets
;
2058 pipeline
->active_desc_sets
= desc_sets
;
2062 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder
*builder
,
2063 struct tu_pipeline
*pipeline
)
2065 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
2066 builder
->create_info
->pVertexInputState
;
2067 const struct ir3_shader_variant
*vs
= builder
->variants
[MESA_SHADER_VERTEX
];
2068 const struct ir3_shader_variant
*bs
= builder
->binning_variant
;
2071 tu_cs_begin_sub_stream(&pipeline
->cs
,
2072 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2073 tu6_emit_vertex_input(&vi_cs
, vs
, vi_info
,
2074 &pipeline
->vi
.bindings_used
);
2075 pipeline
->vi
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2078 tu_cs_begin_sub_stream(&pipeline
->cs
,
2079 MAX_VERTEX_ATTRIBS
* 7 + 2, &vi_cs
);
2080 tu6_emit_vertex_input(
2081 &vi_cs
, bs
, vi_info
, &pipeline
->vi
.bindings_used
);
2082 pipeline
->vi
.binning_state_ib
=
2083 tu_cs_end_sub_stream(&pipeline
->cs
, &vi_cs
);
2088 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder
*builder
,
2089 struct tu_pipeline
*pipeline
)
2091 const VkPipelineInputAssemblyStateCreateInfo
*ia_info
=
2092 builder
->create_info
->pInputAssemblyState
;
2094 pipeline
->ia
.primtype
= tu6_primtype(ia_info
->topology
);
2095 pipeline
->ia
.primitive_restart
= ia_info
->primitiveRestartEnable
;
2099 tu_pipeline_static_state(struct tu_pipeline
*pipeline
, struct tu_cs
*cs
,
2100 uint32_t id
, uint32_t size
)
2102 struct tu_cs_memory memory
;
2104 if (pipeline
->dynamic_state_mask
& BIT(id
))
2107 /* TODO: share this logc with tu_cmd_dynamic_state */
2108 tu_cs_alloc(&pipeline
->cs
, size
, 1, &memory
);
2109 tu_cs_init_external(cs
, memory
.map
, memory
.map
+ size
);
2111 tu_cs_reserve_space(cs
, size
);
2113 assert(id
< ARRAY_SIZE(pipeline
->dynamic_state
));
2114 pipeline
->dynamic_state
[id
].iova
= memory
.iova
;
2115 pipeline
->dynamic_state
[id
].size
= size
;
2120 tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder
*builder
,
2121 struct tu_pipeline
*pipeline
)
2123 const VkPipelineTessellationStateCreateInfo
*tess_info
=
2124 builder
->create_info
->pTessellationState
;
2129 assert(pipeline
->ia
.primtype
== DI_PT_PATCHES0
);
2130 assert(tess_info
->patchControlPoints
<= 32);
2131 pipeline
->ia
.primtype
+= tess_info
->patchControlPoints
;
2132 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_info
=
2133 vk_find_struct_const(tess_info
->pNext
, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2134 pipeline
->tess
.upper_left_domain_origin
= !domain_info
||
2135 domain_info
->domainOrigin
== VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
;
2136 const struct ir3_shader_variant
*hs
= builder
->variants
[MESA_SHADER_TESS_CTRL
];
2137 const struct ir3_shader_variant
*ds
= builder
->variants
[MESA_SHADER_TESS_EVAL
];
2138 pipeline
->tess
.hs_bo_regid
= hs
->const_state
->offsets
.primitive_param
+ 1;
2139 pipeline
->tess
.ds_bo_regid
= ds
->const_state
->offsets
.primitive_param
+ 1;
2143 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder
*builder
,
2144 struct tu_pipeline
*pipeline
)
2148 * pViewportState is a pointer to an instance of the
2149 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2150 * pipeline has rasterization disabled."
2152 * We leave the relevant registers stale in that case.
2154 if (builder
->rasterizer_discard
)
2157 const VkPipelineViewportStateCreateInfo
*vp_info
=
2158 builder
->create_info
->pViewportState
;
2162 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_VIEWPORT
, 18))
2163 tu6_emit_viewport(&cs
, vp_info
->pViewports
);
2165 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_SCISSOR
, 3))
2166 tu6_emit_scissor(&cs
, vp_info
->pScissors
);
2170 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder
*builder
,
2171 struct tu_pipeline
*pipeline
)
2173 const VkPipelineRasterizationStateCreateInfo
*rast_info
=
2174 builder
->create_info
->pRasterizationState
;
2176 assert(rast_info
->polygonMode
== VK_POLYGON_MODE_FILL
);
2179 tu_cs_begin_sub_stream(&pipeline
->cs
, 7, &cs
);
2181 tu_cs_emit_regs(&cs
,
2183 .znear_clip_disable
= rast_info
->depthClampEnable
,
2184 .zfar_clip_disable
= rast_info
->depthClampEnable
,
2185 .unk5
= rast_info
->depthClampEnable
,
2186 .zero_gb_scale_z
= 1,
2187 .vp_clip_code_ignore
= 1));
2188 /* move to hw ctx init? */
2189 tu_cs_emit_regs(&cs
, A6XX_GRAS_UNKNOWN_8001());
2190 tu_cs_emit_regs(&cs
,
2191 A6XX_GRAS_SU_POINT_MINMAX(.min
= 1.0f
/ 16.0f
, .max
= 4092.0f
),
2192 A6XX_GRAS_SU_POINT_SIZE(1.0f
));
2194 pipeline
->rast
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2196 pipeline
->gras_su_cntl
=
2197 tu6_gras_su_cntl(rast_info
, builder
->samples
);
2199 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2)) {
2200 pipeline
->gras_su_cntl
|=
2201 A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(rast_info
->lineWidth
/ 2.0f
);
2202 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= pipeline
->gras_su_cntl
));
2205 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4)) {
2206 tu6_emit_depth_bias(&cs
, rast_info
->depthBiasConstantFactor
,
2207 rast_info
->depthBiasClamp
,
2208 rast_info
->depthBiasSlopeFactor
);
2214 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder
*builder
,
2215 struct tu_pipeline
*pipeline
)
2219 * pDepthStencilState is a pointer to an instance of the
2220 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2221 * the pipeline has rasterization disabled or if the subpass of the
2222 * render pass the pipeline is created against does not use a
2223 * depth/stencil attachment.
2225 * Disable both depth and stencil tests if there is no ds attachment,
2226 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2227 * only the separate stencil attachment
2229 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info
;
2230 const VkPipelineDepthStencilStateCreateInfo
*ds_info
=
2231 builder
->depth_attachment_format
!= VK_FORMAT_UNDEFINED
2232 ? builder
->create_info
->pDepthStencilState
2234 const VkPipelineDepthStencilStateCreateInfo
*ds_info_depth
=
2235 builder
->depth_attachment_format
!= VK_FORMAT_S8_UINT
2236 ? ds_info
: &dummy_ds_info
;
2239 tu_cs_begin_sub_stream(&pipeline
->cs
, 6, &cs
);
2241 /* move to hw ctx init? */
2242 tu_cs_emit_regs(&cs
, A6XX_RB_ALPHA_CONTROL());
2243 tu6_emit_depth_control(&cs
, ds_info_depth
,
2244 builder
->create_info
->pRasterizationState
);
2245 tu6_emit_stencil_control(&cs
, ds_info
);
2247 pipeline
->ds
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2249 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3)) {
2250 tu_cs_emit_regs(&cs
,
2251 A6XX_RB_Z_BOUNDS_MIN(ds_info
->minDepthBounds
),
2252 A6XX_RB_Z_BOUNDS_MAX(ds_info
->maxDepthBounds
));
2255 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2)) {
2256 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.mask
= ds_info
->front
.compareMask
& 0xff,
2257 .bfmask
= ds_info
->back
.compareMask
& 0xff));
2260 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2)) {
2261 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.wrmask
= ds_info
->front
.writeMask
& 0xff,
2262 .bfwrmask
= ds_info
->back
.writeMask
& 0xff));
2265 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2)) {
2266 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.ref
= ds_info
->front
.reference
& 0xff,
2267 .bfref
= ds_info
->back
.reference
& 0xff));
2272 tu_pipeline_builder_parse_multisample_and_color_blend(
2273 struct tu_pipeline_builder
*builder
, struct tu_pipeline
*pipeline
)
2277 * pMultisampleState is a pointer to an instance of the
2278 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2279 * has rasterization disabled.
2283 * pColorBlendState is a pointer to an instance of the
2284 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2285 * pipeline has rasterization disabled or if the subpass of the render
2286 * pass the pipeline is created against does not use any color
2289 * We leave the relevant registers stale when rasterization is disabled.
2291 if (builder
->rasterizer_discard
)
2294 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info
;
2295 const VkPipelineMultisampleStateCreateInfo
*msaa_info
=
2296 builder
->create_info
->pMultisampleState
;
2297 const VkPipelineColorBlendStateCreateInfo
*blend_info
=
2298 builder
->use_color_attachments
? builder
->create_info
->pColorBlendState
2299 : &dummy_blend_info
;
2302 tu_cs_begin_sub_stream(&pipeline
->cs
, MAX_RTS
* 3 + 4, &cs
);
2304 uint32_t blend_enable_mask
;
2305 tu6_emit_rb_mrt_controls(&cs
, blend_info
,
2306 builder
->color_attachment_formats
,
2307 &blend_enable_mask
);
2309 tu6_emit_blend_control(&cs
, blend_enable_mask
,
2310 builder
->use_dual_src_blend
, msaa_info
);
2312 pipeline
->blend
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &cs
);
2314 if (tu_pipeline_static_state(pipeline
, &cs
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5)) {
2315 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2316 tu_cs_emit_array(&cs
, (const uint32_t *) blend_info
->blendConstants
, 4);
2319 const struct VkPipelineSampleLocationsStateCreateInfoEXT
*sample_locations
=
2320 vk_find_struct_const(msaa_info
->pNext
, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
2321 const VkSampleLocationsInfoEXT
*samp_loc
= NULL
;
2323 if (sample_locations
&& sample_locations
->sampleLocationsEnable
)
2324 samp_loc
= &sample_locations
->sampleLocationsInfo
;
2326 if (tu_pipeline_static_state(pipeline
, &cs
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
,
2327 samp_loc
? 9 : 6)) {
2328 tu6_emit_sample_locations(&cs
, samp_loc
);
2333 tu_pipeline_finish(struct tu_pipeline
*pipeline
,
2334 struct tu_device
*dev
,
2335 const VkAllocationCallbacks
*alloc
)
2337 tu_cs_finish(&pipeline
->cs
);
2341 tu_pipeline_builder_build(struct tu_pipeline_builder
*builder
,
2342 struct tu_pipeline
**pipeline
)
2347 vk_zalloc2(&builder
->device
->alloc
, builder
->alloc
, sizeof(**pipeline
),
2348 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2350 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2352 (*pipeline
)->layout
= builder
->layout
;
2354 /* compile and upload shaders */
2355 result
= tu_pipeline_builder_compile_shaders(builder
, *pipeline
);
2356 if (result
!= VK_SUCCESS
) {
2357 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2361 result
= tu_pipeline_allocate_cs(builder
->device
, *pipeline
, builder
, NULL
);
2362 if (result
!= VK_SUCCESS
) {
2363 vk_free2(&builder
->device
->alloc
, builder
->alloc
, *pipeline
);
2367 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
2368 builder
->shader_iova
[i
] = tu_upload_variant(*pipeline
, builder
->variants
[i
]);
2370 builder
->binning_vs_iova
=
2371 tu_upload_variant(*pipeline
, builder
->binning_variant
);
2373 tu_pipeline_builder_parse_dynamic(builder
, *pipeline
);
2374 tu_pipeline_builder_parse_shader_stages(builder
, *pipeline
);
2375 tu_pipeline_builder_parse_vertex_input(builder
, *pipeline
);
2376 tu_pipeline_builder_parse_input_assembly(builder
, *pipeline
);
2377 tu_pipeline_builder_parse_tessellation(builder
, *pipeline
);
2378 tu_pipeline_builder_parse_viewport(builder
, *pipeline
);
2379 tu_pipeline_builder_parse_rasterization(builder
, *pipeline
);
2380 tu_pipeline_builder_parse_depth_stencil(builder
, *pipeline
);
2381 tu_pipeline_builder_parse_multisample_and_color_blend(builder
, *pipeline
);
2382 tu6_emit_load_state(*pipeline
, false);
2384 /* we should have reserved enough space upfront such that the CS never
2387 assert((*pipeline
)->cs
.bo_count
== 1);
2393 tu_pipeline_builder_finish(struct tu_pipeline_builder
*builder
)
2395 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2396 if (!builder
->shaders
[i
])
2398 tu_shader_destroy(builder
->device
, builder
->shaders
[i
], builder
->alloc
);
2403 tu_pipeline_builder_init_graphics(
2404 struct tu_pipeline_builder
*builder
,
2405 struct tu_device
*dev
,
2406 struct tu_pipeline_cache
*cache
,
2407 const VkGraphicsPipelineCreateInfo
*create_info
,
2408 const VkAllocationCallbacks
*alloc
)
2410 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, create_info
->layout
);
2412 *builder
= (struct tu_pipeline_builder
) {
2415 .create_info
= create_info
,
2420 builder
->rasterizer_discard
=
2421 create_info
->pRasterizationState
->rasterizerDiscardEnable
;
2423 if (builder
->rasterizer_discard
) {
2424 builder
->samples
= VK_SAMPLE_COUNT_1_BIT
;
2426 builder
->samples
= create_info
->pMultisampleState
->rasterizationSamples
;
2428 const struct tu_render_pass
*pass
=
2429 tu_render_pass_from_handle(create_info
->renderPass
);
2430 const struct tu_subpass
*subpass
=
2431 &pass
->subpasses
[create_info
->subpass
];
2433 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
2434 builder
->depth_attachment_format
= (a
!= VK_ATTACHMENT_UNUSED
) ?
2435 pass
->attachments
[a
].format
: VK_FORMAT_UNDEFINED
;
2437 assert(subpass
->color_count
== 0 ||
2438 !create_info
->pColorBlendState
||
2439 subpass
->color_count
== create_info
->pColorBlendState
->attachmentCount
);
2440 builder
->color_attachment_count
= subpass
->color_count
;
2441 for (uint32_t i
= 0; i
< subpass
->color_count
; i
++) {
2442 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
2443 if (a
== VK_ATTACHMENT_UNUSED
)
2446 builder
->color_attachment_formats
[i
] = pass
->attachments
[a
].format
;
2447 builder
->use_color_attachments
= true;
2448 builder
->render_components
|= 0xf << (i
* 4);
2451 if (tu_blend_state_is_dual_src(create_info
->pColorBlendState
)) {
2452 builder
->color_attachment_count
++;
2453 builder
->use_dual_src_blend
= true;
2454 /* dual source blending has an extra fs output in the 2nd slot */
2455 if (subpass
->color_attachments
[0].attachment
!= VK_ATTACHMENT_UNUSED
)
2456 builder
->render_components
|= 0xf << 4;
2462 tu_graphics_pipeline_create(VkDevice device
,
2463 VkPipelineCache pipelineCache
,
2464 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2465 const VkAllocationCallbacks
*pAllocator
,
2466 VkPipeline
*pPipeline
)
2468 TU_FROM_HANDLE(tu_device
, dev
, device
);
2469 TU_FROM_HANDLE(tu_pipeline_cache
, cache
, pipelineCache
);
2471 struct tu_pipeline_builder builder
;
2472 tu_pipeline_builder_init_graphics(&builder
, dev
, cache
,
2473 pCreateInfo
, pAllocator
);
2475 struct tu_pipeline
*pipeline
= NULL
;
2476 VkResult result
= tu_pipeline_builder_build(&builder
, &pipeline
);
2477 tu_pipeline_builder_finish(&builder
);
2479 if (result
== VK_SUCCESS
)
2480 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2482 *pPipeline
= VK_NULL_HANDLE
;
2488 tu_CreateGraphicsPipelines(VkDevice device
,
2489 VkPipelineCache pipelineCache
,
2491 const VkGraphicsPipelineCreateInfo
*pCreateInfos
,
2492 const VkAllocationCallbacks
*pAllocator
,
2493 VkPipeline
*pPipelines
)
2495 VkResult final_result
= VK_SUCCESS
;
2497 for (uint32_t i
= 0; i
< count
; i
++) {
2498 VkResult result
= tu_graphics_pipeline_create(device
, pipelineCache
,
2499 &pCreateInfos
[i
], pAllocator
,
2502 if (result
!= VK_SUCCESS
)
2503 final_result
= result
;
2506 return final_result
;
2510 tu_compute_pipeline_create(VkDevice device
,
2511 VkPipelineCache _cache
,
2512 const VkComputePipelineCreateInfo
*pCreateInfo
,
2513 const VkAllocationCallbacks
*pAllocator
,
2514 VkPipeline
*pPipeline
)
2516 TU_FROM_HANDLE(tu_device
, dev
, device
);
2517 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, pCreateInfo
->layout
);
2518 const VkPipelineShaderStageCreateInfo
*stage_info
= &pCreateInfo
->stage
;
2521 struct tu_pipeline
*pipeline
;
2523 *pPipeline
= VK_NULL_HANDLE
;
2526 vk_zalloc2(&dev
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
2527 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2529 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2531 pipeline
->layout
= layout
;
2533 struct ir3_shader_key key
= {};
2535 struct tu_shader
*shader
=
2536 tu_shader_create(dev
, MESA_SHADER_COMPUTE
, stage_info
, layout
, pAllocator
);
2538 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2543 struct ir3_shader_variant
*v
=
2544 ir3_shader_get_variant(shader
->ir3_shader
, &key
, false, &created
);
2546 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2550 tu_pipeline_set_linkage(&pipeline
->program
.link
[MESA_SHADER_COMPUTE
],
2553 result
= tu_pipeline_allocate_cs(dev
, pipeline
, NULL
, v
);
2554 if (result
!= VK_SUCCESS
)
2557 uint64_t shader_iova
= tu_upload_variant(pipeline
, v
);
2559 for (int i
= 0; i
< 3; i
++)
2560 pipeline
->compute
.local_size
[i
] = v
->shader
->nir
->info
.cs
.local_size
[i
];
2562 struct tu_cs prog_cs
;
2563 tu_cs_begin_sub_stream(&pipeline
->cs
, 512, &prog_cs
);
2564 tu6_emit_cs_config(&prog_cs
, shader
, v
, shader_iova
);
2565 pipeline
->program
.state_ib
= tu_cs_end_sub_stream(&pipeline
->cs
, &prog_cs
);
2567 tu6_emit_load_state(pipeline
, true);
2569 *pPipeline
= tu_pipeline_to_handle(pipeline
);
2574 tu_shader_destroy(dev
, shader
, pAllocator
);
2576 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);
2582 tu_CreateComputePipelines(VkDevice device
,
2583 VkPipelineCache pipelineCache
,
2585 const VkComputePipelineCreateInfo
*pCreateInfos
,
2586 const VkAllocationCallbacks
*pAllocator
,
2587 VkPipeline
*pPipelines
)
2589 VkResult final_result
= VK_SUCCESS
;
2591 for (uint32_t i
= 0; i
< count
; i
++) {
2592 VkResult result
= tu_compute_pipeline_create(device
, pipelineCache
,
2594 pAllocator
, &pPipelines
[i
]);
2595 if (result
!= VK_SUCCESS
)
2596 final_result
= result
;
2599 return final_result
;
2603 tu_DestroyPipeline(VkDevice _device
,
2604 VkPipeline _pipeline
,
2605 const VkAllocationCallbacks
*pAllocator
)
2607 TU_FROM_HANDLE(tu_device
, dev
, _device
);
2608 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2613 tu_pipeline_finish(pipeline
, dev
, pAllocator
);
2614 vk_free2(&dev
->alloc
, pAllocator
, pipeline
);