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turnip/pipeline: Don't assume tu_shader is a valid object
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "main/menums.h"
31 #include "nir/nir.h"
32 #include "nir/nir_builder.h"
33 #include "spirv/nir_spirv.h"
34 #include "util/debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/u_atomic.h"
37 #include "vk_format.h"
38 #include "vk_util.h"
39
40 #include "tu_cs.h"
41
42 struct tu_pipeline_builder
43 {
44 struct tu_device *device;
45 struct tu_pipeline_cache *cache;
46 struct tu_pipeline_layout *layout;
47 const VkAllocationCallbacks *alloc;
48 const VkGraphicsPipelineCreateInfo *create_info;
49
50 struct tu_shader *shaders[MESA_SHADER_STAGES];
51 uint32_t shader_offsets[MESA_SHADER_STAGES];
52 uint32_t binning_vs_offset;
53 uint32_t shader_total_size;
54
55 bool rasterizer_discard;
56 /* these states are affectd by rasterizer_discard */
57 VkSampleCountFlagBits samples;
58 bool use_depth_stencil_attachment;
59 bool use_color_attachments;
60 uint32_t color_attachment_count;
61 VkFormat color_attachment_formats[MAX_RTS];
62 };
63
64 static enum tu_dynamic_state_bits
65 tu_dynamic_state_bit(VkDynamicState state)
66 {
67 switch (state) {
68 case VK_DYNAMIC_STATE_VIEWPORT:
69 return TU_DYNAMIC_VIEWPORT;
70 case VK_DYNAMIC_STATE_SCISSOR:
71 return TU_DYNAMIC_SCISSOR;
72 case VK_DYNAMIC_STATE_LINE_WIDTH:
73 return TU_DYNAMIC_LINE_WIDTH;
74 case VK_DYNAMIC_STATE_DEPTH_BIAS:
75 return TU_DYNAMIC_DEPTH_BIAS;
76 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
77 return TU_DYNAMIC_BLEND_CONSTANTS;
78 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
79 return TU_DYNAMIC_DEPTH_BOUNDS;
80 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
81 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
82 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
83 return TU_DYNAMIC_STENCIL_WRITE_MASK;
84 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
85 return TU_DYNAMIC_STENCIL_REFERENCE;
86 default:
87 unreachable("invalid dynamic state");
88 return 0;
89 }
90 }
91
92 static gl_shader_stage
93 tu_shader_stage(VkShaderStageFlagBits stage)
94 {
95 switch (stage) {
96 case VK_SHADER_STAGE_VERTEX_BIT:
97 return MESA_SHADER_VERTEX;
98 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
99 return MESA_SHADER_TESS_CTRL;
100 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
101 return MESA_SHADER_TESS_EVAL;
102 case VK_SHADER_STAGE_GEOMETRY_BIT:
103 return MESA_SHADER_GEOMETRY;
104 case VK_SHADER_STAGE_FRAGMENT_BIT:
105 return MESA_SHADER_FRAGMENT;
106 case VK_SHADER_STAGE_COMPUTE_BIT:
107 return MESA_SHADER_COMPUTE;
108 default:
109 unreachable("invalid VkShaderStageFlagBits");
110 return MESA_SHADER_NONE;
111 }
112 }
113
114 static const VkVertexInputAttributeDescription *
115 tu_find_vertex_input_attribute(
116 const VkPipelineVertexInputStateCreateInfo *vi_info, uint32_t slot)
117 {
118 assert(slot >= VERT_ATTRIB_GENERIC0);
119 slot -= VERT_ATTRIB_GENERIC0;
120 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
121 if (vi_info->pVertexAttributeDescriptions[i].location == slot)
122 return &vi_info->pVertexAttributeDescriptions[i];
123 }
124 return NULL;
125 }
126
127 static const VkVertexInputBindingDescription *
128 tu_find_vertex_input_binding(
129 const VkPipelineVertexInputStateCreateInfo *vi_info,
130 const VkVertexInputAttributeDescription *vi_attr)
131 {
132 assert(vi_attr);
133 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
134 if (vi_info->pVertexBindingDescriptions[i].binding == vi_attr->binding)
135 return &vi_info->pVertexBindingDescriptions[i];
136 }
137 return NULL;
138 }
139
140 static bool
141 tu_logic_op_reads_dst(VkLogicOp op)
142 {
143 switch (op) {
144 case VK_LOGIC_OP_CLEAR:
145 case VK_LOGIC_OP_COPY:
146 case VK_LOGIC_OP_COPY_INVERTED:
147 case VK_LOGIC_OP_SET:
148 return false;
149 default:
150 return true;
151 }
152 }
153
154 static VkBlendFactor
155 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
156 {
157 /* treat dst alpha as 1.0 and avoid reading it */
158 switch (factor) {
159 case VK_BLEND_FACTOR_DST_ALPHA:
160 return VK_BLEND_FACTOR_ONE;
161 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
162 return VK_BLEND_FACTOR_ZERO;
163 default:
164 return factor;
165 }
166 }
167
168 static enum pc_di_primtype
169 tu6_primtype(VkPrimitiveTopology topology)
170 {
171 switch (topology) {
172 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
173 return DI_PT_POINTLIST;
174 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
175 return DI_PT_LINELIST;
176 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
177 return DI_PT_LINESTRIP;
178 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
179 return DI_PT_TRILIST;
180 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
181 return DI_PT_TRISTRIP;
182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
183 return DI_PT_TRIFAN;
184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
185 return DI_PT_LINE_ADJ;
186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
187 return DI_PT_LINESTRIP_ADJ;
188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
189 return DI_PT_TRI_ADJ;
190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
191 return DI_PT_TRISTRIP_ADJ;
192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
193 default:
194 unreachable("invalid primitive topology");
195 return DI_PT_NONE;
196 }
197 }
198
199 static enum adreno_compare_func
200 tu6_compare_func(VkCompareOp op)
201 {
202 switch (op) {
203 case VK_COMPARE_OP_NEVER:
204 return FUNC_NEVER;
205 case VK_COMPARE_OP_LESS:
206 return FUNC_LESS;
207 case VK_COMPARE_OP_EQUAL:
208 return FUNC_EQUAL;
209 case VK_COMPARE_OP_LESS_OR_EQUAL:
210 return FUNC_LEQUAL;
211 case VK_COMPARE_OP_GREATER:
212 return FUNC_GREATER;
213 case VK_COMPARE_OP_NOT_EQUAL:
214 return FUNC_NOTEQUAL;
215 case VK_COMPARE_OP_GREATER_OR_EQUAL:
216 return FUNC_GEQUAL;
217 case VK_COMPARE_OP_ALWAYS:
218 return FUNC_ALWAYS;
219 default:
220 unreachable("invalid VkCompareOp");
221 return FUNC_NEVER;
222 }
223 }
224
225 static enum adreno_stencil_op
226 tu6_stencil_op(VkStencilOp op)
227 {
228 switch (op) {
229 case VK_STENCIL_OP_KEEP:
230 return STENCIL_KEEP;
231 case VK_STENCIL_OP_ZERO:
232 return STENCIL_ZERO;
233 case VK_STENCIL_OP_REPLACE:
234 return STENCIL_REPLACE;
235 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
236 return STENCIL_INCR_CLAMP;
237 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
238 return STENCIL_DECR_CLAMP;
239 case VK_STENCIL_OP_INVERT:
240 return STENCIL_INVERT;
241 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
242 return STENCIL_INCR_WRAP;
243 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
244 return STENCIL_DECR_WRAP;
245 default:
246 unreachable("invalid VkStencilOp");
247 return STENCIL_KEEP;
248 }
249 }
250
251 static enum a3xx_rop_code
252 tu6_rop(VkLogicOp op)
253 {
254 switch (op) {
255 case VK_LOGIC_OP_CLEAR:
256 return ROP_CLEAR;
257 case VK_LOGIC_OP_AND:
258 return ROP_AND;
259 case VK_LOGIC_OP_AND_REVERSE:
260 return ROP_AND_REVERSE;
261 case VK_LOGIC_OP_COPY:
262 return ROP_COPY;
263 case VK_LOGIC_OP_AND_INVERTED:
264 return ROP_AND_INVERTED;
265 case VK_LOGIC_OP_NO_OP:
266 return ROP_NOOP;
267 case VK_LOGIC_OP_XOR:
268 return ROP_XOR;
269 case VK_LOGIC_OP_OR:
270 return ROP_OR;
271 case VK_LOGIC_OP_NOR:
272 return ROP_NOR;
273 case VK_LOGIC_OP_EQUIVALENT:
274 return ROP_EQUIV;
275 case VK_LOGIC_OP_INVERT:
276 return ROP_INVERT;
277 case VK_LOGIC_OP_OR_REVERSE:
278 return ROP_OR_REVERSE;
279 case VK_LOGIC_OP_COPY_INVERTED:
280 return ROP_COPY_INVERTED;
281 case VK_LOGIC_OP_OR_INVERTED:
282 return ROP_OR_INVERTED;
283 case VK_LOGIC_OP_NAND:
284 return ROP_NAND;
285 case VK_LOGIC_OP_SET:
286 return ROP_SET;
287 default:
288 unreachable("invalid VkLogicOp");
289 return ROP_NOOP;
290 }
291 }
292
293 static enum adreno_rb_blend_factor
294 tu6_blend_factor(VkBlendFactor factor)
295 {
296 switch (factor) {
297 case VK_BLEND_FACTOR_ZERO:
298 return FACTOR_ZERO;
299 case VK_BLEND_FACTOR_ONE:
300 return FACTOR_ONE;
301 case VK_BLEND_FACTOR_SRC_COLOR:
302 return FACTOR_SRC_COLOR;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
304 return FACTOR_ONE_MINUS_SRC_COLOR;
305 case VK_BLEND_FACTOR_DST_COLOR:
306 return FACTOR_DST_COLOR;
307 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
308 return FACTOR_ONE_MINUS_DST_COLOR;
309 case VK_BLEND_FACTOR_SRC_ALPHA:
310 return FACTOR_SRC_ALPHA;
311 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
312 return FACTOR_ONE_MINUS_SRC_ALPHA;
313 case VK_BLEND_FACTOR_DST_ALPHA:
314 return FACTOR_DST_ALPHA;
315 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
316 return FACTOR_ONE_MINUS_DST_ALPHA;
317 case VK_BLEND_FACTOR_CONSTANT_COLOR:
318 return FACTOR_CONSTANT_COLOR;
319 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
320 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
321 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
322 return FACTOR_CONSTANT_ALPHA;
323 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
324 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
325 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
326 return FACTOR_SRC_ALPHA_SATURATE;
327 case VK_BLEND_FACTOR_SRC1_COLOR:
328 return FACTOR_SRC1_COLOR;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
330 return FACTOR_ONE_MINUS_SRC1_COLOR;
331 case VK_BLEND_FACTOR_SRC1_ALPHA:
332 return FACTOR_SRC1_ALPHA;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
334 return FACTOR_ONE_MINUS_SRC1_ALPHA;
335 default:
336 unreachable("invalid VkBlendFactor");
337 return FACTOR_ZERO;
338 }
339 }
340
341 static enum a3xx_rb_blend_opcode
342 tu6_blend_op(VkBlendOp op)
343 {
344 switch (op) {
345 case VK_BLEND_OP_ADD:
346 return BLEND_DST_PLUS_SRC;
347 case VK_BLEND_OP_SUBTRACT:
348 return BLEND_SRC_MINUS_DST;
349 case VK_BLEND_OP_REVERSE_SUBTRACT:
350 return BLEND_DST_MINUS_SRC;
351 case VK_BLEND_OP_MIN:
352 return BLEND_MIN_DST_SRC;
353 case VK_BLEND_OP_MAX:
354 return BLEND_MAX_DST_SRC;
355 default:
356 unreachable("invalid VkBlendOp");
357 return BLEND_DST_PLUS_SRC;
358 }
359 }
360
361 static unsigned
362 tu_shader_nibo(const struct tu_shader *shader)
363 {
364 /* Don't use ir3_shader_nibo(), because that would include declared but
365 * unused storage images and SSBOs.
366 */
367 return shader->ssbo_map.num_desc + shader->image_map.num_desc;
368 }
369
370 static void
371 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
372 const struct ir3_shader_variant *vs)
373 {
374 uint32_t sp_vs_ctrl =
375 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
376 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
377 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
378 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
379 if (vs->need_pixlod)
380 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
381 if (vs->need_fine_derivatives)
382 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
383
384 uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(shader->texture_map.num_desc) |
385 A6XX_SP_VS_CONFIG_NSAMP(shader->sampler_map.num_desc);
386 if (vs->instrlen)
387 sp_vs_config |= A6XX_SP_VS_CONFIG_ENABLED;
388
389 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
390 tu_cs_emit(cs, sp_vs_ctrl);
391
392 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
393 tu_cs_emit(cs, sp_vs_config);
394 tu_cs_emit(cs, vs->instrlen);
395
396 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
397 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
398 A6XX_HLSQ_VS_CNTL_ENABLED);
399 }
400
401 static void
402 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
403 const struct ir3_shader_variant *hs)
404 {
405 uint32_t sp_hs_config = 0;
406 if (hs->instrlen)
407 sp_hs_config |= A6XX_SP_HS_CONFIG_ENABLED;
408
409 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
410 tu_cs_emit(cs, 0);
411
412 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
413 tu_cs_emit(cs, sp_hs_config);
414 tu_cs_emit(cs, hs->instrlen);
415
416 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
417 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
418 }
419
420 static void
421 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
422 const struct ir3_shader_variant *ds)
423 {
424 uint32_t sp_ds_config = 0;
425 if (ds->instrlen)
426 sp_ds_config |= A6XX_SP_DS_CONFIG_ENABLED;
427
428 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
429 tu_cs_emit(cs, sp_ds_config);
430 tu_cs_emit(cs, ds->instrlen);
431
432 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
433 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
434 }
435
436 static void
437 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
438 const struct ir3_shader_variant *gs)
439 {
440 uint32_t sp_gs_config = 0;
441 if (gs->instrlen)
442 sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED;
443
444 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
445 tu_cs_emit(cs, 0);
446
447 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
448 tu_cs_emit(cs, sp_gs_config);
449 tu_cs_emit(cs, gs->instrlen);
450
451 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
452 tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
453 }
454
455 static void
456 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
457 const struct ir3_shader_variant *fs)
458 {
459 uint32_t sp_fs_ctrl =
460 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
461 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
462 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
463 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
464 if (fs->total_in > 0)
465 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
466 if (fs->need_pixlod)
467 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
468 if (fs->need_fine_derivatives)
469 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
470
471 uint32_t sp_fs_config = 0;
472 unsigned shader_nibo = 0;
473 if (shader) {
474 shader_nibo = tu_shader_nibo(shader);
475 sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(shader->texture_map.num_desc) |
476 A6XX_SP_FS_CONFIG_NSAMP(shader->sampler_map.num_desc) |
477 A6XX_SP_FS_CONFIG_NIBO(shader_nibo);
478 }
479
480 if (fs->instrlen)
481 sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
482
483 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
484 tu_cs_emit(cs, 0);
485
486 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_AB00, 1);
487 tu_cs_emit(cs, 0x5);
488
489 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
490 tu_cs_emit(cs, sp_fs_ctrl);
491
492 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
493 tu_cs_emit(cs, sp_fs_config);
494 tu_cs_emit(cs, fs->instrlen);
495
496 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
497 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
498 A6XX_HLSQ_FS_CNTL_ENABLED);
499
500 tu_cs_emit_pkt4(cs, REG_A6XX_SP_IBO_COUNT, 1);
501 tu_cs_emit(cs, shader_nibo);
502 }
503
504 static void
505 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
506 const struct ir3_shader_variant *v)
507 {
508 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
509 tu_cs_emit(cs, 0xff);
510
511 unsigned constlen = align(v->constlen, 4);
512 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
513 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
514 A6XX_HLSQ_CS_CNTL_ENABLED);
515
516 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
517 tu_cs_emit(cs, A6XX_SP_CS_CONFIG_ENABLED |
518 A6XX_SP_CS_CONFIG_NIBO(tu_shader_nibo(shader)) |
519 A6XX_SP_CS_CONFIG_NTEX(shader->texture_map.num_desc) |
520 A6XX_SP_CS_CONFIG_NSAMP(shader->sampler_map.num_desc));
521 tu_cs_emit(cs, v->instrlen);
522
523 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
524 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
525 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
526 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
527 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
528 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
529 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
530
531 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
532 tu_cs_emit(cs, 0x41);
533
534 uint32_t local_invocation_id =
535 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
536 uint32_t work_group_id =
537 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
538
539 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
540 tu_cs_emit(cs,
541 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
542 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
543 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
544 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
545 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
546
547 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_IBO_COUNT, 1);
548 tu_cs_emit(cs, tu_shader_nibo(shader));
549 }
550
551 static void
552 tu6_emit_vs_system_values(struct tu_cs *cs,
553 const struct ir3_shader_variant *vs)
554 {
555 const uint32_t vertexid_regid =
556 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
557 const uint32_t instanceid_regid =
558 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
559
560 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
561 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
562 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
563 0xfcfc0000);
564 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
565 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
566 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
567 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_5 */
568 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
569 }
570
571 static void
572 tu6_emit_vpc(struct tu_cs *cs,
573 const struct ir3_shader_variant *vs,
574 const struct ir3_shader_variant *fs,
575 bool binning_pass)
576 {
577 struct ir3_shader_linkage linkage = { 0 };
578 ir3_link_shaders(&linkage, vs, fs);
579
580 if (vs->shader->stream_output.num_outputs && !binning_pass)
581 tu_finishme("stream output");
582
583 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
584 for (uint32_t i = 0; i < linkage.cnt; i++) {
585 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
586 for (uint32_t j = 0; j < comp_count; j++)
587 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
588 }
589
590 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
591 tu_cs_emit(cs, ~vpc_var_enables[0]);
592 tu_cs_emit(cs, ~vpc_var_enables[1]);
593 tu_cs_emit(cs, ~vpc_var_enables[2]);
594 tu_cs_emit(cs, ~vpc_var_enables[3]);
595
596 /* a6xx finds position/pointsize at the end */
597 const uint32_t position_regid =
598 ir3_find_output_regid(vs, VARYING_SLOT_POS);
599 const uint32_t pointsize_regid =
600 ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
601 uint32_t pointsize_loc = 0xff, position_loc = 0xff;
602 if (position_regid != regid(63, 0)) {
603 position_loc = linkage.max_loc;
604 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
605 }
606 if (pointsize_regid != regid(63, 0)) {
607 pointsize_loc = linkage.max_loc;
608 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
609 }
610
611 /* map vs outputs to VPC */
612 assert(linkage.cnt <= 32);
613 const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
614 const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
615 uint32_t sp_vs_out[16];
616 uint32_t sp_vs_vpc_dst[8];
617 sp_vs_out[sp_vs_out_count - 1] = 0;
618 sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
619 for (uint32_t i = 0; i < linkage.cnt; i++) {
620 ((uint16_t *) sp_vs_out)[i] =
621 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
622 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
623 ((uint8_t *) sp_vs_vpc_dst)[i] =
624 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
625 }
626
627 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
628 tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
629
630 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
631 tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
632
633 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
634 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
635 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
636 0xff00ff00);
637
638 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
639 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
640 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
641 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
642
643 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_SIV_CNTL, 1);
644 tu_cs_emit(cs, 0x0000ffff); /* XXX */
645
646 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
647 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
648
649 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
650 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
651 (vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
652 }
653
654 static int
655 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
656 uint32_t index,
657 uint8_t *interp_mode,
658 uint8_t *ps_repl_mode)
659 {
660 enum
661 {
662 INTERP_SMOOTH = 0,
663 INTERP_FLAT = 1,
664 INTERP_ZERO = 2,
665 INTERP_ONE = 3,
666 };
667 enum
668 {
669 PS_REPL_NONE = 0,
670 PS_REPL_S = 1,
671 PS_REPL_T = 2,
672 PS_REPL_ONE_MINUS_T = 3,
673 };
674
675 const uint32_t compmask = fs->inputs[index].compmask;
676
677 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
678 * fourth component occupy three consecutive varying slots
679 */
680 int shift = 0;
681 *interp_mode = 0;
682 *ps_repl_mode = 0;
683 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
684 if (compmask & 0x1) {
685 *ps_repl_mode |= PS_REPL_S << shift;
686 shift += 2;
687 }
688 if (compmask & 0x2) {
689 *ps_repl_mode |= PS_REPL_T << shift;
690 shift += 2;
691 }
692 if (compmask & 0x4) {
693 *interp_mode |= INTERP_ZERO << shift;
694 shift += 2;
695 }
696 if (compmask & 0x8) {
697 *interp_mode |= INTERP_ONE << 6;
698 shift += 2;
699 }
700 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
701 fs->inputs[index].rasterflat) {
702 for (int i = 0; i < 4; i++) {
703 if (compmask & (1 << i)) {
704 *interp_mode |= INTERP_FLAT << shift;
705 shift += 2;
706 }
707 }
708 }
709
710 return shift;
711 }
712
713 static void
714 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
715 const struct ir3_shader_variant *fs,
716 bool binning_pass)
717 {
718 uint32_t interp_modes[8] = { 0 };
719 uint32_t ps_repl_modes[8] = { 0 };
720
721 if (!binning_pass) {
722 for (int i = -1;
723 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
724
725 /* get the mode for input i */
726 uint8_t interp_mode;
727 uint8_t ps_repl_mode;
728 const int bits =
729 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
730
731 /* OR the mode into the array */
732 const uint32_t inloc = fs->inputs[i].inloc * 2;
733 uint32_t n = inloc / 32;
734 uint32_t shift = inloc % 32;
735 interp_modes[n] |= interp_mode << shift;
736 ps_repl_modes[n] |= ps_repl_mode << shift;
737 if (shift + bits > 32) {
738 n++;
739 shift = 32 - shift;
740
741 interp_modes[n] |= interp_mode >> shift;
742 ps_repl_modes[n] |= ps_repl_mode >> shift;
743 }
744 }
745 }
746
747 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
748 tu_cs_emit_array(cs, interp_modes, 8);
749
750 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
751 tu_cs_emit_array(cs, ps_repl_modes, 8);
752 }
753
754 static void
755 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
756 {
757 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
758 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
759 uint32_t smask_in_regid;
760
761 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
762 bool enable_varyings = fs->total_in > 0;
763
764 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
765 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
766 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
767 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
768 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
769 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
770 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
771 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
772 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
773
774 if (fs->num_sampler_prefetch > 0) {
775 assert(VALIDREG(ij_pix_regid));
776 /* also, it seems like ij_pix is *required* to be r0.x */
777 assert(ij_pix_regid == regid(0, 0));
778 }
779
780 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
781 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
782 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
783 0x7000); // XXX);
784 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
785 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
786 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
787 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
788 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
789 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
790 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
791 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
792 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
793 }
794
795 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
796 tu_cs_emit(cs, 0x7);
797 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
798 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
799 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
800 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
801 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
802 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
803 0xfc00fc00);
804 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
805 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
806 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
807 0x0000fc00);
808 tu_cs_emit(cs, 0xfc);
809
810 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
811 tu_cs_emit(cs, enable_varyings ? 3 : 1);
812
813 tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
814 tu_cs_emit(cs, 0); /* XXX */
815
816 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
817 tu_cs_emit(cs, 0xff); /* XXX */
818
819 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
820 tu_cs_emit(cs,
821 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
822 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
823 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
824 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
825 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
826 COND(fs->frag_coord,
827 A6XX_GRAS_CNTL_SIZE |
828 A6XX_GRAS_CNTL_XCOORD |
829 A6XX_GRAS_CNTL_YCOORD |
830 A6XX_GRAS_CNTL_ZCOORD |
831 A6XX_GRAS_CNTL_WCOORD) |
832 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
833
834 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
835 tu_cs_emit(cs,
836 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
837 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
838 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
839 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
840 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
841 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
842 COND(fs->frag_coord,
843 A6XX_RB_RENDER_CONTROL0_SIZE |
844 A6XX_RB_RENDER_CONTROL0_XCOORD |
845 A6XX_RB_RENDER_CONTROL0_YCOORD |
846 A6XX_RB_RENDER_CONTROL0_ZCOORD |
847 A6XX_RB_RENDER_CONTROL0_WCOORD) |
848 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
849 tu_cs_emit(cs,
850 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
851 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
852 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
853 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
854 }
855
856 static void
857 tu6_emit_fs_outputs(struct tu_cs *cs,
858 const struct ir3_shader_variant *fs,
859 uint32_t mrt_count)
860 {
861 uint32_t smask_regid, posz_regid;
862
863 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
864 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
865
866 uint32_t fragdata_regid[8];
867 if (fs->color0_mrt) {
868 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
869 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
870 fragdata_regid[i] = fragdata_regid[0];
871 } else {
872 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
873 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
874 }
875
876 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
877 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
878 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
879 0xfc000000);
880 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
881
882 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
883 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
884 // TODO we could have a mix of half and full precision outputs,
885 // we really need to figure out half-precision from IR3_REG_HALF
886 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
887 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
888 }
889
890 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
891 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
892 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
893 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
894
895 uint32_t gras_su_depth_plane_cntl = 0;
896 uint32_t rb_depth_plane_cntl = 0;
897 if (fs->no_earlyz || fs->writes_pos) {
898 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
899 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
900 }
901
902 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
903 tu_cs_emit(cs, gras_su_depth_plane_cntl);
904
905 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
906 tu_cs_emit(cs, rb_depth_plane_cntl);
907 }
908
909 static void
910 tu6_emit_shader_object(struct tu_cs *cs,
911 gl_shader_stage stage,
912 const struct ir3_shader_variant *variant,
913 const struct tu_bo *binary_bo,
914 uint32_t binary_offset)
915 {
916 uint16_t reg;
917 uint8_t opcode;
918 enum a6xx_state_block sb;
919 switch (stage) {
920 case MESA_SHADER_VERTEX:
921 reg = REG_A6XX_SP_VS_OBJ_START_LO;
922 opcode = CP_LOAD_STATE6_GEOM;
923 sb = SB6_VS_SHADER;
924 break;
925 case MESA_SHADER_TESS_CTRL:
926 reg = REG_A6XX_SP_HS_OBJ_START_LO;
927 opcode = CP_LOAD_STATE6_GEOM;
928 sb = SB6_HS_SHADER;
929 break;
930 case MESA_SHADER_TESS_EVAL:
931 reg = REG_A6XX_SP_DS_OBJ_START_LO;
932 opcode = CP_LOAD_STATE6_GEOM;
933 sb = SB6_DS_SHADER;
934 break;
935 case MESA_SHADER_GEOMETRY:
936 reg = REG_A6XX_SP_GS_OBJ_START_LO;
937 opcode = CP_LOAD_STATE6_GEOM;
938 sb = SB6_GS_SHADER;
939 break;
940 case MESA_SHADER_FRAGMENT:
941 reg = REG_A6XX_SP_FS_OBJ_START_LO;
942 opcode = CP_LOAD_STATE6_FRAG;
943 sb = SB6_FS_SHADER;
944 break;
945 case MESA_SHADER_COMPUTE:
946 reg = REG_A6XX_SP_CS_OBJ_START_LO;
947 opcode = CP_LOAD_STATE6_FRAG;
948 sb = SB6_CS_SHADER;
949 break;
950 default:
951 unreachable("invalid gl_shader_stage");
952 opcode = CP_LOAD_STATE6_GEOM;
953 sb = SB6_VS_SHADER;
954 break;
955 }
956
957 if (!variant->instrlen) {
958 tu_cs_emit_pkt4(cs, reg, 2);
959 tu_cs_emit_qw(cs, 0);
960 return;
961 }
962
963 assert(variant->type == stage);
964
965 const uint64_t binary_iova = binary_bo->iova + binary_offset;
966 assert((binary_iova & 0x3) == 0);
967
968 tu_cs_emit_pkt4(cs, reg, 2);
969 tu_cs_emit_qw(cs, binary_iova);
970
971 /* always indirect */
972 const bool indirect = true;
973 if (indirect) {
974 tu_cs_emit_pkt7(cs, opcode, 3);
975 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
976 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
977 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
978 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
979 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
980 tu_cs_emit_qw(cs, binary_iova);
981 } else {
982 const void *binary = binary_bo->map + binary_offset;
983
984 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
985 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
986 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
987 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
988 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
989 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
990 tu_cs_emit_qw(cs, 0);
991 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
992 }
993 }
994
995 static void
996 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
997 uint32_t opcode, enum a6xx_state_block block)
998 {
999 /* dummy variant */
1000 if (!v->shader)
1001 return;
1002
1003 const struct ir3_const_state *const_state = &v->shader->const_state;
1004 uint32_t base = const_state->offsets.immediate;
1005 int size = const_state->immediates_count;
1006
1007 /* truncate size to avoid writing constants that shader
1008 * does not use:
1009 */
1010 size = MIN2(size + base, v->constlen) - base;
1011
1012 if (size <= 0)
1013 return;
1014
1015 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1016 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1017 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1018 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1019 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1020 CP_LOAD_STATE6_0_NUM_UNIT(size));
1021 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1022 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1023
1024 for (unsigned i = 0; i < size; i++) {
1025 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1026 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1027 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1028 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1029 }
1030 }
1031
1032 static void
1033 tu6_emit_program(struct tu_cs *cs,
1034 const struct tu_pipeline_builder *builder,
1035 const struct tu_bo *binary_bo,
1036 bool binning_pass)
1037 {
1038 static const struct ir3_shader_variant dummy_variant = {
1039 .type = MESA_SHADER_NONE
1040 };
1041 assert(builder->shaders[MESA_SHADER_VERTEX]);
1042 const struct ir3_shader_variant *vs =
1043 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1044 const struct ir3_shader_variant *hs =
1045 builder->shaders[MESA_SHADER_TESS_CTRL]
1046 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1047 : &dummy_variant;
1048 const struct ir3_shader_variant *ds =
1049 builder->shaders[MESA_SHADER_TESS_EVAL]
1050 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1051 : &dummy_variant;
1052 const struct ir3_shader_variant *gs =
1053 builder->shaders[MESA_SHADER_GEOMETRY]
1054 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1055 : &dummy_variant;
1056 const struct ir3_shader_variant *fs =
1057 builder->shaders[MESA_SHADER_FRAGMENT]
1058 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1059 : &dummy_variant;
1060
1061 if (binning_pass) {
1062 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1063 fs = &dummy_variant;
1064 }
1065
1066 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1067 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1068 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1069 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1070 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1071
1072 tu6_emit_vs_system_values(cs, vs);
1073 tu6_emit_vpc(cs, vs, fs, binning_pass);
1074 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1075 tu6_emit_fs_inputs(cs, fs);
1076 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1077
1078 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1079 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1080
1081 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1082 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1083
1084 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1085 if (!binning_pass)
1086 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1087 }
1088
1089 static void
1090 tu6_emit_vertex_input(struct tu_cs *cs,
1091 const struct ir3_shader_variant *vs,
1092 const VkPipelineVertexInputStateCreateInfo *vi_info,
1093 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1094 uint16_t strides[MAX_VERTEX_ATTRIBS],
1095 uint16_t offsets[MAX_VERTEX_ATTRIBS],
1096 uint32_t *count)
1097 {
1098 uint32_t vfd_decode_idx = 0;
1099
1100 for (uint32_t i = 0; i < vs->inputs_count; i++) {
1101 if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
1102 continue;
1103
1104 const VkVertexInputAttributeDescription *vi_attr =
1105 tu_find_vertex_input_attribute(vi_info, vs->inputs[i].slot);
1106 const VkVertexInputBindingDescription *vi_binding =
1107 tu_find_vertex_input_binding(vi_info, vi_attr);
1108 assert(vi_attr && vi_binding);
1109
1110 const struct tu_native_format *format =
1111 tu6_get_native_format(vi_attr->format);
1112 assert(format && format->vtx >= 0);
1113
1114 uint32_t vfd_decode = A6XX_VFD_DECODE_INSTR_IDX(vfd_decode_idx) |
1115 A6XX_VFD_DECODE_INSTR_FORMAT(format->vtx) |
1116 A6XX_VFD_DECODE_INSTR_SWAP(format->swap) |
1117 A6XX_VFD_DECODE_INSTR_UNK30;
1118 if (vi_binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1119 vfd_decode |= A6XX_VFD_DECODE_INSTR_INSTANCED;
1120 if (!vk_format_is_int(vi_attr->format))
1121 vfd_decode |= A6XX_VFD_DECODE_INSTR_FLOAT;
1122
1123 const uint32_t vfd_decode_step_rate = 1;
1124
1125 const uint32_t vfd_dest_cntl =
1126 A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
1127 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid);
1128
1129 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE(vfd_decode_idx), 2);
1130 tu_cs_emit(cs, vfd_decode);
1131 tu_cs_emit(cs, vfd_decode_step_rate);
1132
1133 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DEST_CNTL(vfd_decode_idx), 1);
1134 tu_cs_emit(cs, vfd_dest_cntl);
1135
1136 bindings[vfd_decode_idx] = vi_binding->binding;
1137 strides[vfd_decode_idx] = vi_binding->stride;
1138 offsets[vfd_decode_idx] = vi_attr->offset;
1139
1140 vfd_decode_idx++;
1141 assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
1142 }
1143
1144 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
1145 tu_cs_emit(
1146 cs, A6XX_VFD_CONTROL_0_VTXCNT(vfd_decode_idx) | (vfd_decode_idx << 8));
1147
1148 *count = vfd_decode_idx;
1149 }
1150
1151 static uint32_t
1152 tu6_guardband_adj(uint32_t v)
1153 {
1154 if (v > 256)
1155 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1156 else
1157 return 511;
1158 }
1159
1160 void
1161 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1162 {
1163 float offsets[3];
1164 float scales[3];
1165 scales[0] = viewport->width / 2.0f;
1166 scales[1] = viewport->height / 2.0f;
1167 scales[2] = viewport->maxDepth - viewport->minDepth;
1168 offsets[0] = viewport->x + scales[0];
1169 offsets[1] = viewport->y + scales[1];
1170 offsets[2] = viewport->minDepth;
1171
1172 VkOffset2D min;
1173 VkOffset2D max;
1174 min.x = (int32_t) viewport->x;
1175 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1176 if (viewport->height >= 0.0f) {
1177 min.y = (int32_t) viewport->y;
1178 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1179 } else {
1180 min.y = (int32_t)(viewport->y + viewport->height);
1181 max.y = (int32_t) ceilf(viewport->y);
1182 }
1183 /* the spec allows viewport->height to be 0.0f */
1184 if (min.y == max.y)
1185 max.y++;
1186 assert(min.x >= 0 && min.x < max.x);
1187 assert(min.y >= 0 && min.y < max.y);
1188
1189 VkExtent2D guardband_adj;
1190 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1191 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1192
1193 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1194 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1195 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1196 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1197 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1198 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1199 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1200
1201 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1202 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1203 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1204 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1205 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1206
1207 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1208 tu_cs_emit(cs,
1209 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1210 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1211 }
1212
1213 void
1214 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1215 {
1216 const VkOffset2D min = scissor->offset;
1217 const VkOffset2D max = {
1218 scissor->offset.x + scissor->extent.width,
1219 scissor->offset.y + scissor->extent.height,
1220 };
1221
1222 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1223 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1224 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1225 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1226 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1227 }
1228
1229 static void
1230 tu6_emit_gras_unknowns(struct tu_cs *cs)
1231 {
1232 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_DISABLE_CNTL, 1);
1233 tu_cs_emit(cs, A6XX_GRAS_DISABLE_CNTL_VP_CLIP_CODE_IGNORE);
1234 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1235 tu_cs_emit(cs, 0x0);
1236 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
1237 tu_cs_emit(cs, 0x0);
1238 }
1239
1240 static void
1241 tu6_emit_point_size(struct tu_cs *cs)
1242 {
1243 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1244 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1245 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1246 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1247 }
1248
1249 static uint32_t
1250 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1251 VkSampleCountFlagBits samples)
1252 {
1253 uint32_t gras_su_cntl = 0;
1254
1255 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1256 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1257 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1258 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1259
1260 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1261 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1262
1263 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1264
1265 if (rast_info->depthBiasEnable)
1266 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1267
1268 if (samples > VK_SAMPLE_COUNT_1_BIT)
1269 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1270
1271 return gras_su_cntl;
1272 }
1273
1274 void
1275 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1276 uint32_t gras_su_cntl,
1277 float line_width)
1278 {
1279 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1280 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1281
1282 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1283 tu_cs_emit(cs, gras_su_cntl);
1284 }
1285
1286 void
1287 tu6_emit_depth_bias(struct tu_cs *cs,
1288 float constant_factor,
1289 float clamp,
1290 float slope_factor)
1291 {
1292 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1293 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1294 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1295 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1296 }
1297
1298 static void
1299 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1300 {
1301 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1302 tu_cs_emit(cs, 0);
1303 }
1304
1305 static void
1306 tu6_emit_depth_control(struct tu_cs *cs,
1307 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1308 {
1309 assert(!ds_info->depthBoundsTestEnable);
1310
1311 uint32_t rb_depth_cntl = 0;
1312 if (ds_info->depthTestEnable) {
1313 rb_depth_cntl |=
1314 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1315 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1316 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1317
1318 if (ds_info->depthWriteEnable)
1319 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1320 }
1321
1322 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1323 tu_cs_emit(cs, rb_depth_cntl);
1324 }
1325
1326 static void
1327 tu6_emit_stencil_control(struct tu_cs *cs,
1328 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1329 {
1330 uint32_t rb_stencil_control = 0;
1331 if (ds_info->stencilTestEnable) {
1332 const VkStencilOpState *front = &ds_info->front;
1333 const VkStencilOpState *back = &ds_info->back;
1334 rb_stencil_control |=
1335 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1336 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1337 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1338 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1339 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1340 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1341 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1342 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1343 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1344 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1345 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1346 }
1347
1348 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1349 tu_cs_emit(cs, rb_stencil_control);
1350 }
1351
1352 void
1353 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1354 {
1355 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1356 tu_cs_emit(
1357 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1358 }
1359
1360 void
1361 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1362 {
1363 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1364 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1365 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1366 }
1367
1368 void
1369 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1370 {
1371 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1372 tu_cs_emit(cs,
1373 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1374 }
1375
1376 static uint32_t
1377 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1378 bool has_alpha)
1379 {
1380 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1381 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1382 has_alpha ? att->srcColorBlendFactor
1383 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1384 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1385 has_alpha ? att->dstColorBlendFactor
1386 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1387 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1388 const enum adreno_rb_blend_factor src_alpha_factor =
1389 tu6_blend_factor(att->srcAlphaBlendFactor);
1390 const enum adreno_rb_blend_factor dst_alpha_factor =
1391 tu6_blend_factor(att->dstAlphaBlendFactor);
1392
1393 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1394 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1395 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1396 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1397 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1398 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1399 }
1400
1401 static uint32_t
1402 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1403 uint32_t rb_mrt_control_rop,
1404 bool is_int,
1405 bool has_alpha)
1406 {
1407 uint32_t rb_mrt_control =
1408 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1409
1410 /* ignore blending and logic op for integer attachments */
1411 if (is_int) {
1412 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1413 return rb_mrt_control;
1414 }
1415
1416 rb_mrt_control |= rb_mrt_control_rop;
1417
1418 if (att->blendEnable) {
1419 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1420
1421 if (has_alpha)
1422 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1423 }
1424
1425 return rb_mrt_control;
1426 }
1427
1428 static void
1429 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1430 const VkPipelineColorBlendStateCreateInfo *blend_info,
1431 const VkFormat attachment_formats[MAX_RTS],
1432 uint32_t *blend_enable_mask)
1433 {
1434 *blend_enable_mask = 0;
1435
1436 bool rop_reads_dst = false;
1437 uint32_t rb_mrt_control_rop = 0;
1438 if (blend_info->logicOpEnable) {
1439 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1440 rb_mrt_control_rop =
1441 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1442 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1443 }
1444
1445 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1446 const VkPipelineColorBlendAttachmentState *att =
1447 &blend_info->pAttachments[i];
1448 const VkFormat format = attachment_formats[i];
1449
1450 uint32_t rb_mrt_control = 0;
1451 uint32_t rb_mrt_blend_control = 0;
1452 if (format != VK_FORMAT_UNDEFINED) {
1453 const bool is_int = vk_format_is_int(format);
1454 const bool has_alpha = vk_format_has_alpha(format);
1455
1456 rb_mrt_control =
1457 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
1458 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
1459
1460 if (att->blendEnable || rop_reads_dst)
1461 *blend_enable_mask |= 1 << i;
1462 }
1463
1464 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1465 tu_cs_emit(cs, rb_mrt_control);
1466 tu_cs_emit(cs, rb_mrt_blend_control);
1467 }
1468
1469 for (uint32_t i = blend_info->attachmentCount; i < MAX_RTS; i++) {
1470 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
1471 tu_cs_emit(cs, 0);
1472 tu_cs_emit(cs, 0);
1473 }
1474 }
1475
1476 static void
1477 tu6_emit_blend_control(struct tu_cs *cs,
1478 uint32_t blend_enable_mask,
1479 const VkPipelineMultisampleStateCreateInfo *msaa_info)
1480 {
1481 assert(!msaa_info->sampleShadingEnable);
1482 assert(!msaa_info->alphaToOneEnable);
1483
1484 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
1485 if (blend_enable_mask)
1486 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
1487 if (msaa_info->alphaToCoverageEnable)
1488 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
1489
1490 const uint32_t sample_mask =
1491 msaa_info->pSampleMask ? *msaa_info->pSampleMask
1492 : ((1 << msaa_info->rasterizationSamples) - 1);
1493
1494 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
1495 uint32_t rb_blend_cntl =
1496 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
1497 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
1498 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
1499 if (msaa_info->alphaToCoverageEnable)
1500 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
1501
1502 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
1503 tu_cs_emit(cs, sp_blend_cntl);
1504
1505 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
1506 tu_cs_emit(cs, rb_blend_cntl);
1507 }
1508
1509 void
1510 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
1511 {
1512 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
1513 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
1514 }
1515
1516 static VkResult
1517 tu_pipeline_create(struct tu_device *dev,
1518 const VkAllocationCallbacks *pAllocator,
1519 struct tu_pipeline **out_pipeline)
1520 {
1521 struct tu_pipeline *pipeline =
1522 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
1523 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1524 if (!pipeline)
1525 return VK_ERROR_OUT_OF_HOST_MEMORY;
1526
1527 tu_cs_init(&pipeline->cs, TU_CS_MODE_SUB_STREAM, 2048);
1528
1529 /* reserve the space now such that tu_cs_begin_sub_stream never fails */
1530 VkResult result = tu_cs_reserve_space(dev, &pipeline->cs, 2048);
1531 if (result != VK_SUCCESS) {
1532 vk_free2(&dev->alloc, pAllocator, pipeline);
1533 return result;
1534 }
1535
1536 *out_pipeline = pipeline;
1537
1538 return VK_SUCCESS;
1539 }
1540
1541 static VkResult
1542 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
1543 {
1544 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
1545 NULL
1546 };
1547 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
1548 gl_shader_stage stage =
1549 tu_shader_stage(builder->create_info->pStages[i].stage);
1550 stage_infos[stage] = &builder->create_info->pStages[i];
1551 }
1552
1553 struct tu_shader_compile_options options;
1554 tu_shader_compile_options_init(&options, builder->create_info);
1555
1556 /* compile shaders in reverse order */
1557 struct tu_shader *next_stage_shader = NULL;
1558 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
1559 stage > MESA_SHADER_NONE; stage--) {
1560 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
1561 if (!stage_info)
1562 continue;
1563
1564 struct tu_shader *shader =
1565 tu_shader_create(builder->device, stage, stage_info, builder->layout,
1566 builder->alloc);
1567 if (!shader)
1568 return VK_ERROR_OUT_OF_HOST_MEMORY;
1569
1570 VkResult result =
1571 tu_shader_compile(builder->device, shader, next_stage_shader,
1572 &options, builder->alloc);
1573 if (result != VK_SUCCESS)
1574 return result;
1575
1576 builder->shaders[stage] = shader;
1577 builder->shader_offsets[stage] = builder->shader_total_size;
1578 builder->shader_total_size +=
1579 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
1580
1581 next_stage_shader = shader;
1582 }
1583
1584 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1585 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1586 builder->binning_vs_offset = builder->shader_total_size;
1587 builder->shader_total_size +=
1588 sizeof(uint32_t) * vs->variants[1].info.sizedwords;
1589 }
1590
1591 return VK_SUCCESS;
1592 }
1593
1594 static VkResult
1595 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
1596 struct tu_pipeline *pipeline)
1597 {
1598 struct tu_bo *bo = &pipeline->program.binary_bo;
1599
1600 VkResult result =
1601 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
1602 if (result != VK_SUCCESS)
1603 return result;
1604
1605 result = tu_bo_map(builder->device, bo);
1606 if (result != VK_SUCCESS)
1607 return result;
1608
1609 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1610 const struct tu_shader *shader = builder->shaders[i];
1611 if (!shader)
1612 continue;
1613
1614 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
1615 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
1616 }
1617
1618 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
1619 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1620 memcpy(bo->map + builder->binning_vs_offset, vs->binning_binary,
1621 sizeof(uint32_t) * vs->variants[1].info.sizedwords);
1622 }
1623
1624 return VK_SUCCESS;
1625 }
1626
1627 static void
1628 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
1629 struct tu_pipeline *pipeline)
1630 {
1631 const VkPipelineDynamicStateCreateInfo *dynamic_info =
1632 builder->create_info->pDynamicState;
1633
1634 if (!dynamic_info)
1635 return;
1636
1637 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
1638 pipeline->dynamic_state.mask |=
1639 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
1640 }
1641 }
1642
1643 static void
1644 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
1645 struct tu_shader *shader,
1646 struct ir3_shader_variant *v)
1647 {
1648 link->ubo_state = v->shader->ubo_state;
1649 link->const_state = v->shader->const_state;
1650 link->constlen = v->constlen;
1651 link->texture_map = shader->texture_map;
1652 link->sampler_map = shader->sampler_map;
1653 link->ubo_map = shader->ubo_map;
1654 link->ssbo_map = shader->ssbo_map;
1655 link->image_map = shader->image_map;
1656 }
1657
1658 static void
1659 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
1660 struct tu_pipeline *pipeline)
1661 {
1662 struct tu_cs prog_cs;
1663 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1664 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false);
1665 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1666
1667 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 512, &prog_cs);
1668 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
1669 pipeline->program.binning_state_ib =
1670 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
1671
1672 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
1673 if (!builder->shaders[i])
1674 continue;
1675
1676 tu_pipeline_set_linkage(&pipeline->program.link[i],
1677 builder->shaders[i],
1678 &builder->shaders[i]->variants[0]);
1679 }
1680 }
1681
1682 static void
1683 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
1684 struct tu_pipeline *pipeline)
1685 {
1686 const VkPipelineVertexInputStateCreateInfo *vi_info =
1687 builder->create_info->pVertexInputState;
1688 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
1689
1690 struct tu_cs vi_cs;
1691 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1692 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1693 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
1694 pipeline->vi.bindings, pipeline->vi.strides,
1695 pipeline->vi.offsets, &pipeline->vi.count);
1696 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1697
1698 if (vs->has_binning_pass) {
1699 tu_cs_begin_sub_stream(builder->device, &pipeline->cs,
1700 MAX_VERTEX_ATTRIBS * 5 + 2, &vi_cs);
1701 tu6_emit_vertex_input(
1702 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
1703 pipeline->vi.binning_strides, pipeline->vi.binning_offsets,
1704 &pipeline->vi.binning_count);
1705 pipeline->vi.binning_state_ib =
1706 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
1707 }
1708 }
1709
1710 static void
1711 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
1712 struct tu_pipeline *pipeline)
1713 {
1714 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
1715 builder->create_info->pInputAssemblyState;
1716
1717 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
1718 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
1719 }
1720
1721 static void
1722 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
1723 struct tu_pipeline *pipeline)
1724 {
1725 /* The spec says:
1726 *
1727 * pViewportState is a pointer to an instance of the
1728 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
1729 * pipeline has rasterization disabled."
1730 *
1731 * We leave the relevant registers stale in that case.
1732 */
1733 if (builder->rasterizer_discard)
1734 return;
1735
1736 const VkPipelineViewportStateCreateInfo *vp_info =
1737 builder->create_info->pViewportState;
1738
1739 struct tu_cs vp_cs;
1740 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 15, &vp_cs);
1741
1742 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
1743 assert(vp_info->viewportCount == 1);
1744 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
1745 }
1746
1747 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
1748 assert(vp_info->scissorCount == 1);
1749 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
1750 }
1751
1752 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
1753 }
1754
1755 static void
1756 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
1757 struct tu_pipeline *pipeline)
1758 {
1759 const VkPipelineRasterizationStateCreateInfo *rast_info =
1760 builder->create_info->pRasterizationState;
1761
1762 assert(!rast_info->depthClampEnable);
1763 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
1764
1765 struct tu_cs rast_cs;
1766 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 20, &rast_cs);
1767
1768 /* move to hw ctx init? */
1769 tu6_emit_gras_unknowns(&rast_cs);
1770 tu6_emit_point_size(&rast_cs);
1771
1772 const uint32_t gras_su_cntl =
1773 tu6_gras_su_cntl(rast_info, builder->samples);
1774
1775 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
1776 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
1777
1778 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
1779 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
1780 rast_info->depthBiasClamp,
1781 rast_info->depthBiasSlopeFactor);
1782 }
1783
1784 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
1785
1786 pipeline->rast.gras_su_cntl = gras_su_cntl;
1787 }
1788
1789 static void
1790 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
1791 struct tu_pipeline *pipeline)
1792 {
1793 /* The spec says:
1794 *
1795 * pDepthStencilState is a pointer to an instance of the
1796 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
1797 * the pipeline has rasterization disabled or if the subpass of the
1798 * render pass the pipeline is created against does not use a
1799 * depth/stencil attachment.
1800 *
1801 * We disable both depth and stenil tests in those cases.
1802 */
1803 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
1804 const VkPipelineDepthStencilStateCreateInfo *ds_info =
1805 builder->use_depth_stencil_attachment
1806 ? builder->create_info->pDepthStencilState
1807 : &dummy_ds_info;
1808
1809 struct tu_cs ds_cs;
1810 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, 12, &ds_cs);
1811
1812 /* move to hw ctx init? */
1813 tu6_emit_alpha_control_disable(&ds_cs);
1814
1815 tu6_emit_depth_control(&ds_cs, ds_info);
1816 tu6_emit_stencil_control(&ds_cs, ds_info);
1817
1818 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
1819 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
1820 ds_info->back.compareMask);
1821 }
1822 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
1823 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
1824 ds_info->back.writeMask);
1825 }
1826 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
1827 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
1828 ds_info->back.reference);
1829 }
1830
1831 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
1832 }
1833
1834 static void
1835 tu_pipeline_builder_parse_multisample_and_color_blend(
1836 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
1837 {
1838 /* The spec says:
1839 *
1840 * pMultisampleState is a pointer to an instance of the
1841 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
1842 * has rasterization disabled.
1843 *
1844 * Also,
1845 *
1846 * pColorBlendState is a pointer to an instance of the
1847 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
1848 * pipeline has rasterization disabled or if the subpass of the render
1849 * pass the pipeline is created against does not use any color
1850 * attachments.
1851 *
1852 * We leave the relevant registers stale when rasterization is disabled.
1853 */
1854 if (builder->rasterizer_discard)
1855 return;
1856
1857 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
1858 const VkPipelineMultisampleStateCreateInfo *msaa_info =
1859 builder->create_info->pMultisampleState;
1860 const VkPipelineColorBlendStateCreateInfo *blend_info =
1861 builder->use_color_attachments ? builder->create_info->pColorBlendState
1862 : &dummy_blend_info;
1863
1864 struct tu_cs blend_cs;
1865 tu_cs_begin_sub_stream(builder->device, &pipeline->cs, MAX_RTS * 3 + 9,
1866 &blend_cs);
1867
1868 uint32_t blend_enable_mask;
1869 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
1870 builder->color_attachment_formats,
1871 &blend_enable_mask);
1872
1873 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
1874 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
1875
1876 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
1877
1878 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
1879 }
1880
1881 static void
1882 tu_pipeline_finish(struct tu_pipeline *pipeline,
1883 struct tu_device *dev,
1884 const VkAllocationCallbacks *alloc)
1885 {
1886 tu_cs_finish(dev, &pipeline->cs);
1887
1888 if (pipeline->program.binary_bo.gem_handle)
1889 tu_bo_finish(dev, &pipeline->program.binary_bo);
1890 }
1891
1892 static VkResult
1893 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
1894 struct tu_pipeline **pipeline)
1895 {
1896 VkResult result = tu_pipeline_create(builder->device, builder->alloc,
1897 pipeline);
1898 if (result != VK_SUCCESS)
1899 return result;
1900
1901 /* compile and upload shaders */
1902 result = tu_pipeline_builder_compile_shaders(builder);
1903 if (result == VK_SUCCESS)
1904 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
1905 if (result != VK_SUCCESS) {
1906 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
1907 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
1908 *pipeline = VK_NULL_HANDLE;
1909
1910 return result;
1911 }
1912
1913 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
1914 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
1915 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
1916 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
1917 tu_pipeline_builder_parse_viewport(builder, *pipeline);
1918 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
1919 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
1920 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
1921
1922 /* we should have reserved enough space upfront such that the CS never
1923 * grows
1924 */
1925 assert((*pipeline)->cs.bo_count == 1);
1926
1927 return VK_SUCCESS;
1928 }
1929
1930 static void
1931 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
1932 {
1933 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
1934 if (!builder->shaders[i])
1935 continue;
1936 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
1937 }
1938 }
1939
1940 static void
1941 tu_pipeline_builder_init_graphics(
1942 struct tu_pipeline_builder *builder,
1943 struct tu_device *dev,
1944 struct tu_pipeline_cache *cache,
1945 const VkGraphicsPipelineCreateInfo *create_info,
1946 const VkAllocationCallbacks *alloc)
1947 {
1948 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
1949
1950 *builder = (struct tu_pipeline_builder) {
1951 .device = dev,
1952 .cache = cache,
1953 .create_info = create_info,
1954 .alloc = alloc,
1955 .layout = layout,
1956 };
1957
1958 builder->rasterizer_discard =
1959 create_info->pRasterizationState->rasterizerDiscardEnable;
1960
1961 if (builder->rasterizer_discard) {
1962 builder->samples = VK_SAMPLE_COUNT_1_BIT;
1963 } else {
1964 builder->samples = create_info->pMultisampleState->rasterizationSamples;
1965
1966 const struct tu_render_pass *pass =
1967 tu_render_pass_from_handle(create_info->renderPass);
1968 const struct tu_subpass *subpass =
1969 &pass->subpasses[create_info->subpass];
1970
1971 builder->use_depth_stencil_attachment =
1972 subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
1973
1974 assert(subpass->color_count == 0 ||
1975 !create_info->pColorBlendState ||
1976 subpass->color_count == create_info->pColorBlendState->attachmentCount);
1977 builder->color_attachment_count = subpass->color_count;
1978 for (uint32_t i = 0; i < subpass->color_count; i++) {
1979 const uint32_t a = subpass->color_attachments[i].attachment;
1980 if (a == VK_ATTACHMENT_UNUSED)
1981 continue;
1982
1983 builder->color_attachment_formats[i] = pass->attachments[a].format;
1984 builder->use_color_attachments = true;
1985 }
1986 }
1987 }
1988
1989 static VkResult
1990 tu_graphics_pipeline_create(VkDevice device,
1991 VkPipelineCache pipelineCache,
1992 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1993 const VkAllocationCallbacks *pAllocator,
1994 VkPipeline *pPipeline)
1995 {
1996 TU_FROM_HANDLE(tu_device, dev, device);
1997 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
1998
1999 struct tu_pipeline_builder builder;
2000 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2001 pCreateInfo, pAllocator);
2002
2003 struct tu_pipeline *pipeline = NULL;
2004 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2005 tu_pipeline_builder_finish(&builder);
2006
2007 if (result == VK_SUCCESS)
2008 *pPipeline = tu_pipeline_to_handle(pipeline);
2009 else
2010 *pPipeline = VK_NULL_HANDLE;
2011
2012 return result;
2013 }
2014
2015 VkResult
2016 tu_CreateGraphicsPipelines(VkDevice device,
2017 VkPipelineCache pipelineCache,
2018 uint32_t count,
2019 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2020 const VkAllocationCallbacks *pAllocator,
2021 VkPipeline *pPipelines)
2022 {
2023 VkResult final_result = VK_SUCCESS;
2024
2025 for (uint32_t i = 0; i < count; i++) {
2026 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2027 &pCreateInfos[i], pAllocator,
2028 &pPipelines[i]);
2029
2030 if (result != VK_SUCCESS)
2031 final_result = result;
2032 }
2033
2034 return final_result;
2035 }
2036
2037 static void
2038 tu6_emit_compute_program(struct tu_cs *cs,
2039 struct tu_shader *shader,
2040 const struct tu_bo *binary_bo)
2041 {
2042 const struct ir3_shader_variant *v = &shader->variants[0];
2043
2044 tu6_emit_cs_config(cs, shader, v);
2045
2046 /* The compute program is the only one in the pipeline, so 0 offset. */
2047 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2048
2049 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2050 }
2051
2052 static VkResult
2053 tu_compute_upload_shader(VkDevice device,
2054 struct tu_pipeline *pipeline,
2055 struct tu_shader *shader)
2056 {
2057 TU_FROM_HANDLE(tu_device, dev, device);
2058 struct tu_bo *bo = &pipeline->program.binary_bo;
2059 struct ir3_shader_variant *v = &shader->variants[0];
2060
2061 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2062 VkResult result =
2063 tu_bo_init_new(dev, bo, shader_size);
2064 if (result != VK_SUCCESS)
2065 return result;
2066
2067 result = tu_bo_map(dev, bo);
2068 if (result != VK_SUCCESS)
2069 return result;
2070
2071 memcpy(bo->map, shader->binary, shader_size);
2072
2073 return VK_SUCCESS;
2074 }
2075
2076
2077 static VkResult
2078 tu_compute_pipeline_create(VkDevice device,
2079 VkPipelineCache _cache,
2080 const VkComputePipelineCreateInfo *pCreateInfo,
2081 const VkAllocationCallbacks *pAllocator,
2082 VkPipeline *pPipeline)
2083 {
2084 TU_FROM_HANDLE(tu_device, dev, device);
2085 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2086 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2087 VkResult result;
2088
2089 struct tu_pipeline *pipeline;
2090
2091 *pPipeline = VK_NULL_HANDLE;
2092
2093 result = tu_pipeline_create(dev, pAllocator, &pipeline);
2094 if (result != VK_SUCCESS)
2095 return result;
2096
2097 pipeline->layout = layout;
2098
2099 struct tu_shader_compile_options options;
2100 tu_shader_compile_options_init(&options, NULL);
2101
2102 struct tu_shader *shader =
2103 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2104 if (!shader) {
2105 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2106 goto fail;
2107 }
2108
2109 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2110 if (result != VK_SUCCESS)
2111 goto fail;
2112
2113 struct ir3_shader_variant *v = &shader->variants[0];
2114
2115 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2116 shader, v);
2117
2118 result = tu_compute_upload_shader(device, pipeline, shader);
2119 if (result != VK_SUCCESS)
2120 goto fail;
2121
2122 for (int i = 0; i < 3; i++)
2123 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2124
2125 struct tu_cs prog_cs;
2126 tu_cs_begin_sub_stream(dev, &pipeline->cs, 512, &prog_cs);
2127 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2128 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2129
2130 *pPipeline = tu_pipeline_to_handle(pipeline);
2131 return VK_SUCCESS;
2132
2133 fail:
2134 if (shader)
2135 tu_shader_destroy(dev, shader, pAllocator);
2136
2137 tu_pipeline_finish(pipeline, dev, pAllocator);
2138 vk_free2(&dev->alloc, pAllocator, pipeline);
2139
2140 return result;
2141 }
2142
2143 VkResult
2144 tu_CreateComputePipelines(VkDevice device,
2145 VkPipelineCache pipelineCache,
2146 uint32_t count,
2147 const VkComputePipelineCreateInfo *pCreateInfos,
2148 const VkAllocationCallbacks *pAllocator,
2149 VkPipeline *pPipelines)
2150 {
2151 VkResult final_result = VK_SUCCESS;
2152
2153 for (uint32_t i = 0; i < count; i++) {
2154 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2155 &pCreateInfos[i],
2156 pAllocator, &pPipelines[i]);
2157 if (result != VK_SUCCESS)
2158 final_result = result;
2159 }
2160
2161 return final_result;
2162 }
2163
2164 void
2165 tu_DestroyPipeline(VkDevice _device,
2166 VkPipeline _pipeline,
2167 const VkAllocationCallbacks *pAllocator)
2168 {
2169 TU_FROM_HANDLE(tu_device, dev, _device);
2170 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2171
2172 if (!_pipeline)
2173 return;
2174
2175 tu_pipeline_finish(pipeline, dev, pAllocator);
2176 vk_free2(&dev->alloc, pAllocator, pipeline);
2177 }