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turnip: implement VK_EXT_sample_locations
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
27
28 #include "tu_private.h"
29
30 #include "ir3/ir3_nir.h"
31 #include "main/menums.h"
32 #include "nir/nir.h"
33 #include "nir/nir_builder.h"
34 #include "spirv/nir_spirv.h"
35 #include "util/debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/u_atomic.h"
38 #include "vk_format.h"
39 #include "vk_util.h"
40
41 #include "tu_cs.h"
42
43 /* Emit IB that preloads the descriptors that the shader uses */
44
45 static inline uint32_t
46 tu6_vkstage2opcode(VkShaderStageFlags stage)
47 {
48 switch (stage) {
49 case VK_SHADER_STAGE_VERTEX_BIT:
50 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
51 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
52 case VK_SHADER_STAGE_GEOMETRY_BIT:
53 return CP_LOAD_STATE6_GEOM;
54 case VK_SHADER_STAGE_FRAGMENT_BIT:
55 case VK_SHADER_STAGE_COMPUTE_BIT:
56 return CP_LOAD_STATE6_FRAG;
57 default:
58 unreachable("bad shader type");
59 }
60 }
61
62 static enum a6xx_state_block
63 tu6_tex_stage2sb(VkShaderStageFlags stage)
64 {
65 switch (stage) {
66 case VK_SHADER_STAGE_VERTEX_BIT:
67 return SB6_VS_TEX;
68 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
69 return SB6_HS_TEX;
70 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
71 return SB6_DS_TEX;
72 case VK_SHADER_STAGE_GEOMETRY_BIT:
73 return SB6_GS_TEX;
74 case VK_SHADER_STAGE_FRAGMENT_BIT:
75 return SB6_FS_TEX;
76 case VK_SHADER_STAGE_COMPUTE_BIT:
77 return SB6_CS_TEX;
78 default:
79 unreachable("bad shader stage");
80 }
81 }
82
83 static enum a6xx_state_block
84 tu6_ubo_stage2sb(VkShaderStageFlags stage)
85 {
86 switch (stage) {
87 case VK_SHADER_STAGE_VERTEX_BIT:
88 return SB6_VS_SHADER;
89 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
90 return SB6_HS_SHADER;
91 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
92 return SB6_DS_SHADER;
93 case VK_SHADER_STAGE_GEOMETRY_BIT:
94 return SB6_GS_SHADER;
95 case VK_SHADER_STAGE_FRAGMENT_BIT:
96 return SB6_FS_SHADER;
97 case VK_SHADER_STAGE_COMPUTE_BIT:
98 return SB6_CS_SHADER;
99 default:
100 unreachable("bad shader stage");
101 }
102 }
103
104 static void
105 emit_load_state(struct tu_cs *cs, unsigned opcode, enum a6xx_state_type st,
106 enum a6xx_state_block sb, unsigned base, unsigned offset,
107 unsigned count)
108 {
109 /* Note: just emit one packet, even if count overflows NUM_UNIT. It's not
110 * clear if emitting more packets will even help anything. Presumably the
111 * descriptor cache is relatively small, and these packets stop doing
112 * anything when there are too many descriptors.
113 */
114 tu_cs_emit_pkt7(cs, opcode, 3);
115 tu_cs_emit(cs,
116 CP_LOAD_STATE6_0_STATE_TYPE(st) |
117 CP_LOAD_STATE6_0_STATE_SRC(SS6_BINDLESS) |
118 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
119 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(count, 1024-1)));
120 tu_cs_emit_qw(cs, offset | (base << 28));
121 }
122
123 static unsigned
124 tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
125 {
126 const unsigned load_state_size = 4;
127 unsigned size = 0;
128 for (unsigned i = 0; i < layout->num_sets; i++) {
129 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
130 for (unsigned j = 0; j < set_layout->binding_count; j++) {
131 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
132 unsigned count = 0;
133 /* Note: some users, like amber for example, pass in
134 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
135 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
136 */
137 VkShaderStageFlags stages = compute ?
138 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
139 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
140 unsigned stage_count = util_bitcount(stages);
141 switch (binding->type) {
142 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
143 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
144 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
145 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
146 /* IBO-backed resources only need one packet for all graphics stages */
147 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT)
148 count += 1;
149 if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
150 count += 1;
151 break;
152 case VK_DESCRIPTOR_TYPE_SAMPLER:
153 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
154 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
155 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
156 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
157 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
158 /* Textures and UBO's needs a packet for each stage */
159 count = stage_count;
160 break;
161 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
162 /* Because of how we pack combined images and samplers, we
163 * currently can't use one packet for the whole array.
164 */
165 count = stage_count * binding->array_size * 2;
166 break;
167 default:
168 unreachable("bad descriptor type");
169 }
170 size += count * load_state_size;
171 }
172 }
173 return size;
174 }
175
176 static void
177 tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
178 {
179 unsigned size = tu6_load_state_size(pipeline->layout, compute);
180 if (size == 0)
181 return;
182
183 struct tu_cs cs;
184 tu_cs_begin_sub_stream(&pipeline->cs, size, &cs);
185
186 struct tu_pipeline_layout *layout = pipeline->layout;
187 for (unsigned i = 0; i < layout->num_sets; i++) {
188 struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
189 for (unsigned j = 0; j < set_layout->binding_count; j++) {
190 struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
191 unsigned base = i;
192 unsigned offset = binding->offset / 4;
193 /* Note: some users, like amber for example, pass in
194 * VK_SHADER_STAGE_ALL which includes a bunch of extra bits, so
195 * filter these out by using VK_SHADER_STAGE_ALL_GRAPHICS explicitly.
196 */
197 VkShaderStageFlags stages = compute ?
198 binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
199 binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
200 unsigned count = binding->array_size;
201 if (count == 0 || stages == 0)
202 continue;
203 switch (binding->type) {
204 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
205 base = MAX_SETS;
206 offset = (layout->input_attachment_count +
207 layout->set[i].dynamic_offset_start +
208 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
209 /* fallthrough */
210 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
212 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
213 /* IBO-backed resources only need one packet for all graphics stages */
214 if (stages & ~VK_SHADER_STAGE_COMPUTE_BIT) {
215 emit_load_state(&cs, CP_LOAD_STATE6, ST6_SHADER, SB6_IBO,
216 base, offset, count);
217 }
218 if (stages & VK_SHADER_STAGE_COMPUTE_BIT) {
219 emit_load_state(&cs, CP_LOAD_STATE6_FRAG, ST6_IBO, SB6_CS_SHADER,
220 base, offset, count);
221 }
222 break;
223 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
224 base = MAX_SETS;
225 offset = (layout->set[i].input_attachment_start +
226 binding->input_attachment_offset) * A6XX_TEX_CONST_DWORDS;
227 case VK_DESCRIPTOR_TYPE_SAMPLER:
228 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
229 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER: {
230 unsigned stage_log2;
231 for_each_bit(stage_log2, stages) {
232 VkShaderStageFlags stage = 1 << stage_log2;
233 emit_load_state(&cs, tu6_vkstage2opcode(stage),
234 binding->type == VK_DESCRIPTOR_TYPE_SAMPLER ?
235 ST6_SHADER : ST6_CONSTANTS,
236 tu6_tex_stage2sb(stage), base, offset, count);
237 }
238 break;
239 }
240 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
241 base = MAX_SETS;
242 offset = (layout->input_attachment_count +
243 layout->set[i].dynamic_offset_start +
244 binding->dynamic_offset_offset) * A6XX_TEX_CONST_DWORDS;
245 /* fallthrough */
246 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER: {
247 unsigned stage_log2;
248 for_each_bit(stage_log2, stages) {
249 VkShaderStageFlags stage = 1 << stage_log2;
250 emit_load_state(&cs, tu6_vkstage2opcode(stage), ST6_UBO,
251 tu6_ubo_stage2sb(stage), base, offset, count);
252 }
253 break;
254 }
255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER: {
256 unsigned stage_log2;
257 for_each_bit(stage_log2, stages) {
258 VkShaderStageFlags stage = 1 << stage_log2;
259 /* TODO: We could emit less CP_LOAD_STATE6 if we used
260 * struct-of-arrays instead of array-of-structs.
261 */
262 for (unsigned i = 0; i < count; i++) {
263 unsigned tex_offset = offset + 2 * i * A6XX_TEX_CONST_DWORDS;
264 unsigned sam_offset = offset + (2 * i + 1) * A6XX_TEX_CONST_DWORDS;
265 emit_load_state(&cs, tu6_vkstage2opcode(stage),
266 ST6_CONSTANTS, tu6_tex_stage2sb(stage),
267 base, tex_offset, 1);
268 emit_load_state(&cs, tu6_vkstage2opcode(stage),
269 ST6_SHADER, tu6_tex_stage2sb(stage),
270 base, sam_offset, 1);
271 }
272 }
273 break;
274 }
275 default:
276 unreachable("bad descriptor type");
277 }
278 }
279 }
280
281 pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
282 }
283
284 struct tu_pipeline_builder
285 {
286 struct tu_device *device;
287 struct tu_pipeline_cache *cache;
288 struct tu_pipeline_layout *layout;
289 const VkAllocationCallbacks *alloc;
290 const VkGraphicsPipelineCreateInfo *create_info;
291
292 struct tu_shader *shaders[MESA_SHADER_STAGES];
293 uint32_t shader_offsets[MESA_SHADER_STAGES];
294 uint32_t binning_vs_offset;
295 uint32_t shader_total_size;
296
297 bool rasterizer_discard;
298 /* these states are affectd by rasterizer_discard */
299 VkSampleCountFlagBits samples;
300 bool use_color_attachments;
301 uint32_t color_attachment_count;
302 VkFormat color_attachment_formats[MAX_RTS];
303 VkFormat depth_attachment_format;
304 };
305
306 static enum tu_dynamic_state_bits
307 tu_dynamic_state_bit(VkDynamicState state)
308 {
309 switch (state) {
310 case VK_DYNAMIC_STATE_VIEWPORT:
311 return TU_DYNAMIC_VIEWPORT;
312 case VK_DYNAMIC_STATE_SCISSOR:
313 return TU_DYNAMIC_SCISSOR;
314 case VK_DYNAMIC_STATE_LINE_WIDTH:
315 return TU_DYNAMIC_LINE_WIDTH;
316 case VK_DYNAMIC_STATE_DEPTH_BIAS:
317 return TU_DYNAMIC_DEPTH_BIAS;
318 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
319 return TU_DYNAMIC_BLEND_CONSTANTS;
320 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
321 return TU_DYNAMIC_DEPTH_BOUNDS;
322 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
323 return TU_DYNAMIC_STENCIL_COMPARE_MASK;
324 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
325 return TU_DYNAMIC_STENCIL_WRITE_MASK;
326 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
327 return TU_DYNAMIC_STENCIL_REFERENCE;
328 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
329 return TU_DYNAMIC_SAMPLE_LOCATIONS;
330 default:
331 unreachable("invalid dynamic state");
332 return 0;
333 }
334 }
335
336 static gl_shader_stage
337 tu_shader_stage(VkShaderStageFlagBits stage)
338 {
339 switch (stage) {
340 case VK_SHADER_STAGE_VERTEX_BIT:
341 return MESA_SHADER_VERTEX;
342 case VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT:
343 return MESA_SHADER_TESS_CTRL;
344 case VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT:
345 return MESA_SHADER_TESS_EVAL;
346 case VK_SHADER_STAGE_GEOMETRY_BIT:
347 return MESA_SHADER_GEOMETRY;
348 case VK_SHADER_STAGE_FRAGMENT_BIT:
349 return MESA_SHADER_FRAGMENT;
350 case VK_SHADER_STAGE_COMPUTE_BIT:
351 return MESA_SHADER_COMPUTE;
352 default:
353 unreachable("invalid VkShaderStageFlagBits");
354 return MESA_SHADER_NONE;
355 }
356 }
357
358 static bool
359 tu_logic_op_reads_dst(VkLogicOp op)
360 {
361 switch (op) {
362 case VK_LOGIC_OP_CLEAR:
363 case VK_LOGIC_OP_COPY:
364 case VK_LOGIC_OP_COPY_INVERTED:
365 case VK_LOGIC_OP_SET:
366 return false;
367 default:
368 return true;
369 }
370 }
371
372 static VkBlendFactor
373 tu_blend_factor_no_dst_alpha(VkBlendFactor factor)
374 {
375 /* treat dst alpha as 1.0 and avoid reading it */
376 switch (factor) {
377 case VK_BLEND_FACTOR_DST_ALPHA:
378 return VK_BLEND_FACTOR_ONE;
379 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
380 return VK_BLEND_FACTOR_ZERO;
381 default:
382 return factor;
383 }
384 }
385
386 static enum pc_di_primtype
387 tu6_primtype(VkPrimitiveTopology topology)
388 {
389 switch (topology) {
390 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
391 return DI_PT_POINTLIST;
392 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
393 return DI_PT_LINELIST;
394 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
395 return DI_PT_LINESTRIP;
396 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
397 return DI_PT_TRILIST;
398 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
399 return DI_PT_TRISTRIP;
400 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
401 return DI_PT_TRIFAN;
402 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
403 return DI_PT_LINE_ADJ;
404 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
405 return DI_PT_LINESTRIP_ADJ;
406 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
407 return DI_PT_TRI_ADJ;
408 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
409 return DI_PT_TRISTRIP_ADJ;
410 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
411 default:
412 unreachable("invalid primitive topology");
413 return DI_PT_NONE;
414 }
415 }
416
417 static enum adreno_compare_func
418 tu6_compare_func(VkCompareOp op)
419 {
420 switch (op) {
421 case VK_COMPARE_OP_NEVER:
422 return FUNC_NEVER;
423 case VK_COMPARE_OP_LESS:
424 return FUNC_LESS;
425 case VK_COMPARE_OP_EQUAL:
426 return FUNC_EQUAL;
427 case VK_COMPARE_OP_LESS_OR_EQUAL:
428 return FUNC_LEQUAL;
429 case VK_COMPARE_OP_GREATER:
430 return FUNC_GREATER;
431 case VK_COMPARE_OP_NOT_EQUAL:
432 return FUNC_NOTEQUAL;
433 case VK_COMPARE_OP_GREATER_OR_EQUAL:
434 return FUNC_GEQUAL;
435 case VK_COMPARE_OP_ALWAYS:
436 return FUNC_ALWAYS;
437 default:
438 unreachable("invalid VkCompareOp");
439 return FUNC_NEVER;
440 }
441 }
442
443 static enum adreno_stencil_op
444 tu6_stencil_op(VkStencilOp op)
445 {
446 switch (op) {
447 case VK_STENCIL_OP_KEEP:
448 return STENCIL_KEEP;
449 case VK_STENCIL_OP_ZERO:
450 return STENCIL_ZERO;
451 case VK_STENCIL_OP_REPLACE:
452 return STENCIL_REPLACE;
453 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
454 return STENCIL_INCR_CLAMP;
455 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
456 return STENCIL_DECR_CLAMP;
457 case VK_STENCIL_OP_INVERT:
458 return STENCIL_INVERT;
459 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
460 return STENCIL_INCR_WRAP;
461 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
462 return STENCIL_DECR_WRAP;
463 default:
464 unreachable("invalid VkStencilOp");
465 return STENCIL_KEEP;
466 }
467 }
468
469 static enum a3xx_rop_code
470 tu6_rop(VkLogicOp op)
471 {
472 switch (op) {
473 case VK_LOGIC_OP_CLEAR:
474 return ROP_CLEAR;
475 case VK_LOGIC_OP_AND:
476 return ROP_AND;
477 case VK_LOGIC_OP_AND_REVERSE:
478 return ROP_AND_REVERSE;
479 case VK_LOGIC_OP_COPY:
480 return ROP_COPY;
481 case VK_LOGIC_OP_AND_INVERTED:
482 return ROP_AND_INVERTED;
483 case VK_LOGIC_OP_NO_OP:
484 return ROP_NOOP;
485 case VK_LOGIC_OP_XOR:
486 return ROP_XOR;
487 case VK_LOGIC_OP_OR:
488 return ROP_OR;
489 case VK_LOGIC_OP_NOR:
490 return ROP_NOR;
491 case VK_LOGIC_OP_EQUIVALENT:
492 return ROP_EQUIV;
493 case VK_LOGIC_OP_INVERT:
494 return ROP_INVERT;
495 case VK_LOGIC_OP_OR_REVERSE:
496 return ROP_OR_REVERSE;
497 case VK_LOGIC_OP_COPY_INVERTED:
498 return ROP_COPY_INVERTED;
499 case VK_LOGIC_OP_OR_INVERTED:
500 return ROP_OR_INVERTED;
501 case VK_LOGIC_OP_NAND:
502 return ROP_NAND;
503 case VK_LOGIC_OP_SET:
504 return ROP_SET;
505 default:
506 unreachable("invalid VkLogicOp");
507 return ROP_NOOP;
508 }
509 }
510
511 static enum adreno_rb_blend_factor
512 tu6_blend_factor(VkBlendFactor factor)
513 {
514 switch (factor) {
515 case VK_BLEND_FACTOR_ZERO:
516 return FACTOR_ZERO;
517 case VK_BLEND_FACTOR_ONE:
518 return FACTOR_ONE;
519 case VK_BLEND_FACTOR_SRC_COLOR:
520 return FACTOR_SRC_COLOR;
521 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
522 return FACTOR_ONE_MINUS_SRC_COLOR;
523 case VK_BLEND_FACTOR_DST_COLOR:
524 return FACTOR_DST_COLOR;
525 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
526 return FACTOR_ONE_MINUS_DST_COLOR;
527 case VK_BLEND_FACTOR_SRC_ALPHA:
528 return FACTOR_SRC_ALPHA;
529 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
530 return FACTOR_ONE_MINUS_SRC_ALPHA;
531 case VK_BLEND_FACTOR_DST_ALPHA:
532 return FACTOR_DST_ALPHA;
533 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
534 return FACTOR_ONE_MINUS_DST_ALPHA;
535 case VK_BLEND_FACTOR_CONSTANT_COLOR:
536 return FACTOR_CONSTANT_COLOR;
537 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
538 return FACTOR_ONE_MINUS_CONSTANT_COLOR;
539 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
540 return FACTOR_CONSTANT_ALPHA;
541 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
542 return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
543 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
544 return FACTOR_SRC_ALPHA_SATURATE;
545 case VK_BLEND_FACTOR_SRC1_COLOR:
546 return FACTOR_SRC1_COLOR;
547 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
548 return FACTOR_ONE_MINUS_SRC1_COLOR;
549 case VK_BLEND_FACTOR_SRC1_ALPHA:
550 return FACTOR_SRC1_ALPHA;
551 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
552 return FACTOR_ONE_MINUS_SRC1_ALPHA;
553 default:
554 unreachable("invalid VkBlendFactor");
555 return FACTOR_ZERO;
556 }
557 }
558
559 static enum a3xx_rb_blend_opcode
560 tu6_blend_op(VkBlendOp op)
561 {
562 switch (op) {
563 case VK_BLEND_OP_ADD:
564 return BLEND_DST_PLUS_SRC;
565 case VK_BLEND_OP_SUBTRACT:
566 return BLEND_SRC_MINUS_DST;
567 case VK_BLEND_OP_REVERSE_SUBTRACT:
568 return BLEND_DST_MINUS_SRC;
569 case VK_BLEND_OP_MIN:
570 return BLEND_MIN_DST_SRC;
571 case VK_BLEND_OP_MAX:
572 return BLEND_MAX_DST_SRC;
573 default:
574 unreachable("invalid VkBlendOp");
575 return BLEND_DST_PLUS_SRC;
576 }
577 }
578
579 static uint32_t
580 emit_xs_config(const struct ir3_shader_variant *sh)
581 {
582 if (sh->instrlen) {
583 return A6XX_SP_VS_CONFIG_ENABLED |
584 COND(sh->bindless_tex, A6XX_SP_VS_CONFIG_BINDLESS_TEX) |
585 COND(sh->bindless_samp, A6XX_SP_VS_CONFIG_BINDLESS_SAMP) |
586 COND(sh->bindless_ibo, A6XX_SP_VS_CONFIG_BINDLESS_IBO) |
587 COND(sh->bindless_ubo, A6XX_SP_VS_CONFIG_BINDLESS_UBO);
588 } else {
589 return 0;
590 }
591 }
592
593 static void
594 tu6_emit_vs_config(struct tu_cs *cs, struct tu_shader *shader,
595 const struct ir3_shader_variant *vs)
596 {
597 uint32_t sp_vs_ctrl =
598 A6XX_SP_VS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
599 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
600 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
601 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
602 if (vs->need_pixlod)
603 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
604 if (vs->need_fine_derivatives)
605 sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_DIFF_FINE;
606
607 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CTRL_REG0, 1);
608 tu_cs_emit(cs, sp_vs_ctrl);
609
610 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_CONFIG, 2);
611 tu_cs_emit(cs, emit_xs_config(vs));
612 tu_cs_emit(cs, vs->instrlen);
613
614 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
615 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
616 A6XX_HLSQ_VS_CNTL_ENABLED);
617 }
618
619 static void
620 tu6_emit_hs_config(struct tu_cs *cs, struct tu_shader *shader,
621 const struct ir3_shader_variant *hs)
622 {
623 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
624 tu_cs_emit(cs, 0);
625
626 tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CONFIG, 2);
627 tu_cs_emit(cs, emit_xs_config(hs));
628 tu_cs_emit(cs, hs->instrlen);
629
630 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_HS_CNTL, 1);
631 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
632 }
633
634 static void
635 tu6_emit_ds_config(struct tu_cs *cs, struct tu_shader *shader,
636 const struct ir3_shader_variant *ds)
637 {
638 tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_CONFIG, 2);
639 tu_cs_emit(cs, emit_xs_config(ds));
640 tu_cs_emit(cs, ds->instrlen);
641
642 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_DS_CNTL, 1);
643 tu_cs_emit(cs, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(ds->constlen, 4)));
644 }
645
646 static void
647 tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader,
648 const struct ir3_shader_variant *gs)
649 {
650 bool has_gs = gs->type != MESA_SHADER_NONE;
651 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
652 tu_cs_emit(cs, 0);
653
654 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2);
655 tu_cs_emit(cs, emit_xs_config(gs));
656 tu_cs_emit(cs, gs->instrlen);
657
658 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1);
659 tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) |
660 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4)));
661 }
662
663 static void
664 tu6_emit_fs_config(struct tu_cs *cs, struct tu_shader *shader,
665 const struct ir3_shader_variant *fs)
666 {
667 uint32_t sp_fs_ctrl =
668 A6XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) | 0x1000000 |
669 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
670 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
671 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
672 if (fs->total_in > 0)
673 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
674 if (fs->need_pixlod)
675 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
676 if (fs->need_fine_derivatives)
677 sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_DIFF_FINE;
678
679 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CTRL_REG0, 1);
680 tu_cs_emit(cs, sp_fs_ctrl);
681
682 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_CONFIG, 2);
683 tu_cs_emit(cs, emit_xs_config(fs));
684 tu_cs_emit(cs, fs->instrlen);
685
686 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
687 tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
688 A6XX_HLSQ_FS_CNTL_ENABLED);
689 }
690
691 static void
692 tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader,
693 const struct ir3_shader_variant *v)
694 {
695 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
696 tu_cs_emit(cs, 0xff);
697
698 unsigned constlen = align(v->constlen, 4);
699 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL, 1);
700 tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) |
701 A6XX_HLSQ_CS_CNTL_ENABLED);
702
703 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONFIG, 2);
704 tu_cs_emit(cs, emit_xs_config(v));
705 tu_cs_emit(cs, v->instrlen);
706
707 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG0, 1);
708 tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
709 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(v->info.max_reg + 1) |
710 A6XX_SP_CS_CTRL_REG0_MERGEDREGS |
711 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v->branchstack) |
712 COND(v->need_pixlod, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE) |
713 COND(v->need_fine_derivatives, A6XX_SP_CS_CTRL_REG0_DIFF_FINE));
714
715 tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
716 tu_cs_emit(cs, 0x41);
717
718 uint32_t local_invocation_id =
719 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
720 uint32_t work_group_id =
721 ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
722
723 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
724 tu_cs_emit(cs,
725 A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
726 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
727 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
728 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
729 tu_cs_emit(cs, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
730 }
731
732 static void
733 tu6_emit_vs_system_values(struct tu_cs *cs,
734 const struct ir3_shader_variant *vs,
735 const struct ir3_shader_variant *gs)
736 {
737 const uint32_t vertexid_regid =
738 ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
739 const uint32_t instanceid_regid =
740 ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
741 const uint32_t primitiveid_regid = gs->type != MESA_SHADER_NONE ?
742 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
743 regid(63, 0);
744 const uint32_t gsheader_regid = gs->type != MESA_SHADER_NONE ?
745 ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3) :
746 regid(63, 0);
747
748 tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 6);
749 tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
750 A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
751 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
752 0xfc000000);
753 tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
754 tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
755 tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
756 tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
757 0xfc00); /* VFD_CONTROL_5 */
758 tu_cs_emit(cs, 0x00000000); /* VFD_CONTROL_6 */
759 }
760
761 /* Add any missing varyings needed for stream-out. Otherwise varyings not
762 * used by fragment shader will be stripped out.
763 */
764 static void
765 tu6_link_streamout(struct ir3_shader_linkage *l,
766 const struct ir3_shader_variant *v)
767 {
768 const struct ir3_stream_output_info *info = &v->shader->stream_output;
769
770 /*
771 * First, any stream-out varyings not already in linkage map (ie. also
772 * consumed by frag shader) need to be added:
773 */
774 for (unsigned i = 0; i < info->num_outputs; i++) {
775 const struct ir3_stream_output *out = &info->output[i];
776 unsigned compmask =
777 (1 << (out->num_components + out->start_component)) - 1;
778 unsigned k = out->register_index;
779 unsigned idx, nextloc = 0;
780
781 /* psize/pos need to be the last entries in linkage map, and will
782 * get added link_stream_out, so skip over them:
783 */
784 if (v->outputs[k].slot == VARYING_SLOT_PSIZ ||
785 v->outputs[k].slot == VARYING_SLOT_POS)
786 continue;
787
788 for (idx = 0; idx < l->cnt; idx++) {
789 if (l->var[idx].regid == v->outputs[k].regid)
790 break;
791 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
792 }
793
794 /* add if not already in linkage map: */
795 if (idx == l->cnt)
796 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
797
798 /* expand component-mask if needed, ie streaming out all components
799 * but frag shader doesn't consume all components:
800 */
801 if (compmask & ~l->var[idx].compmask) {
802 l->var[idx].compmask |= compmask;
803 l->max_loc = MAX2(l->max_loc, l->var[idx].loc +
804 util_last_bit(l->var[idx].compmask));
805 }
806 }
807 }
808
809 static void
810 tu6_setup_streamout(const struct ir3_shader_variant *v,
811 struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
812 {
813 const struct ir3_stream_output_info *info = &v->shader->stream_output;
814
815 memset(tf, 0, sizeof(*tf));
816
817 tf->prog_count = align(l->max_loc, 2) / 2;
818
819 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
820
821 /* set stride info to the streamout state */
822 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
823 tf->stride[i] = info->stride[i];
824
825 for (unsigned i = 0; i < info->num_outputs; i++) {
826 const struct ir3_stream_output *out = &info->output[i];
827 unsigned k = out->register_index;
828 unsigned idx;
829
830 tf->ncomp[out->output_buffer] += out->num_components;
831
832 /* linkage map sorted by order frag shader wants things, so
833 * a bit less ideal here..
834 */
835 for (idx = 0; idx < l->cnt; idx++)
836 if (l->var[idx].regid == v->outputs[k].regid)
837 break;
838
839 debug_assert(idx < l->cnt);
840
841 for (unsigned j = 0; j < out->num_components; j++) {
842 unsigned c = j + out->start_component;
843 unsigned loc = l->var[idx].loc + c;
844 unsigned off = j + out->dst_offset; /* in dwords */
845
846 if (loc & 1) {
847 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
848 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
849 A6XX_VPC_SO_PROG_B_OFF(off * 4);
850 } else {
851 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
852 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
853 A6XX_VPC_SO_PROG_A_OFF(off * 4);
854 }
855 }
856 }
857
858 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
859 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
860 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
861 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
862 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
863 }
864
865 static void
866 tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
867 enum a6xx_state_block block, uint32_t offset,
868 uint32_t size, uint32_t *dwords) {
869 assert(size % 4 == 0);
870
871 tu_cs_emit_pkt7(cs, opcode, 3 + size);
872 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
873 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
874 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
875 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
876 CP_LOAD_STATE6_0_NUM_UNIT(size / 4));
877
878 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
879 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
880 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
881
882 tu_cs_emit_array(cs, dwords, size);
883 }
884
885 static void
886 tu6_emit_link_map(struct tu_cs *cs,
887 const struct ir3_shader_variant *producer,
888 const struct ir3_shader_variant *consumer) {
889 const struct ir3_const_state *const_state = &consumer->shader->const_state;
890 uint32_t base = const_state->offsets.primitive_map;
891 uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
892 num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
893 int size = DIV_ROUND_UP(num_loc, 4);
894
895 size = (MIN2(size + base, consumer->constlen) - base) * 4;
896
897 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
898 patch_locs);
899 }
900
901 static uint16_t
902 gl_primitive_to_tess(uint16_t primitive) {
903 switch (primitive) {
904 case GL_POINTS:
905 return TESS_POINTS;
906 case GL_LINE_STRIP:
907 return TESS_LINES;
908 case GL_TRIANGLE_STRIP:
909 return TESS_CW_TRIS;
910 default:
911 unreachable("");
912 }
913 }
914
915 static void
916 tu6_emit_vpc(struct tu_cs *cs,
917 const struct ir3_shader_variant *vs,
918 const struct ir3_shader_variant *gs,
919 const struct ir3_shader_variant *fs,
920 bool binning_pass,
921 struct tu_streamout_state *tf)
922 {
923 bool has_gs = gs->type != MESA_SHADER_NONE;
924 const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
925 struct ir3_shader_linkage linkage = { 0 };
926 ir3_link_shaders(&linkage, last_shader, fs);
927
928 if (last_shader->shader->stream_output.num_outputs)
929 tu6_link_streamout(&linkage, last_shader);
930
931 BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
932 for (uint32_t i = 0; i < linkage.cnt; i++) {
933 const uint32_t comp_count = util_last_bit(linkage.var[i].compmask);
934 for (uint32_t j = 0; j < comp_count; j++)
935 BITSET_SET(vpc_var_enables, linkage.var[i].loc + j);
936 }
937
938 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
939 tu_cs_emit(cs, ~vpc_var_enables[0]);
940 tu_cs_emit(cs, ~vpc_var_enables[1]);
941 tu_cs_emit(cs, ~vpc_var_enables[2]);
942 tu_cs_emit(cs, ~vpc_var_enables[3]);
943
944 /* a6xx finds position/pointsize at the end */
945 const uint32_t position_regid =
946 ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
947 const uint32_t pointsize_regid =
948 ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
949 const uint32_t layer_regid = has_gs ?
950 ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
951
952 uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
953 if (layer_regid != regid(63, 0)) {
954 layer_loc = linkage.max_loc;
955 ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
956 }
957 if (position_regid != regid(63, 0)) {
958 position_loc = linkage.max_loc;
959 ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
960 }
961 if (pointsize_regid != regid(63, 0)) {
962 pointsize_loc = linkage.max_loc;
963 ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
964 }
965
966 if (last_shader->shader->stream_output.num_outputs)
967 tu6_setup_streamout(last_shader, &linkage, tf);
968
969 /* map outputs of the last shader to VPC */
970 assert(linkage.cnt <= 32);
971 const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
972 const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
973 uint32_t sp_out[16];
974 uint32_t sp_vpc_dst[8];
975 for (uint32_t i = 0; i < linkage.cnt; i++) {
976 ((uint16_t *) sp_out)[i] =
977 A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
978 A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
979 ((uint8_t *) sp_vpc_dst)[i] =
980 A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
981 }
982
983 if (has_gs)
984 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
985 else
986 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
987 tu_cs_emit_array(cs, sp_out, sp_out_count);
988
989 if (has_gs)
990 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
991 else
992 tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
993 tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
994
995 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
996 tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
997 (fs->total_in > 0 ? A6XX_VPC_CNTL_0_VARYING : 0) |
998 0xff00ff00);
999
1000 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
1001 tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
1002 A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
1003 A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
1004
1005 if (has_gs) {
1006 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
1007 tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
1008 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
1009 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
1010 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
1011
1012 tu6_emit_link_map(cs, vs, gs);
1013
1014 uint32_t primitive_regid =
1015 ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
1016 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
1017 tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
1018 A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
1019 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
1020
1021 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
1022 tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
1023
1024 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
1025 tu_cs_emit(cs, CONDREG(layer_regid,
1026 A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
1027
1028 uint32_t flags_regid = ir3_find_output_regid(gs,
1029 VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
1030
1031 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
1032 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
1033 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
1034
1035 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
1036 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
1037 CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
1038 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
1039 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
1040
1041 uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
1042 uint16_t output =
1043 gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
1044 uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
1045 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
1046 tu_cs_emit(cs,
1047 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
1048 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
1049 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
1050
1051 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
1052 tu_cs_emit(cs, 0);
1053
1054 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
1055 tu_cs_emit(cs, 0);
1056
1057 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
1058 tu_cs_emit(cs, 0xff);
1059
1060 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
1061 tu_cs_emit(cs, 0xffff00);
1062
1063 /* Size of per-primitive alloction in ldlw memory in vec4s. */
1064 uint32_t vec4_size =
1065 gs->shader->nir->info.gs.vertices_in *
1066 DIV_ROUND_UP(vs->shader->output_size, 4);
1067 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
1068 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
1069
1070 tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
1071 tu_cs_emit(cs, 0);
1072
1073 tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
1074 tu_cs_emit(cs, vs->shader->output_size);
1075 }
1076
1077 tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
1078 tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
1079
1080 tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
1081 tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
1082 (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
1083 }
1084
1085 static int
1086 tu6_vpc_varying_mode(const struct ir3_shader_variant *fs,
1087 uint32_t index,
1088 uint8_t *interp_mode,
1089 uint8_t *ps_repl_mode)
1090 {
1091 enum
1092 {
1093 INTERP_SMOOTH = 0,
1094 INTERP_FLAT = 1,
1095 INTERP_ZERO = 2,
1096 INTERP_ONE = 3,
1097 };
1098 enum
1099 {
1100 PS_REPL_NONE = 0,
1101 PS_REPL_S = 1,
1102 PS_REPL_T = 2,
1103 PS_REPL_ONE_MINUS_T = 3,
1104 };
1105
1106 const uint32_t compmask = fs->inputs[index].compmask;
1107
1108 /* NOTE: varyings are packed, so if compmask is 0xb then first, second, and
1109 * fourth component occupy three consecutive varying slots
1110 */
1111 int shift = 0;
1112 *interp_mode = 0;
1113 *ps_repl_mode = 0;
1114 if (fs->inputs[index].slot == VARYING_SLOT_PNTC) {
1115 if (compmask & 0x1) {
1116 *ps_repl_mode |= PS_REPL_S << shift;
1117 shift += 2;
1118 }
1119 if (compmask & 0x2) {
1120 *ps_repl_mode |= PS_REPL_T << shift;
1121 shift += 2;
1122 }
1123 if (compmask & 0x4) {
1124 *interp_mode |= INTERP_ZERO << shift;
1125 shift += 2;
1126 }
1127 if (compmask & 0x8) {
1128 *interp_mode |= INTERP_ONE << 6;
1129 shift += 2;
1130 }
1131 } else if ((fs->inputs[index].interpolate == INTERP_MODE_FLAT) ||
1132 fs->inputs[index].rasterflat) {
1133 for (int i = 0; i < 4; i++) {
1134 if (compmask & (1 << i)) {
1135 *interp_mode |= INTERP_FLAT << shift;
1136 shift += 2;
1137 }
1138 }
1139 }
1140
1141 return shift;
1142 }
1143
1144 static void
1145 tu6_emit_vpc_varying_modes(struct tu_cs *cs,
1146 const struct ir3_shader_variant *fs,
1147 bool binning_pass)
1148 {
1149 uint32_t interp_modes[8] = { 0 };
1150 uint32_t ps_repl_modes[8] = { 0 };
1151
1152 if (!binning_pass) {
1153 for (int i = -1;
1154 (i = ir3_next_varying(fs, i)) < (int) fs->inputs_count;) {
1155
1156 /* get the mode for input i */
1157 uint8_t interp_mode;
1158 uint8_t ps_repl_mode;
1159 const int bits =
1160 tu6_vpc_varying_mode(fs, i, &interp_mode, &ps_repl_mode);
1161
1162 /* OR the mode into the array */
1163 const uint32_t inloc = fs->inputs[i].inloc * 2;
1164 uint32_t n = inloc / 32;
1165 uint32_t shift = inloc % 32;
1166 interp_modes[n] |= interp_mode << shift;
1167 ps_repl_modes[n] |= ps_repl_mode << shift;
1168 if (shift + bits > 32) {
1169 n++;
1170 shift = 32 - shift;
1171
1172 interp_modes[n] |= interp_mode >> shift;
1173 ps_repl_modes[n] |= ps_repl_mode >> shift;
1174 }
1175 }
1176 }
1177
1178 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
1179 tu_cs_emit_array(cs, interp_modes, 8);
1180
1181 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
1182 tu_cs_emit_array(cs, ps_repl_modes, 8);
1183 }
1184
1185 static void
1186 tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
1187 {
1188 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
1189 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
1190 uint32_t smask_in_regid;
1191
1192 bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
1193 bool enable_varyings = fs->total_in > 0;
1194
1195 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
1196 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
1197 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
1198 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
1199 zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
1200 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1201 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1202 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1203 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1204
1205 if (fs->num_sampler_prefetch > 0) {
1206 assert(VALIDREG(ij_pix_regid));
1207 /* also, it seems like ij_pix is *required* to be r0.x */
1208 assert(ij_pix_regid == regid(0, 0));
1209 }
1210
1211 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
1212 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
1213 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
1214 0x7000); // XXX);
1215 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1216 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1217 tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
1218 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
1219 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
1220 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
1221 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
1222 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
1223 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
1224 }
1225
1226 if (fs->num_sampler_prefetch > 0) {
1227 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
1228 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
1229 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
1230 tu_cs_emit(cs,
1231 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
1232 A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
1233 }
1234 }
1235
1236 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
1237 tu_cs_emit(cs, 0x7);
1238 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
1239 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
1240 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
1241 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
1242 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
1243 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
1244 0xfc00fc00);
1245 tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
1246 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
1247 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
1248 0x0000fc00);
1249 tu_cs_emit(cs, 0xfc);
1250
1251 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
1252 tu_cs_emit(cs, enable_varyings ? 3 : 1);
1253
1254 tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
1255 tu_cs_emit(cs, 0xff); /* XXX */
1256
1257 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
1258 tu_cs_emit(cs,
1259 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
1260 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
1261 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
1262 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
1263 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
1264 COND(fs->frag_coord,
1265 A6XX_GRAS_CNTL_SIZE |
1266 A6XX_GRAS_CNTL_XCOORD |
1267 A6XX_GRAS_CNTL_YCOORD |
1268 A6XX_GRAS_CNTL_ZCOORD |
1269 A6XX_GRAS_CNTL_WCOORD) |
1270 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
1271
1272 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
1273 tu_cs_emit(cs,
1274 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
1275 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
1276 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
1277 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
1278 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
1279 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
1280 COND(fs->frag_coord,
1281 A6XX_RB_RENDER_CONTROL0_SIZE |
1282 A6XX_RB_RENDER_CONTROL0_XCOORD |
1283 A6XX_RB_RENDER_CONTROL0_YCOORD |
1284 A6XX_RB_RENDER_CONTROL0_ZCOORD |
1285 A6XX_RB_RENDER_CONTROL0_WCOORD) |
1286 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
1287 tu_cs_emit(cs,
1288 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
1289 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
1290 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
1291 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
1292
1293 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
1294 tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
1295
1296 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8101, 1);
1297 tu_cs_emit(cs, COND(sample_shading, 0x6)); // XXX
1298
1299 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
1300 tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
1301 }
1302
1303 static void
1304 tu6_emit_fs_outputs(struct tu_cs *cs,
1305 const struct ir3_shader_variant *fs,
1306 uint32_t mrt_count)
1307 {
1308 uint32_t smask_regid, posz_regid;
1309
1310 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
1311 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
1312
1313 uint32_t fragdata_regid[8];
1314 if (fs->color0_mrt) {
1315 fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
1316 for (uint32_t i = 1; i < ARRAY_SIZE(fragdata_regid); i++)
1317 fragdata_regid[i] = fragdata_regid[0];
1318 } else {
1319 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++)
1320 fragdata_regid[i] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + i);
1321 }
1322
1323 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
1324 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
1325 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
1326 0xfc000000);
1327 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
1328
1329 tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
1330 for (uint32_t i = 0; i < ARRAY_SIZE(fragdata_regid); i++) {
1331 // TODO we could have a mix of half and full precision outputs,
1332 // we really need to figure out half-precision from IR3_REG_HALF
1333 tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
1334 (false ? A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION : 0));
1335 }
1336
1337 tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
1338 tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
1339 COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
1340 tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
1341
1342 uint32_t gras_su_depth_plane_cntl = 0;
1343 uint32_t rb_depth_plane_cntl = 0;
1344 if (fs->no_earlyz || fs->writes_pos) {
1345 gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1346 rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
1347 }
1348
1349 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
1350 tu_cs_emit(cs, gras_su_depth_plane_cntl);
1351
1352 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
1353 tu_cs_emit(cs, rb_depth_plane_cntl);
1354 }
1355
1356 static void
1357 tu6_emit_shader_object(struct tu_cs *cs,
1358 gl_shader_stage stage,
1359 const struct ir3_shader_variant *variant,
1360 const struct tu_bo *binary_bo,
1361 uint32_t binary_offset)
1362 {
1363 uint16_t reg;
1364 uint8_t opcode;
1365 enum a6xx_state_block sb;
1366 switch (stage) {
1367 case MESA_SHADER_VERTEX:
1368 reg = REG_A6XX_SP_VS_OBJ_START_LO;
1369 opcode = CP_LOAD_STATE6_GEOM;
1370 sb = SB6_VS_SHADER;
1371 break;
1372 case MESA_SHADER_TESS_CTRL:
1373 reg = REG_A6XX_SP_HS_OBJ_START_LO;
1374 opcode = CP_LOAD_STATE6_GEOM;
1375 sb = SB6_HS_SHADER;
1376 break;
1377 case MESA_SHADER_TESS_EVAL:
1378 reg = REG_A6XX_SP_DS_OBJ_START_LO;
1379 opcode = CP_LOAD_STATE6_GEOM;
1380 sb = SB6_DS_SHADER;
1381 break;
1382 case MESA_SHADER_GEOMETRY:
1383 reg = REG_A6XX_SP_GS_OBJ_START_LO;
1384 opcode = CP_LOAD_STATE6_GEOM;
1385 sb = SB6_GS_SHADER;
1386 break;
1387 case MESA_SHADER_FRAGMENT:
1388 reg = REG_A6XX_SP_FS_OBJ_START_LO;
1389 opcode = CP_LOAD_STATE6_FRAG;
1390 sb = SB6_FS_SHADER;
1391 break;
1392 case MESA_SHADER_COMPUTE:
1393 reg = REG_A6XX_SP_CS_OBJ_START_LO;
1394 opcode = CP_LOAD_STATE6_FRAG;
1395 sb = SB6_CS_SHADER;
1396 break;
1397 default:
1398 unreachable("invalid gl_shader_stage");
1399 opcode = CP_LOAD_STATE6_GEOM;
1400 sb = SB6_VS_SHADER;
1401 break;
1402 }
1403
1404 if (!variant->instrlen) {
1405 tu_cs_emit_pkt4(cs, reg, 2);
1406 tu_cs_emit_qw(cs, 0);
1407 return;
1408 }
1409
1410 assert(variant->type == stage);
1411
1412 const uint64_t binary_iova = binary_bo->iova + binary_offset;
1413 assert((binary_iova & 0xf) == 0);
1414 /* note: it looks like HW might try to read a few instructions beyond the instrlen size
1415 * of the shader. this could be a potential source of problems at some point
1416 * possibly this doesn't happen if shader iova is aligned enough (to 4k for example)
1417 */
1418
1419 tu_cs_emit_pkt4(cs, reg, 2);
1420 tu_cs_emit_qw(cs, binary_iova);
1421
1422 /* always indirect */
1423 const bool indirect = true;
1424 if (indirect) {
1425 tu_cs_emit_pkt7(cs, opcode, 3);
1426 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1427 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1428 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1429 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1430 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1431 tu_cs_emit_qw(cs, binary_iova);
1432 } else {
1433 const void *binary = binary_bo->map + binary_offset;
1434
1435 tu_cs_emit_pkt7(cs, opcode, 3 + variant->info.sizedwords);
1436 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1437 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1438 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1439 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
1440 CP_LOAD_STATE6_0_NUM_UNIT(variant->instrlen));
1441 tu_cs_emit_qw(cs, 0);
1442 tu_cs_emit_array(cs, binary, variant->info.sizedwords);
1443 }
1444 }
1445
1446 static void
1447 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
1448 uint32_t opcode, enum a6xx_state_block block)
1449 {
1450 /* dummy variant */
1451 if (!v->shader)
1452 return;
1453
1454 const struct ir3_const_state *const_state = &v->shader->const_state;
1455 uint32_t base = const_state->offsets.immediate;
1456 int size = const_state->immediates_count;
1457
1458 /* truncate size to avoid writing constants that shader
1459 * does not use:
1460 */
1461 size = MIN2(size + base, v->constlen) - base;
1462
1463 if (size <= 0)
1464 return;
1465
1466 tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
1467 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
1468 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1469 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
1470 CP_LOAD_STATE6_0_STATE_BLOCK(block) |
1471 CP_LOAD_STATE6_0_NUM_UNIT(size));
1472 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
1473 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
1474
1475 for (unsigned i = 0; i < size; i++) {
1476 tu_cs_emit(cs, const_state->immediates[i].val[0]);
1477 tu_cs_emit(cs, const_state->immediates[i].val[1]);
1478 tu_cs_emit(cs, const_state->immediates[i].val[2]);
1479 tu_cs_emit(cs, const_state->immediates[i].val[3]);
1480 }
1481 }
1482
1483 static void
1484 tu6_emit_geometry_consts(struct tu_cs *cs,
1485 const struct ir3_shader_variant *vs,
1486 const struct ir3_shader_variant *gs) {
1487 unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
1488
1489 uint32_t params[4] = {
1490 vs->shader->output_size * num_vertices * 4, /* primitive stride */
1491 vs->shader->output_size * 4, /* vertex stride */
1492 0,
1493 0,
1494 };
1495 uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
1496 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
1497 ARRAY_SIZE(params), params);
1498
1499 uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
1500 tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
1501 ARRAY_SIZE(params), params);
1502 }
1503
1504 static void
1505 tu6_emit_program(struct tu_cs *cs,
1506 const struct tu_pipeline_builder *builder,
1507 const struct tu_bo *binary_bo,
1508 bool binning_pass,
1509 struct tu_streamout_state *tf)
1510 {
1511 static const struct ir3_shader_variant dummy_variant = {
1512 .type = MESA_SHADER_NONE
1513 };
1514 assert(builder->shaders[MESA_SHADER_VERTEX]);
1515 const struct ir3_shader_variant *vs =
1516 &builder->shaders[MESA_SHADER_VERTEX]->variants[0];
1517 const struct ir3_shader_variant *hs =
1518 builder->shaders[MESA_SHADER_TESS_CTRL]
1519 ? &builder->shaders[MESA_SHADER_TESS_CTRL]->variants[0]
1520 : &dummy_variant;
1521 const struct ir3_shader_variant *ds =
1522 builder->shaders[MESA_SHADER_TESS_EVAL]
1523 ? &builder->shaders[MESA_SHADER_TESS_EVAL]->variants[0]
1524 : &dummy_variant;
1525 const struct ir3_shader_variant *gs =
1526 builder->shaders[MESA_SHADER_GEOMETRY]
1527 ? &builder->shaders[MESA_SHADER_GEOMETRY]->variants[0]
1528 : &dummy_variant;
1529 const struct ir3_shader_variant *fs =
1530 builder->shaders[MESA_SHADER_FRAGMENT]
1531 ? &builder->shaders[MESA_SHADER_FRAGMENT]->variants[0]
1532 : &dummy_variant;
1533 bool has_gs = gs->type != MESA_SHADER_NONE;
1534
1535 if (binning_pass) {
1536 /* if we have streamout, use full VS in binning pass, as the
1537 * binning pass VS will have outputs on other than position/psize
1538 * stripped out:
1539 */
1540 if (vs->shader->stream_output.num_outputs == 0)
1541 vs = &builder->shaders[MESA_SHADER_VERTEX]->variants[1];
1542 fs = &dummy_variant;
1543 }
1544
1545 tu6_emit_vs_config(cs, builder->shaders[MESA_SHADER_VERTEX], vs);
1546 tu6_emit_hs_config(cs, builder->shaders[MESA_SHADER_TESS_CTRL], hs);
1547 tu6_emit_ds_config(cs, builder->shaders[MESA_SHADER_TESS_EVAL], ds);
1548 tu6_emit_gs_config(cs, builder->shaders[MESA_SHADER_GEOMETRY], gs);
1549 tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
1550
1551 tu6_emit_vs_system_values(cs, vs, gs);
1552 tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
1553 tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
1554 tu6_emit_fs_inputs(cs, fs);
1555 tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
1556
1557 tu6_emit_shader_object(cs, MESA_SHADER_VERTEX, vs, binary_bo,
1558 binning_pass ? builder->binning_vs_offset : builder->shader_offsets[MESA_SHADER_VERTEX]);
1559 if (has_gs)
1560 tu6_emit_shader_object(cs, MESA_SHADER_GEOMETRY, gs, binary_bo,
1561 builder->shader_offsets[MESA_SHADER_GEOMETRY]);
1562 tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
1563 builder->shader_offsets[MESA_SHADER_FRAGMENT]);
1564
1565 tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
1566 if (has_gs) {
1567 tu6_emit_immediates(cs, gs, CP_LOAD_STATE6_GEOM, SB6_GS_SHADER);
1568 tu6_emit_geometry_consts(cs, vs, gs);
1569 }
1570 if (!binning_pass)
1571 tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
1572 }
1573
1574 static void
1575 tu6_emit_vertex_input(struct tu_cs *cs,
1576 const struct ir3_shader_variant *vs,
1577 const VkPipelineVertexInputStateCreateInfo *info,
1578 uint8_t bindings[MAX_VERTEX_ATTRIBS],
1579 uint32_t *count)
1580 {
1581 uint32_t vfd_fetch_idx = 0;
1582 uint32_t vfd_decode_idx = 0;
1583 uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
1584
1585 for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
1586 const VkVertexInputBindingDescription *binding =
1587 &info->pVertexBindingDescriptions[i];
1588
1589 tu_cs_emit_regs(cs,
1590 A6XX_VFD_FETCH_STRIDE(vfd_fetch_idx, binding->stride));
1591
1592 if (binding->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE)
1593 binding_instanced |= 1 << binding->binding;
1594
1595 bindings[vfd_fetch_idx] = binding->binding;
1596 vfd_fetch_idx++;
1597 }
1598
1599 /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
1600
1601 for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
1602 const VkVertexInputAttributeDescription *attr =
1603 &info->pVertexAttributeDescriptions[i];
1604 uint32_t binding_idx, input_idx;
1605
1606 for (binding_idx = 0; binding_idx < vfd_fetch_idx; binding_idx++) {
1607 if (bindings[binding_idx] == attr->binding)
1608 break;
1609 }
1610 assert(binding_idx < vfd_fetch_idx);
1611
1612 for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
1613 if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
1614 break;
1615 }
1616
1617 /* attribute not used, skip it */
1618 if (input_idx == vs->inputs_count)
1619 continue;
1620
1621 const struct tu_native_format format = tu6_format_vtx(attr->format);
1622 tu_cs_emit_regs(cs,
1623 A6XX_VFD_DECODE_INSTR(vfd_decode_idx,
1624 .idx = binding_idx,
1625 .offset = attr->offset,
1626 .instanced = binding_instanced & (1 << attr->binding),
1627 .format = format.fmt,
1628 .swap = format.swap,
1629 .unk30 = 1,
1630 ._float = !vk_format_is_int(attr->format)),
1631 A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
1632
1633 tu_cs_emit_regs(cs,
1634 A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
1635 .writemask = vs->inputs[input_idx].compmask,
1636 .regid = vs->inputs[input_idx].regid));
1637
1638 vfd_decode_idx++;
1639 }
1640
1641 tu_cs_emit_regs(cs,
1642 A6XX_VFD_CONTROL_0(
1643 .fetch_cnt = vfd_fetch_idx,
1644 .decode_cnt = vfd_decode_idx));
1645
1646 *count = vfd_fetch_idx;
1647 }
1648
1649 static uint32_t
1650 tu6_guardband_adj(uint32_t v)
1651 {
1652 if (v > 256)
1653 return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
1654 else
1655 return 511;
1656 }
1657
1658 void
1659 tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
1660 {
1661 float offsets[3];
1662 float scales[3];
1663 scales[0] = viewport->width / 2.0f;
1664 scales[1] = viewport->height / 2.0f;
1665 scales[2] = viewport->maxDepth - viewport->minDepth;
1666 offsets[0] = viewport->x + scales[0];
1667 offsets[1] = viewport->y + scales[1];
1668 offsets[2] = viewport->minDepth;
1669
1670 VkOffset2D min;
1671 VkOffset2D max;
1672 min.x = (int32_t) viewport->x;
1673 max.x = (int32_t) ceilf(viewport->x + viewport->width);
1674 if (viewport->height >= 0.0f) {
1675 min.y = (int32_t) viewport->y;
1676 max.y = (int32_t) ceilf(viewport->y + viewport->height);
1677 } else {
1678 min.y = (int32_t)(viewport->y + viewport->height);
1679 max.y = (int32_t) ceilf(viewport->y);
1680 }
1681 /* the spec allows viewport->height to be 0.0f */
1682 if (min.y == max.y)
1683 max.y++;
1684 assert(min.x >= 0 && min.x < max.x);
1685 assert(min.y >= 0 && min.y < max.y);
1686
1687 VkExtent2D guardband_adj;
1688 guardband_adj.width = tu6_guardband_adj(max.x - min.x);
1689 guardband_adj.height = tu6_guardband_adj(max.y - min.y);
1690
1691 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
1692 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
1693 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
1694 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
1695 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
1696 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
1697 tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
1698
1699 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
1700 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
1701 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
1702 tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
1703 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
1704
1705 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
1706 tu_cs_emit(cs,
1707 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband_adj.width) |
1708 A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband_adj.height));
1709
1710 float z_clamp_min = MIN2(viewport->minDepth, viewport->maxDepth);
1711 float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
1712
1713 tu_cs_emit_regs(cs,
1714 A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
1715 A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
1716
1717 tu_cs_emit_regs(cs,
1718 A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
1719 A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
1720 }
1721
1722 void
1723 tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
1724 {
1725 const VkOffset2D min = scissor->offset;
1726 const VkOffset2D max = {
1727 scissor->offset.x + scissor->extent.width,
1728 scissor->offset.y + scissor->extent.height,
1729 };
1730
1731 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
1732 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
1733 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
1734 tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
1735 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
1736 }
1737
1738 void
1739 tu6_emit_sample_locations(struct tu_cs *cs, const VkSampleLocationsInfoEXT *samp_loc)
1740 {
1741 if (!samp_loc) {
1742 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
1743 tu_cs_emit(cs, 0);
1744
1745 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
1746 tu_cs_emit(cs, 0);
1747
1748 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
1749 tu_cs_emit(cs, 0);
1750 return;
1751 }
1752
1753 assert(samp_loc->sampleLocationsPerPixel == samp_loc->sampleLocationsCount);
1754 assert(samp_loc->sampleLocationGridSize.width == 1);
1755 assert(samp_loc->sampleLocationGridSize.height == 1);
1756
1757 uint32_t sample_config =
1758 A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE;
1759 uint32_t sample_locations = 0;
1760 for (uint32_t i = 0; i < samp_loc->sampleLocationsCount; i++) {
1761 sample_locations |=
1762 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(samp_loc->pSampleLocations[i].x) |
1763 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(samp_loc->pSampleLocations[i].y)) << i*8;
1764 }
1765
1766 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 2);
1767 tu_cs_emit(cs, sample_config);
1768 tu_cs_emit(cs, sample_locations);
1769
1770 tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 2);
1771 tu_cs_emit(cs, sample_config);
1772 tu_cs_emit(cs, sample_locations);
1773
1774 tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 2);
1775 tu_cs_emit(cs, sample_config);
1776 tu_cs_emit(cs, sample_locations);
1777 }
1778
1779 static void
1780 tu6_emit_gras_unknowns(struct tu_cs *cs)
1781 {
1782 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
1783 tu_cs_emit(cs, 0x0);
1784 }
1785
1786 static void
1787 tu6_emit_point_size(struct tu_cs *cs)
1788 {
1789 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POINT_MINMAX, 2);
1790 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_MINMAX_MIN(1.0f / 16.0f) |
1791 A6XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
1792 tu_cs_emit(cs, A6XX_GRAS_SU_POINT_SIZE(1.0f).value);
1793 }
1794
1795 static uint32_t
1796 tu6_gras_su_cntl(const VkPipelineRasterizationStateCreateInfo *rast_info,
1797 VkSampleCountFlagBits samples)
1798 {
1799 uint32_t gras_su_cntl = 0;
1800
1801 if (rast_info->cullMode & VK_CULL_MODE_FRONT_BIT)
1802 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
1803 if (rast_info->cullMode & VK_CULL_MODE_BACK_BIT)
1804 gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
1805
1806 if (rast_info->frontFace == VK_FRONT_FACE_CLOCKWISE)
1807 gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
1808
1809 /* don't set A6XX_GRAS_SU_CNTL_LINEHALFWIDTH */
1810
1811 if (rast_info->depthBiasEnable)
1812 gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
1813
1814 if (samples > VK_SAMPLE_COUNT_1_BIT)
1815 gras_su_cntl |= A6XX_GRAS_SU_CNTL_MSAA_ENABLE;
1816
1817 return gras_su_cntl;
1818 }
1819
1820 void
1821 tu6_emit_gras_su_cntl(struct tu_cs *cs,
1822 uint32_t gras_su_cntl,
1823 float line_width)
1824 {
1825 assert((gras_su_cntl & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK) == 0);
1826 gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(line_width / 2.0f);
1827
1828 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_CNTL, 1);
1829 tu_cs_emit(cs, gras_su_cntl);
1830 }
1831
1832 void
1833 tu6_emit_depth_bias(struct tu_cs *cs,
1834 float constant_factor,
1835 float clamp,
1836 float slope_factor)
1837 {
1838 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
1839 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_SCALE(slope_factor).value);
1840 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET(constant_factor).value);
1841 tu_cs_emit(cs, A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(clamp).value);
1842 }
1843
1844 static void
1845 tu6_emit_alpha_control_disable(struct tu_cs *cs)
1846 {
1847 tu_cs_emit_pkt4(cs, REG_A6XX_RB_ALPHA_CONTROL, 1);
1848 tu_cs_emit(cs, 0);
1849 }
1850
1851 static void
1852 tu6_emit_depth_control(struct tu_cs *cs,
1853 const VkPipelineDepthStencilStateCreateInfo *ds_info,
1854 const VkPipelineRasterizationStateCreateInfo *rast_info)
1855 {
1856 assert(!ds_info->depthBoundsTestEnable);
1857
1858 uint32_t rb_depth_cntl = 0;
1859 if (ds_info->depthTestEnable) {
1860 rb_depth_cntl |=
1861 A6XX_RB_DEPTH_CNTL_Z_ENABLE |
1862 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1863 A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
1864
1865 if (rast_info->depthClampEnable)
1866 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
1867
1868 if (ds_info->depthWriteEnable)
1869 rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
1870 }
1871
1872 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
1873 tu_cs_emit(cs, rb_depth_cntl);
1874 }
1875
1876 static void
1877 tu6_emit_stencil_control(struct tu_cs *cs,
1878 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1879 {
1880 uint32_t rb_stencil_control = 0;
1881 if (ds_info->stencilTestEnable) {
1882 const VkStencilOpState *front = &ds_info->front;
1883 const VkStencilOpState *back = &ds_info->back;
1884 rb_stencil_control |=
1885 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
1886 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
1887 A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
1888 A6XX_RB_STENCIL_CONTROL_FUNC(tu6_compare_func(front->compareOp)) |
1889 A6XX_RB_STENCIL_CONTROL_FAIL(tu6_stencil_op(front->failOp)) |
1890 A6XX_RB_STENCIL_CONTROL_ZPASS(tu6_stencil_op(front->passOp)) |
1891 A6XX_RB_STENCIL_CONTROL_ZFAIL(tu6_stencil_op(front->depthFailOp)) |
1892 A6XX_RB_STENCIL_CONTROL_FUNC_BF(tu6_compare_func(back->compareOp)) |
1893 A6XX_RB_STENCIL_CONTROL_FAIL_BF(tu6_stencil_op(back->failOp)) |
1894 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(tu6_stencil_op(back->passOp)) |
1895 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(tu6_stencil_op(back->depthFailOp));
1896 }
1897
1898 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_CONTROL, 1);
1899 tu_cs_emit(cs, rb_stencil_control);
1900 }
1901
1902 void
1903 tu6_emit_stencil_compare_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1904 {
1905 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILMASK, 1);
1906 tu_cs_emit(
1907 cs, A6XX_RB_STENCILMASK_MASK(front) | A6XX_RB_STENCILMASK_BFMASK(back));
1908 }
1909
1910 void
1911 tu6_emit_stencil_write_mask(struct tu_cs *cs, uint32_t front, uint32_t back)
1912 {
1913 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILWRMASK, 1);
1914 tu_cs_emit(cs, A6XX_RB_STENCILWRMASK_WRMASK(front) |
1915 A6XX_RB_STENCILWRMASK_BFWRMASK(back));
1916 }
1917
1918 void
1919 tu6_emit_stencil_reference(struct tu_cs *cs, uint32_t front, uint32_t back)
1920 {
1921 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCILREF, 1);
1922 tu_cs_emit(cs,
1923 A6XX_RB_STENCILREF_REF(front) | A6XX_RB_STENCILREF_BFREF(back));
1924 }
1925
1926 static uint32_t
1927 tu6_rb_mrt_blend_control(const VkPipelineColorBlendAttachmentState *att,
1928 bool has_alpha)
1929 {
1930 const enum a3xx_rb_blend_opcode color_op = tu6_blend_op(att->colorBlendOp);
1931 const enum adreno_rb_blend_factor src_color_factor = tu6_blend_factor(
1932 has_alpha ? att->srcColorBlendFactor
1933 : tu_blend_factor_no_dst_alpha(att->srcColorBlendFactor));
1934 const enum adreno_rb_blend_factor dst_color_factor = tu6_blend_factor(
1935 has_alpha ? att->dstColorBlendFactor
1936 : tu_blend_factor_no_dst_alpha(att->dstColorBlendFactor));
1937 const enum a3xx_rb_blend_opcode alpha_op = tu6_blend_op(att->alphaBlendOp);
1938 const enum adreno_rb_blend_factor src_alpha_factor =
1939 tu6_blend_factor(att->srcAlphaBlendFactor);
1940 const enum adreno_rb_blend_factor dst_alpha_factor =
1941 tu6_blend_factor(att->dstAlphaBlendFactor);
1942
1943 return A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(src_color_factor) |
1944 A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(color_op) |
1945 A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(dst_color_factor) |
1946 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(src_alpha_factor) |
1947 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(alpha_op) |
1948 A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(dst_alpha_factor);
1949 }
1950
1951 static uint32_t
1952 tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
1953 uint32_t rb_mrt_control_rop,
1954 bool is_int,
1955 bool has_alpha)
1956 {
1957 uint32_t rb_mrt_control =
1958 A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(att->colorWriteMask);
1959
1960 /* ignore blending and logic op for integer attachments */
1961 if (is_int) {
1962 rb_mrt_control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
1963 return rb_mrt_control;
1964 }
1965
1966 rb_mrt_control |= rb_mrt_control_rop;
1967
1968 if (att->blendEnable) {
1969 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND;
1970
1971 if (has_alpha)
1972 rb_mrt_control |= A6XX_RB_MRT_CONTROL_BLEND2;
1973 }
1974
1975 return rb_mrt_control;
1976 }
1977
1978 static void
1979 tu6_emit_rb_mrt_controls(struct tu_cs *cs,
1980 const VkPipelineColorBlendStateCreateInfo *blend_info,
1981 const VkFormat attachment_formats[MAX_RTS],
1982 uint32_t *blend_enable_mask)
1983 {
1984 *blend_enable_mask = 0;
1985
1986 bool rop_reads_dst = false;
1987 uint32_t rb_mrt_control_rop = 0;
1988 if (blend_info->logicOpEnable) {
1989 rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
1990 rb_mrt_control_rop =
1991 A6XX_RB_MRT_CONTROL_ROP_ENABLE |
1992 A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
1993 }
1994
1995 for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
1996 const VkPipelineColorBlendAttachmentState *att =
1997 &blend_info->pAttachments[i];
1998 const VkFormat format = attachment_formats[i];
1999
2000 uint32_t rb_mrt_control = 0;
2001 uint32_t rb_mrt_blend_control = 0;
2002 if (format != VK_FORMAT_UNDEFINED) {
2003 const bool is_int = vk_format_is_int(format);
2004 const bool has_alpha = vk_format_has_alpha(format);
2005
2006 rb_mrt_control =
2007 tu6_rb_mrt_control(att, rb_mrt_control_rop, is_int, has_alpha);
2008 rb_mrt_blend_control = tu6_rb_mrt_blend_control(att, has_alpha);
2009
2010 if (att->blendEnable || rop_reads_dst)
2011 *blend_enable_mask |= 1 << i;
2012 }
2013
2014 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
2015 tu_cs_emit(cs, rb_mrt_control);
2016 tu_cs_emit(cs, rb_mrt_blend_control);
2017 }
2018 }
2019
2020 static void
2021 tu6_emit_blend_control(struct tu_cs *cs,
2022 uint32_t blend_enable_mask,
2023 const VkPipelineMultisampleStateCreateInfo *msaa_info)
2024 {
2025 assert(!msaa_info->alphaToOneEnable);
2026
2027 uint32_t sp_blend_cntl = A6XX_SP_BLEND_CNTL_UNK8;
2028 if (blend_enable_mask)
2029 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ENABLED;
2030 if (msaa_info->alphaToCoverageEnable)
2031 sp_blend_cntl |= A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE;
2032
2033 const uint32_t sample_mask =
2034 msaa_info->pSampleMask ? *msaa_info->pSampleMask
2035 : ((1 << msaa_info->rasterizationSamples) - 1);
2036
2037 /* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
2038 uint32_t rb_blend_cntl =
2039 A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) |
2040 A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND |
2041 A6XX_RB_BLEND_CNTL_SAMPLE_MASK(sample_mask);
2042 if (msaa_info->alphaToCoverageEnable)
2043 rb_blend_cntl |= A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE;
2044
2045 tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
2046 tu_cs_emit(cs, sp_blend_cntl);
2047
2048 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
2049 tu_cs_emit(cs, rb_blend_cntl);
2050 }
2051
2052 void
2053 tu6_emit_blend_constants(struct tu_cs *cs, const float constants[4])
2054 {
2055 tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
2056 tu_cs_emit_array(cs, (const uint32_t *) constants, 4);
2057 }
2058
2059 static VkResult
2060 tu_pipeline_create(struct tu_device *dev,
2061 struct tu_pipeline_layout *layout,
2062 bool compute,
2063 const VkAllocationCallbacks *pAllocator,
2064 struct tu_pipeline **out_pipeline)
2065 {
2066 struct tu_pipeline *pipeline =
2067 vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
2068 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2069 if (!pipeline)
2070 return VK_ERROR_OUT_OF_HOST_MEMORY;
2071
2072 tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
2073
2074 /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
2075 * that LOAD_STATE can potentially take up a large amount of space so we
2076 * calculate its size explicitly.
2077 */
2078 unsigned load_state_size = tu6_load_state_size(layout, compute);
2079 VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
2080 if (result != VK_SUCCESS) {
2081 vk_free2(&dev->alloc, pAllocator, pipeline);
2082 return result;
2083 }
2084
2085 *out_pipeline = pipeline;
2086
2087 return VK_SUCCESS;
2088 }
2089
2090 static VkResult
2091 tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
2092 {
2093 const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
2094 NULL
2095 };
2096 for (uint32_t i = 0; i < builder->create_info->stageCount; i++) {
2097 gl_shader_stage stage =
2098 tu_shader_stage(builder->create_info->pStages[i].stage);
2099 stage_infos[stage] = &builder->create_info->pStages[i];
2100 }
2101
2102 struct tu_shader_compile_options options;
2103 tu_shader_compile_options_init(&options, builder->create_info);
2104
2105 /* compile shaders in reverse order */
2106 struct tu_shader *next_stage_shader = NULL;
2107 for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
2108 stage > MESA_SHADER_NONE; stage--) {
2109 const VkPipelineShaderStageCreateInfo *stage_info = stage_infos[stage];
2110 if (!stage_info)
2111 continue;
2112
2113 struct tu_shader *shader =
2114 tu_shader_create(builder->device, stage, stage_info, builder->layout,
2115 builder->alloc);
2116 if (!shader)
2117 return VK_ERROR_OUT_OF_HOST_MEMORY;
2118
2119 VkResult result =
2120 tu_shader_compile(builder->device, shader, next_stage_shader,
2121 &options, builder->alloc);
2122 if (result != VK_SUCCESS)
2123 return result;
2124
2125 builder->shaders[stage] = shader;
2126 builder->shader_offsets[stage] = builder->shader_total_size;
2127 builder->shader_total_size +=
2128 sizeof(uint32_t) * shader->variants[0].info.sizedwords;
2129
2130 next_stage_shader = shader;
2131 }
2132
2133 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2134 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2135 const struct ir3_shader_variant *variant;
2136
2137 if (vs->ir3_shader.stream_output.num_outputs)
2138 variant = &vs->variants[0];
2139 else
2140 variant = &vs->variants[1];
2141
2142 builder->binning_vs_offset = builder->shader_total_size;
2143 builder->shader_total_size +=
2144 sizeof(uint32_t) * variant->info.sizedwords;
2145 }
2146
2147 return VK_SUCCESS;
2148 }
2149
2150 static VkResult
2151 tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
2152 struct tu_pipeline *pipeline)
2153 {
2154 struct tu_bo *bo = &pipeline->program.binary_bo;
2155
2156 VkResult result =
2157 tu_bo_init_new(builder->device, bo, builder->shader_total_size);
2158 if (result != VK_SUCCESS)
2159 return result;
2160
2161 result = tu_bo_map(builder->device, bo);
2162 if (result != VK_SUCCESS)
2163 return result;
2164
2165 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2166 const struct tu_shader *shader = builder->shaders[i];
2167 if (!shader)
2168 continue;
2169
2170 memcpy(bo->map + builder->shader_offsets[i], shader->binary,
2171 sizeof(uint32_t) * shader->variants[0].info.sizedwords);
2172 }
2173
2174 if (builder->shaders[MESA_SHADER_VERTEX]->has_binning_pass) {
2175 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2176 const struct ir3_shader_variant *variant;
2177 void *bin;
2178
2179 if (vs->ir3_shader.stream_output.num_outputs) {
2180 variant = &vs->variants[0];
2181 bin = vs->binary;
2182 } else {
2183 variant = &vs->variants[1];
2184 bin = vs->binning_binary;
2185 }
2186
2187 memcpy(bo->map + builder->binning_vs_offset, bin,
2188 sizeof(uint32_t) * variant->info.sizedwords);
2189 }
2190
2191 return VK_SUCCESS;
2192 }
2193
2194 static void
2195 tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
2196 struct tu_pipeline *pipeline)
2197 {
2198 const VkPipelineDynamicStateCreateInfo *dynamic_info =
2199 builder->create_info->pDynamicState;
2200
2201 if (!dynamic_info)
2202 return;
2203
2204 for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
2205 pipeline->dynamic_state.mask |=
2206 tu_dynamic_state_bit(dynamic_info->pDynamicStates[i]);
2207 }
2208 }
2209
2210 static void
2211 tu_pipeline_set_linkage(struct tu_program_descriptor_linkage *link,
2212 struct tu_shader *shader,
2213 struct ir3_shader_variant *v)
2214 {
2215 link->ubo_state = v->shader->ubo_state;
2216 link->const_state = v->shader->const_state;
2217 link->constlen = v->constlen;
2218 link->push_consts = shader->push_consts;
2219 }
2220
2221 static void
2222 tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
2223 struct tu_pipeline *pipeline)
2224 {
2225 struct tu_cs prog_cs;
2226 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2227 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
2228 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2229
2230 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2231 tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
2232 pipeline->program.binning_state_ib =
2233 tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2234
2235 VkShaderStageFlags stages = 0;
2236 for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
2237 stages |= builder->create_info->pStages[i].stage;
2238 }
2239 pipeline->active_stages = stages;
2240
2241 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
2242 if (!builder->shaders[i])
2243 continue;
2244
2245 tu_pipeline_set_linkage(&pipeline->program.link[i],
2246 builder->shaders[i],
2247 &builder->shaders[i]->variants[0]);
2248 }
2249
2250 if (builder->shaders[MESA_SHADER_FRAGMENT]) {
2251 memcpy(pipeline->program.input_attachment_idx,
2252 builder->shaders[MESA_SHADER_FRAGMENT]->attachment_idx,
2253 sizeof(pipeline->program.input_attachment_idx));
2254 }
2255 }
2256
2257 static void
2258 tu_pipeline_builder_parse_vertex_input(struct tu_pipeline_builder *builder,
2259 struct tu_pipeline *pipeline)
2260 {
2261 const VkPipelineVertexInputStateCreateInfo *vi_info =
2262 builder->create_info->pVertexInputState;
2263 const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
2264
2265 struct tu_cs vi_cs;
2266 tu_cs_begin_sub_stream(&pipeline->cs,
2267 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2268 tu6_emit_vertex_input(&vi_cs, &vs->variants[0], vi_info,
2269 pipeline->vi.bindings, &pipeline->vi.count);
2270 pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2271
2272 if (vs->has_binning_pass) {
2273 tu_cs_begin_sub_stream(&pipeline->cs,
2274 MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
2275 tu6_emit_vertex_input(
2276 &vi_cs, &vs->variants[1], vi_info, pipeline->vi.binning_bindings,
2277 &pipeline->vi.binning_count);
2278 pipeline->vi.binning_state_ib =
2279 tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
2280 }
2281 }
2282
2283 static void
2284 tu_pipeline_builder_parse_input_assembly(struct tu_pipeline_builder *builder,
2285 struct tu_pipeline *pipeline)
2286 {
2287 const VkPipelineInputAssemblyStateCreateInfo *ia_info =
2288 builder->create_info->pInputAssemblyState;
2289
2290 pipeline->ia.primtype = tu6_primtype(ia_info->topology);
2291 pipeline->ia.primitive_restart = ia_info->primitiveRestartEnable;
2292 }
2293
2294 static void
2295 tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
2296 struct tu_pipeline *pipeline)
2297 {
2298 /* The spec says:
2299 *
2300 * pViewportState is a pointer to an instance of the
2301 * VkPipelineViewportStateCreateInfo structure, and is ignored if the
2302 * pipeline has rasterization disabled."
2303 *
2304 * We leave the relevant registers stale in that case.
2305 */
2306 if (builder->rasterizer_discard)
2307 return;
2308
2309 const VkPipelineViewportStateCreateInfo *vp_info =
2310 builder->create_info->pViewportState;
2311
2312 struct tu_cs vp_cs;
2313 tu_cs_begin_sub_stream(&pipeline->cs, 21, &vp_cs);
2314
2315 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_VIEWPORT)) {
2316 assert(vp_info->viewportCount == 1);
2317 tu6_emit_viewport(&vp_cs, vp_info->pViewports);
2318 }
2319
2320 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SCISSOR)) {
2321 assert(vp_info->scissorCount == 1);
2322 tu6_emit_scissor(&vp_cs, vp_info->pScissors);
2323 }
2324
2325 pipeline->vp.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vp_cs);
2326 }
2327
2328 static void
2329 tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
2330 struct tu_pipeline *pipeline)
2331 {
2332 const VkPipelineRasterizationStateCreateInfo *rast_info =
2333 builder->create_info->pRasterizationState;
2334
2335 assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
2336
2337 struct tu_cs rast_cs;
2338 tu_cs_begin_sub_stream(&pipeline->cs, 20, &rast_cs);
2339
2340
2341 tu_cs_emit_regs(&rast_cs,
2342 A6XX_GRAS_CL_CNTL(
2343 .znear_clip_disable = rast_info->depthClampEnable,
2344 .zfar_clip_disable = rast_info->depthClampEnable,
2345 .unk5 = rast_info->depthClampEnable,
2346 .zero_gb_scale_z = 1,
2347 .vp_clip_code_ignore = 1));
2348 /* move to hw ctx init? */
2349 tu6_emit_gras_unknowns(&rast_cs);
2350 tu6_emit_point_size(&rast_cs);
2351
2352 const uint32_t gras_su_cntl =
2353 tu6_gras_su_cntl(rast_info, builder->samples);
2354
2355 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_LINE_WIDTH))
2356 tu6_emit_gras_su_cntl(&rast_cs, gras_su_cntl, rast_info->lineWidth);
2357
2358 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_DEPTH_BIAS)) {
2359 tu6_emit_depth_bias(&rast_cs, rast_info->depthBiasConstantFactor,
2360 rast_info->depthBiasClamp,
2361 rast_info->depthBiasSlopeFactor);
2362 }
2363
2364 pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &rast_cs);
2365
2366 pipeline->rast.gras_su_cntl = gras_su_cntl;
2367 }
2368
2369 static void
2370 tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
2371 struct tu_pipeline *pipeline)
2372 {
2373 /* The spec says:
2374 *
2375 * pDepthStencilState is a pointer to an instance of the
2376 * VkPipelineDepthStencilStateCreateInfo structure, and is ignored if
2377 * the pipeline has rasterization disabled or if the subpass of the
2378 * render pass the pipeline is created against does not use a
2379 * depth/stencil attachment.
2380 *
2381 * Disable both depth and stencil tests if there is no ds attachment,
2382 * Disable depth test if ds attachment is S8_UINT, since S8_UINT defines
2383 * only the separate stencil attachment
2384 */
2385 static const VkPipelineDepthStencilStateCreateInfo dummy_ds_info;
2386 const VkPipelineDepthStencilStateCreateInfo *ds_info =
2387 builder->depth_attachment_format != VK_FORMAT_UNDEFINED
2388 ? builder->create_info->pDepthStencilState
2389 : &dummy_ds_info;
2390 const VkPipelineDepthStencilStateCreateInfo *ds_info_depth =
2391 builder->depth_attachment_format != VK_FORMAT_S8_UINT
2392 ? ds_info : &dummy_ds_info;
2393
2394 struct tu_cs ds_cs;
2395 tu_cs_begin_sub_stream(&pipeline->cs, 12, &ds_cs);
2396
2397 /* move to hw ctx init? */
2398 tu6_emit_alpha_control_disable(&ds_cs);
2399
2400 tu6_emit_depth_control(&ds_cs, ds_info_depth,
2401 builder->create_info->pRasterizationState);
2402 tu6_emit_stencil_control(&ds_cs, ds_info);
2403
2404 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_COMPARE_MASK)) {
2405 tu6_emit_stencil_compare_mask(&ds_cs, ds_info->front.compareMask,
2406 ds_info->back.compareMask);
2407 }
2408 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_WRITE_MASK)) {
2409 tu6_emit_stencil_write_mask(&ds_cs, ds_info->front.writeMask,
2410 ds_info->back.writeMask);
2411 }
2412 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_STENCIL_REFERENCE)) {
2413 tu6_emit_stencil_reference(&ds_cs, ds_info->front.reference,
2414 ds_info->back.reference);
2415 }
2416
2417 pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &ds_cs);
2418 }
2419
2420 static void
2421 tu_pipeline_builder_parse_multisample_and_color_blend(
2422 struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline)
2423 {
2424 /* The spec says:
2425 *
2426 * pMultisampleState is a pointer to an instance of the
2427 * VkPipelineMultisampleStateCreateInfo, and is ignored if the pipeline
2428 * has rasterization disabled.
2429 *
2430 * Also,
2431 *
2432 * pColorBlendState is a pointer to an instance of the
2433 * VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
2434 * pipeline has rasterization disabled or if the subpass of the render
2435 * pass the pipeline is created against does not use any color
2436 * attachments.
2437 *
2438 * We leave the relevant registers stale when rasterization is disabled.
2439 */
2440 if (builder->rasterizer_discard)
2441 return;
2442
2443 static const VkPipelineColorBlendStateCreateInfo dummy_blend_info;
2444 const VkPipelineMultisampleStateCreateInfo *msaa_info =
2445 builder->create_info->pMultisampleState;
2446 const VkPipelineColorBlendStateCreateInfo *blend_info =
2447 builder->use_color_attachments ? builder->create_info->pColorBlendState
2448 : &dummy_blend_info;
2449
2450 struct tu_cs blend_cs;
2451 tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 9, &blend_cs);
2452
2453 uint32_t blend_enable_mask;
2454 tu6_emit_rb_mrt_controls(&blend_cs, blend_info,
2455 builder->color_attachment_formats,
2456 &blend_enable_mask);
2457
2458 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_BLEND_CONSTANTS))
2459 tu6_emit_blend_constants(&blend_cs, blend_info->blendConstants);
2460
2461 if (!(pipeline->dynamic_state.mask & TU_DYNAMIC_SAMPLE_LOCATIONS)) {
2462 const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
2463 vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
2464 const VkSampleLocationsInfoEXT *samp_loc = NULL;
2465
2466 if (sample_locations && sample_locations->sampleLocationsEnable)
2467 samp_loc = &sample_locations->sampleLocationsInfo;
2468
2469 tu6_emit_sample_locations(&blend_cs, samp_loc);
2470 }
2471
2472 tu6_emit_blend_control(&blend_cs, blend_enable_mask, msaa_info);
2473
2474 pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &blend_cs);
2475 }
2476
2477 static void
2478 tu_pipeline_finish(struct tu_pipeline *pipeline,
2479 struct tu_device *dev,
2480 const VkAllocationCallbacks *alloc)
2481 {
2482 tu_cs_finish(&pipeline->cs);
2483
2484 if (pipeline->program.binary_bo.gem_handle)
2485 tu_bo_finish(dev, &pipeline->program.binary_bo);
2486 }
2487
2488 static VkResult
2489 tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
2490 struct tu_pipeline **pipeline)
2491 {
2492 VkResult result = tu_pipeline_create(builder->device, builder->layout,
2493 false, builder->alloc, pipeline);
2494 if (result != VK_SUCCESS)
2495 return result;
2496
2497 (*pipeline)->layout = builder->layout;
2498
2499 /* compile and upload shaders */
2500 result = tu_pipeline_builder_compile_shaders(builder);
2501 if (result == VK_SUCCESS)
2502 result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
2503 if (result != VK_SUCCESS) {
2504 tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
2505 vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
2506 *pipeline = VK_NULL_HANDLE;
2507
2508 return result;
2509 }
2510
2511 tu_pipeline_builder_parse_dynamic(builder, *pipeline);
2512 tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
2513 tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
2514 tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
2515 tu_pipeline_builder_parse_viewport(builder, *pipeline);
2516 tu_pipeline_builder_parse_rasterization(builder, *pipeline);
2517 tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
2518 tu_pipeline_builder_parse_multisample_and_color_blend(builder, *pipeline);
2519 tu6_emit_load_state(*pipeline, false);
2520
2521 /* we should have reserved enough space upfront such that the CS never
2522 * grows
2523 */
2524 assert((*pipeline)->cs.bo_count == 1);
2525
2526 return VK_SUCCESS;
2527 }
2528
2529 static void
2530 tu_pipeline_builder_finish(struct tu_pipeline_builder *builder)
2531 {
2532 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2533 if (!builder->shaders[i])
2534 continue;
2535 tu_shader_destroy(builder->device, builder->shaders[i], builder->alloc);
2536 }
2537 }
2538
2539 static void
2540 tu_pipeline_builder_init_graphics(
2541 struct tu_pipeline_builder *builder,
2542 struct tu_device *dev,
2543 struct tu_pipeline_cache *cache,
2544 const VkGraphicsPipelineCreateInfo *create_info,
2545 const VkAllocationCallbacks *alloc)
2546 {
2547 TU_FROM_HANDLE(tu_pipeline_layout, layout, create_info->layout);
2548
2549 *builder = (struct tu_pipeline_builder) {
2550 .device = dev,
2551 .cache = cache,
2552 .create_info = create_info,
2553 .alloc = alloc,
2554 .layout = layout,
2555 };
2556
2557 builder->rasterizer_discard =
2558 create_info->pRasterizationState->rasterizerDiscardEnable;
2559
2560 if (builder->rasterizer_discard) {
2561 builder->samples = VK_SAMPLE_COUNT_1_BIT;
2562 } else {
2563 builder->samples = create_info->pMultisampleState->rasterizationSamples;
2564
2565 const struct tu_render_pass *pass =
2566 tu_render_pass_from_handle(create_info->renderPass);
2567 const struct tu_subpass *subpass =
2568 &pass->subpasses[create_info->subpass];
2569
2570 const uint32_t a = subpass->depth_stencil_attachment.attachment;
2571 builder->depth_attachment_format = (a != VK_ATTACHMENT_UNUSED) ?
2572 pass->attachments[a].format : VK_FORMAT_UNDEFINED;
2573
2574 assert(subpass->color_count == 0 ||
2575 !create_info->pColorBlendState ||
2576 subpass->color_count == create_info->pColorBlendState->attachmentCount);
2577 builder->color_attachment_count = subpass->color_count;
2578 for (uint32_t i = 0; i < subpass->color_count; i++) {
2579 const uint32_t a = subpass->color_attachments[i].attachment;
2580 if (a == VK_ATTACHMENT_UNUSED)
2581 continue;
2582
2583 builder->color_attachment_formats[i] = pass->attachments[a].format;
2584 builder->use_color_attachments = true;
2585 }
2586 }
2587 }
2588
2589 static VkResult
2590 tu_graphics_pipeline_create(VkDevice device,
2591 VkPipelineCache pipelineCache,
2592 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2593 const VkAllocationCallbacks *pAllocator,
2594 VkPipeline *pPipeline)
2595 {
2596 TU_FROM_HANDLE(tu_device, dev, device);
2597 TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
2598
2599 struct tu_pipeline_builder builder;
2600 tu_pipeline_builder_init_graphics(&builder, dev, cache,
2601 pCreateInfo, pAllocator);
2602
2603 struct tu_pipeline *pipeline = NULL;
2604 VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
2605 tu_pipeline_builder_finish(&builder);
2606
2607 if (result == VK_SUCCESS)
2608 *pPipeline = tu_pipeline_to_handle(pipeline);
2609 else
2610 *pPipeline = VK_NULL_HANDLE;
2611
2612 return result;
2613 }
2614
2615 VkResult
2616 tu_CreateGraphicsPipelines(VkDevice device,
2617 VkPipelineCache pipelineCache,
2618 uint32_t count,
2619 const VkGraphicsPipelineCreateInfo *pCreateInfos,
2620 const VkAllocationCallbacks *pAllocator,
2621 VkPipeline *pPipelines)
2622 {
2623 VkResult final_result = VK_SUCCESS;
2624
2625 for (uint32_t i = 0; i < count; i++) {
2626 VkResult result = tu_graphics_pipeline_create(device, pipelineCache,
2627 &pCreateInfos[i], pAllocator,
2628 &pPipelines[i]);
2629
2630 if (result != VK_SUCCESS)
2631 final_result = result;
2632 }
2633
2634 return final_result;
2635 }
2636
2637 static void
2638 tu6_emit_compute_program(struct tu_cs *cs,
2639 struct tu_shader *shader,
2640 const struct tu_bo *binary_bo)
2641 {
2642 const struct ir3_shader_variant *v = &shader->variants[0];
2643
2644 tu6_emit_cs_config(cs, shader, v);
2645
2646 /* The compute program is the only one in the pipeline, so 0 offset. */
2647 tu6_emit_shader_object(cs, MESA_SHADER_COMPUTE, v, binary_bo, 0);
2648
2649 tu6_emit_immediates(cs, v, CP_LOAD_STATE6_FRAG, SB6_CS_SHADER);
2650 }
2651
2652 static VkResult
2653 tu_compute_upload_shader(VkDevice device,
2654 struct tu_pipeline *pipeline,
2655 struct tu_shader *shader)
2656 {
2657 TU_FROM_HANDLE(tu_device, dev, device);
2658 struct tu_bo *bo = &pipeline->program.binary_bo;
2659 struct ir3_shader_variant *v = &shader->variants[0];
2660
2661 uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
2662 VkResult result =
2663 tu_bo_init_new(dev, bo, shader_size);
2664 if (result != VK_SUCCESS)
2665 return result;
2666
2667 result = tu_bo_map(dev, bo);
2668 if (result != VK_SUCCESS)
2669 return result;
2670
2671 memcpy(bo->map, shader->binary, shader_size);
2672
2673 return VK_SUCCESS;
2674 }
2675
2676
2677 static VkResult
2678 tu_compute_pipeline_create(VkDevice device,
2679 VkPipelineCache _cache,
2680 const VkComputePipelineCreateInfo *pCreateInfo,
2681 const VkAllocationCallbacks *pAllocator,
2682 VkPipeline *pPipeline)
2683 {
2684 TU_FROM_HANDLE(tu_device, dev, device);
2685 TU_FROM_HANDLE(tu_pipeline_layout, layout, pCreateInfo->layout);
2686 const VkPipelineShaderStageCreateInfo *stage_info = &pCreateInfo->stage;
2687 VkResult result;
2688
2689 struct tu_pipeline *pipeline;
2690
2691 *pPipeline = VK_NULL_HANDLE;
2692
2693 result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
2694 if (result != VK_SUCCESS)
2695 return result;
2696
2697 pipeline->layout = layout;
2698
2699 struct tu_shader_compile_options options;
2700 tu_shader_compile_options_init(&options, NULL);
2701
2702 struct tu_shader *shader =
2703 tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
2704 if (!shader) {
2705 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2706 goto fail;
2707 }
2708
2709 result = tu_shader_compile(dev, shader, NULL, &options, pAllocator);
2710 if (result != VK_SUCCESS)
2711 goto fail;
2712
2713 struct ir3_shader_variant *v = &shader->variants[0];
2714
2715 tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
2716 shader, v);
2717
2718 result = tu_compute_upload_shader(device, pipeline, shader);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721
2722 for (int i = 0; i < 3; i++)
2723 pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
2724
2725 struct tu_cs prog_cs;
2726 tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
2727 tu6_emit_compute_program(&prog_cs, shader, &pipeline->program.binary_bo);
2728 pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
2729
2730 tu6_emit_load_state(pipeline, true);
2731
2732 *pPipeline = tu_pipeline_to_handle(pipeline);
2733 return VK_SUCCESS;
2734
2735 fail:
2736 if (shader)
2737 tu_shader_destroy(dev, shader, pAllocator);
2738
2739 tu_pipeline_finish(pipeline, dev, pAllocator);
2740 vk_free2(&dev->alloc, pAllocator, pipeline);
2741
2742 return result;
2743 }
2744
2745 VkResult
2746 tu_CreateComputePipelines(VkDevice device,
2747 VkPipelineCache pipelineCache,
2748 uint32_t count,
2749 const VkComputePipelineCreateInfo *pCreateInfos,
2750 const VkAllocationCallbacks *pAllocator,
2751 VkPipeline *pPipelines)
2752 {
2753 VkResult final_result = VK_SUCCESS;
2754
2755 for (uint32_t i = 0; i < count; i++) {
2756 VkResult result = tu_compute_pipeline_create(device, pipelineCache,
2757 &pCreateInfos[i],
2758 pAllocator, &pPipelines[i]);
2759 if (result != VK_SUCCESS)
2760 final_result = result;
2761 }
2762
2763 return final_result;
2764 }
2765
2766 void
2767 tu_DestroyPipeline(VkDevice _device,
2768 VkPipeline _pipeline,
2769 const VkAllocationCallbacks *pAllocator)
2770 {
2771 TU_FROM_HANDLE(tu_device, dev, _device);
2772 TU_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
2773
2774 if (!_pipeline)
2775 return;
2776
2777 tu_pipeline_finish(pipeline, dev, pAllocator);
2778 vk_free2(&dev->alloc, pAllocator, pipeline);
2779 }