src/nmutil/test/test_clz.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3
   4 from nmutil.clz import CLZ
   5 import unittest
   6 import math
   7 import random
   8
   9
  10 class CLZTestCase(unittest.TestCase):
  11     def run_tst(self, inputs, width=8):
  12
  13         m = Module()
  14
  15         m.submodules.dut = dut = CLZ(width)
  16         sig_in = Signal.like(dut.sig_in)
  17         count = Signal.like(dut.lz)
  18
  19
  20         m.d.comb += [
  21             dut.sig_in.eq(sig_in),
  22             count.eq(dut.lz)]
  23
  24         sim = Simulator(m)
  25
  26         def process():
  27             for i in inputs:
  28                 yield sig_in.eq(i)
  29                 yield Delay(1e-6)
  30         sim.add_process(process)
  31         with sim.write_vcd("clz.vcd", "clz.gtkw", traces=[
  32                 sig_in, count]):
  33             sim.run()
  34
  35     def test_selected(self):
  36         inputs = [0, 15, 10, 127]
  37         self.run_tst(iter(inputs), width=8)
  38
  39     def test_non_power_2(self):
  40         inputs = [0, 128, 512]
  41         self.run_tst(iter(inputs), width=11)
  42
  43
  44 if __name__ == "__main__":
  45     unittest.main()