NEWS.txt

   1 Release Notes Version 0.0.3 16 May 2021
   2 -------------
   3
   4 Version 0.0.3 adds preliminary pseudo-code and support for some basic
   5 scalar IEEE754 FP operations.  Additional Pseudo-code from the v3.0B
   6 Specification (specifically Section A.3 Book I p782) has been extracted
   7 and cleaned up to become executable through compilation into python.
   8 This provides the implementation of "fcfids".
   9
  10 Additionally. a RADIX MMU implementation has been added plus associated
  11 unit tests, and Load/Store Exceptions are underway: misaligned exceptions
  12 are already generated; RADIX MMU exceptions will be added in a next
  13 release.
  14
  15
  16 Release Notes Version 0.0.1 23 April 2021
  17 -------------
  18
  19 The Libre-SOC Project is pleased to announce the first release of an
  20 OpenPOWER ISA co-simulation test suite with its own built-in OpenPOWER
  21 ISA Simulator.
  22
  23 https://git.libre-soc.org/?p=openpower-isa.git
  24
  25 Available also on pypi:
  26 https://pypi.org/project/libresoc-openpower-isa/
  27
  28 Containing thousands of unit tests for OpenPOWER v3.0 its purpose is
  29 to provide cross-emulator cross-simulator cross-HDL inter-verification,
  30 and to enable and accelerate research and collaboration in OpenPOWER.
  31
  32 Currently included in co-simulation is:
  33
  34 * an internal OpenPOWER simulator written in python (ISACaller)
  35 * a means to fire up qemu bare-metal programs using pygdbmi
  36 * single-stepping followed by extraction of registers and memory
  37 * comparison and reporting on any discrepancies
  38
  39 in this fashion, obscure previously undiscovered bugs in qemu have been
  40 found and reported.
  41
  42 Libre-SOC's HDL (written in nmigen) also runs the exact same unit
  43 tests, comparing through the same single-stepping, against ISACaller.
  44 Having cross-verified ISACaller against qemu, running the same unit tests
  45 against Libre-SOC HDL ensures that Libre-SOC's hardware implementation
  46 behaves the same (minus the qemu bug).
  47
  48 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD
  49
  50 The project provides a useful bootstrap methodology for testing extensions
  51 of the OpenPOWER ISA: currently, SVP64 (a Cray-style variable-length
  52 Vector Extension to OpenPOWER) is currently being developed in the
  53 simulator and in LibreSOC HDL.
  54
  55 Future plans are to add Microwatt and power-gem5 into the mix, as well
  56 as ssh out to remote POWER9/10 compatible hardware, and also running
  57 native gdb (obviously, only on actual OpenPOWER compatible hardware).
  58 It would also be nice to receive patches adding IBM's proprietary
  59 OpenPOWER emulator as well.
  60
  61 With power-gem5 having the exact same remote machine-driven gdb interface
  62 as qemu, this one should be easy. Microwatt will require external access
  63 via its DMI interface on a simulator of some kind (verilator, cocotb)
  64 in order to read memory and registers.
  65
  66 The python-based simulator, ineptly named ISACaller, is noteworthy in
  67 that not one single line of hand-generated python simulator code was
  68 written, neither for the OpenPOWER ISA decoding nor for the emulated
  69 execution of actual instructions.
  70
  71 Instead, information was extracted into human-readable machine-readable
  72 CSV, text, and markdown files, and a compiler (language translator)
  73 written. python-ply afficionados will love that the compiler was based
  74 on GardenSnake.py
  75
  76 With the pseudocode and ISA Opcode fields having been extracted from the
  77 OpenPOWER v3.0B ISA Manual, this means that the *actual specification
  78 itself* (having been compiled to python) is what was tested by the
  79 several thousand unit tests.
  80
  81 This gets particularly interesting when researching new extensions
  82 to OpenPOWER, because the very first thing required is to add the
  83 opcodes, fields, forms and pseudocode, for ISACaller to be able to
  84 use it.  This should make adding a proposed extension to the actual ISA
  85 considerably smoother.
  86
  87 With the v3.0B pseusocode now proven as executable, there is no reason
  88 why in future additional compilers (c, c++) or Formal Correctness Proofs
  89 should not be at least partly auto-generated.  More details here, in
  90 the walkthrough:
  91
  92 https://libre-soc.org/3d_gpu/architecture/decoder/
  93
  94 Also potentially of huge value would be the addition of openocd support
  95 via JTAG / DMI for OpenPOWER, then using JTAG it would be possible
  96 not only to run the exact same unit tests against FPGAs and ASICSs, it
  97 would be possible to run the same unit tests through litex "jtagremote",
  98 and against cocotb as well.  Hints on that, here:
  99
 100 https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;h=05fe4879470c3fd3373f2ed68be21f740b46367d;hb=964a6afdf08fd924b75603b2d7bd3a31b9815561#l63
 101
 102 https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;h=8cddb39c6d2a5509bde635e2987055264c423b84;hb=1d20454df8ccfb8ccdd8b32d7138f38553c23f1d#l480
 103
 104 Note that the firmware_upload.py program speaks  the exact same jtagremote
 105 bitbanging protocol that is in upstream litex (and openocd).  A patch
 106 is available to litex which enables it for litex sim:
 107
 108 https://ftp.libre-soc.org/litex-sim-jtagremote.patch
 109
 110 Libre-SOC therefore cordially invites other parties interested
 111 in OpenPOWER to collaborate in this weird and wonderful
 112 cross-hardware-software project, which throws FPGAs, simulators,
 113 emulators, language translators and hardware into a melting pot and
 114 lights the blue touchpaper.
 115
 116 Questions and contributions welcomed at the libre-soc-dev mailing list,
 117 and at #libre-soc on freenode.
 118
 119 This work is sponsored by NLnet under its Privacy and Enhanced Trust
 120 Programme. http://nlnet.nl
 121