openpower/isa/pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Special Registers Altered:
  24
  25     None
  26
  27 # Load Byte and Zero with Post-Update Indexed
  28
  29 X-Form
  30
  31 * lbzupx RT,RA,RB
  32
  33 Pseudo-code:
  34
  35     EA <- (RA)
  36     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  37     RA <- (RA) + (RB)
  38
  39 Special Registers Altered:
  40
  41     None
  42
  43 # Load Halfword and Zero with Post-Update
  44
  45 D-Form
  46
  47 * lhzup RT,D(RA)
  48
  49 Pseudo-code:
  50
  51     EA <- (RA)
  52     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  53     RA <- (RA) + EXTS(D)
  54
  55 Special Registers Altered:
  56
  57     None
  58
  59 # Load Halfword and Zero with Post-Update Indexed
  60
  61 X-Form
  62
  63 * lhzupx RT,RA,RB
  64
  65 Pseudo-code:
  66
  67     EA <- (RA)
  68     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  69     RA <- (RA) + (RB)
  70
  71 Special Registers Altered:
  72
  73     None
  74
  75 # Load Halfword Algebraic with Post-Update
  76
  77 D-Form
  78
  79 * lhaup RT,D(RA)
  80
  81 Pseudo-code:
  82
  83     EA <- (RA)
  84     RT <- EXTS(MEM(EA, 2))
  85     RA <- (RA) + EXTS(D)
  86
  87 Special Registers Altered:
  88
  89     None
  90
  91 # Load Halfword Algebraic with Post-Update Indexed
  92
  93 X-Form
  94
  95 * lhaupx RT,RA,RB
  96
  97 Pseudo-code:
  98
  99     EA <- (RA)
 100     RT <- EXTS(MEM(EA, 2))
 101     RA <- (RA) + (RB)
 102
 103 Special Registers Altered:
 104
 105     None
 106
 107 # Load Word and Zero with Post-Update
 108
 109 D-Form
 110
 111 * lwzup RT,D(RA)
 112
 113 Pseudo-code:
 114
 115     EA <- (RA)
 116     RT <- [0]*32 || MEM(EA, 4)
 117     RA <- (RA) + EXTS(D)
 118
 119 Special Registers Altered:
 120
 121     None
 122
 123 # Load Word and Zero with Post-Update Indexed
 124
 125 X-Form
 126
 127 * lwzupx RT,RA,RB
 128
 129 Pseudo-code:
 130
 131     EA <- (RA)
 132     RT <- [0] * 32 || MEM(EA, 4)
 133     RA <- (RA) + (RB)
 134
 135 Special Registers Altered:
 136
 137     None
 138
 139 # Load Word Algebraic with Post-Update Indexed
 140
 141 X-Form
 142
 143 * lwaupx RT,RA,RB
 144
 145 Pseudo-code:
 146
 147     EA <- (RA)
 148     RT <- EXTS(MEM(EA, 4))
 149     RA <- (RA) + (RB)
 150
 151 Special Registers Altered:
 152
 153     None
 154
 155 # Load Doubleword with Post-Update Indexed
 156
 157 DS-Form
 158
 159 * ldup RT,DS(RA)
 160
 161 Pseudo-code:
 162
 163     EA <- (RA)
 164     RT <- MEM(EA, 8)
 165     RA <- (RA) + EXTS(DS || 0b00)
 166
 167 Special Registers Altered:
 168
 169     None
 170
 171 # Load Doubleword with Post-Update Indexed
 172
 173 X-Form
 174
 175 * ldupx RT,RA,RB
 176
 177 Pseudo-code:
 178
 179     EA <- (RA)
 180     RT <- MEM(EA, 8)
 181     RA <- (RA) + (RB)
 182
 183 Special Registers Altered:
 184
 185     None
 186