openpower/isa/pifixedstore.mdwn

   1 <!-- This defines DRAFT instructions described in SV -->
   2
   3 <!-- This defines instructions that store from a register to RAM -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 # Store Byte with Update
   7
   8 D-Form
   9
  10 * stbup RS,D(RA)
  11
  12 Pseudo-code:
  13
  14     EA <- (RA) + EXTS(D)
  15     ea <- (RA)
  16     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  17     RA <- EA
  18
  19 Special Registers Altered:
  20
  21     None
  22
  23 # Store Byte with Update Indexed
  24
  25 X-Form
  26
  27 * stbupx RS,RA,RB
  28
  29 Pseudo-code:
  30
  31     EA <- (RA) + (RB)
  32     ea <- (RA)
  33     MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
  34     RA <- EA
  35
  36 Special Registers Altered:
  37
  38     None
  39
  40 # Store Halfword with Update
  41
  42 D-Form
  43
  44 * sthup RS,D(RA)
  45
  46 Pseudo-code:
  47
  48     EA <- (RA) + EXTS(D)
  49     ea <- (RA)
  50     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  51     RA <- EA
  52
  53 Special Registers Altered:
  54
  55     None
  56
  57 # Store Halfword with Update Indexed
  58
  59 X-Form
  60
  61 * sthupx RS,RA,RB
  62
  63 Pseudo-code:
  64
  65     EA <- (RA) + (RB)
  66     ea <- (RA)
  67     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
  68     RA <- EA
  69
  70 Special Registers Altered:
  71
  72     None
  73
  74 # Store Word with Update
  75
  76 D-Form
  77
  78 * stwup RS,D(RA)
  79
  80 Pseudo-code:
  81
  82     EA <- (RA) + EXTS(D)
  83     ea <- (RA)
  84     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
  85     RA <- EA
  86
  87 Special Registers Altered:
  88
  89     None
  90
  91 # Store Word with Update Indexed
  92
  93 X-Form
  94
  95 * stwupx RS,RA,RB
  96
  97 Pseudo-code:
  98
  99     EA <- (RA) + (RB)
 100     ea <- (RA)
 101     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
 102     RA <- EA
 103
 104 Special Registers Altered:
 105
 106     None
 107
 108 # Store Doubleword with Update
 109
 110 DS-Form
 111
 112 * stdup RS,DS(RA)
 113
 114 Pseudo-code:
 115
 116     EA <- (RA) + EXTS(DS || 0b00)
 117     ea <- (RA)
 118     MEM(EA, 8) <- (RS)
 119     RA <- EA
 120
 121 Special Registers Altered:
 122
 123     None
 124
 125 # Store Doubleword with Update Indexed
 126
 127 X-Form
 128
 129 * stdupx RS,RA,RB
 130
 131 Pseudo-code:
 132
 133     EA <- (RA) + (RB)
 134     ea <- (RA)
 135     MEM(ea, 8) <- (RS)
 136     RA <- EA
 137
 138 Special Registers Altered:
 139
 140     None
 141