src/openpower/decoder/isa/test_caller.py

   1 import unittest
   2
   3 from nmutil.formaltest import FHDLTestCase
   4 from openpower.decoder.isa.caller import get_masked_reg, set_masked_reg
   5 from openpower.decoder.isa.test_runner import run_tst
   6 from openpower.decoder.selectable_int import SelectableInt
   7 from openpower.simulator.program import Program
   8
   9
  10 class DecoderTestCase(FHDLTestCase):
  11     def test_add(self):
  12         lst = ["add 1, 3, 2"]
  13         initial_regs = [0] * 32
  14         initial_regs[3] = 0x1234
  15         initial_regs[2] = 0x4321
  16         with Program(lst, bigendian=False) as program:
  17             sim = self.run_tst_program(program, initial_regs)
  18             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  19
  20     def test_addi(self):
  21         lst = ["addi 3, 0, 0x1234",
  22                "addi 2, 0, 0x4321",
  23                "add  1, 3, 2"]
  24         with Program(lst, bigendian=False) as program:
  25             sim = self.run_tst_program(program)
  26             print(sim.gpr(1))
  27             self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
  28
  29     def test_load_store(self):
  30         lst = ["addi 1, 0, 0x0010",
  31                "addi 2, 0, 0x1234",
  32                "stw 2, 0(1)",
  33                "lwz 3, 0(1)"]
  34         with Program(lst, bigendian=False) as program:
  35             sim = self.run_tst_program(program)
  36             print(sim.gpr(1))
  37             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
  38
  39     @unittest.skip("broken")
  40     def test_addpcis(self):
  41         lst = ["addpcis 1, 0x1",
  42                "addpcis 2, 0x1",
  43                "addpcis 3, 0x1"]
  44         with Program(lst, bigendian=False) as program:
  45             sim = self.run_tst_program(program)
  46             self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
  47             self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
  48             self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
  49
  50     def test_branch(self):
  51         lst = ["ba 0xc",             # branch to line 4
  52                "addi 1, 0, 0x1234",  # Should never execute
  53                "ba 0x1000",          # exit the program
  54                "addi 2, 0, 0x1234",  # line 4
  55                "ba 0x8"]             # branch to line 3
  56         with Program(lst, bigendian=False) as program:
  57             sim = self.run_tst_program(program)
  58             self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
  59             self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
  60             self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
  61
  62     def test_branch_link(self):
  63         lst = ["bl 0xc",
  64                "addi 2, 1, 0x1234",
  65                "ba 0x1000",
  66                "addi 1, 0, 0x1234",
  67                "bclr 20, 0, 0"]
  68         with Program(lst, bigendian=False) as program:
  69             sim = self.run_tst_program(program)
  70             self.assertEqual(sim.spr['LR'], SelectableInt(0x4, 64))
  71
  72     def test_branch_ctr(self):
  73         lst = ["addi 1, 0, 0x10",    # target of jump
  74                "mtspr 9, 1",         # mtctr 1
  75                "bcctr 20, 0, 0",     # bctr
  76                "addi 2, 0, 0x1",     # should never execute
  77                "addi 1, 0, 0x1234"]  # target of ctr
  78         with Program(lst, bigendian=False) as program:
  79             sim = self.run_tst_program(program)
  80             self.assertEqual(sim.spr['CTR'], SelectableInt(0x10, 64))
  81             self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
  82             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
  83
  84     def test_branch_cond(self):
  85         for i in [0, 10]:
  86             lst = [f"addi 1, 0, {i}",  # set r1 to i
  87                    "cmpi cr0, 1, 1, 10",  # compare r1 with 10 and store to cr0
  88                    "bc 12, 2, 0x8",       # beq 0x8 -
  89                                        # branch if r1 equals 10 to the nop below
  90                    "addi 2, 0, 0x1234",   # if r1 == 10 this shouldn't execute
  91                    "or 0, 0, 0"]          # branch target
  92             with Program(lst, bigendian=False) as program:
  93                 sim = self.run_tst_program(program)
  94                 if i == 10:
  95                     self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
  96                 else:
  97                     self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
  98
  99     def test_branch_loop(self):
 100         lst = ["addi 1, 0, 0",
 101                "addi 1, 0, 0",
 102                "addi 1, 1, 1",
 103                "add  2, 2, 1",
 104                "cmpi cr0, 1, 1, 10",
 105                "bc 12, 0, -0xc"]
 106         with Program(lst, bigendian=False) as program:
 107             sim = self.run_tst_program(program)
 108             # Verified with qemu
 109             self.assertEqual(sim.gpr(2), SelectableInt(0x37, 64))
 110
 111     def test_branch_loop_ctr(self):
 112         lst = ["addi 1, 0, 0",
 113                "addi 2, 0, 7",
 114                "mtspr 9, 2",    # set ctr to 7
 115                "addi 1, 1, 5",
 116                "bc 16, 0, -0x4"]  # bdnz to the addi above
 117         with Program(lst, bigendian=False) as program:
 118             sim = self.run_tst_program(program)
 119             # Verified with qemu
 120             self.assertEqual(sim.gpr(1), SelectableInt(0x23, 64))
 121
 122     def test_add_compare(self):
 123         lst = ["addis 1, 0, 0xffff",
 124                "addis 2, 0, 0xffff",
 125                "add. 1, 1, 2",
 126                "mfcr 3"]
 127         with Program(lst, bigendian=False) as program:
 128             sim = self.run_tst_program(program)
 129             # Verified with QEMU
 130             self.assertEqual(sim.gpr(3), SelectableInt(0x80000000, 64))
 131
 132     def test_cmp(self):
 133         lst = ["addis 1, 0, 0xffff",
 134                "addis 2, 0, 0xffff",
 135                "cmp cr2, 0, 1, 2",
 136                "mfcr 3"]
 137         with Program(lst, bigendian=False) as program:
 138             sim = self.run_tst_program(program)
 139             self.assertEqual(sim.gpr(3), SelectableInt(0x200000, 64))
 140
 141     def test_slw(self):
 142         lst = ["slw 1, 3, 2"]
 143         initial_regs = [0] * 32
 144         initial_regs[3] = 0xdeadbeefcafebabe
 145         initial_regs[2] = 5
 146         with Program(lst, bigendian=False) as program:
 147             sim = self.run_tst_program(program, initial_regs)
 148             self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 64))
 149
 150     def test_srw(self):
 151         lst = ["srw 1, 3, 2"]
 152         initial_regs = [0] * 32
 153         initial_regs[3] = 0xdeadbeefcafebabe
 154         initial_regs[2] = 5
 155         with Program(lst, bigendian=False) as program:
 156             sim = self.run_tst_program(program, initial_regs)
 157             self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 64))
 158
 159     def test_rlwinm(self):
 160         lst = ["rlwinm 3, 1, 5, 20, 6"]
 161         initial_regs = [0] * 32
 162         initial_regs[1] = -1
 163         with Program(lst, bigendian=False) as program:
 164             sim = self.run_tst_program(program, initial_regs)
 165             self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64))
 166
 167     def test_rlwimi(self):
 168         lst = ["rlwimi 3, 1, 5, 20, 6"]
 169         initial_regs = [0] * 32
 170         initial_regs[1] = 0xffffffffdeadbeef
 171         initial_regs[3] = 0x12345678
 172         with Program(lst, bigendian=False) as program:
 173             sim = self.run_tst_program(program, initial_regs)
 174             self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64))
 175
 176     def test_rldic(self):
 177         lst = ["rldic 3, 1, 5, 20"]
 178         initial_regs = [0] * 32
 179         initial_regs[1] = 0xdeadbeefcafec0de
 180         with Program(lst, bigendian=False) as program:
 181             sim = self.run_tst_program(program, initial_regs)
 182             self.assertEqual(sim.gpr(3), SelectableInt(0xdf95fd81bc0, 64))
 183
 184     def test_prty(self):
 185         lst = ["prtyw 2, 1"]
 186         initial_regs = [0] * 32
 187         initial_regs[1] = 0xdeadbeeecaffc0de
 188         with Program(lst, bigendian=False) as program:
 189             sim = self.run_tst_program(program, initial_regs)
 190             self.assertEqual(sim.gpr(2), SelectableInt(0x100000001, 64))
 191
 192     def test_popcnt(self):
 193         lst = ["popcntb 2, 1",
 194                "popcntw 3, 1",
 195                "popcntd 4, 1"
 196                ]
 197         initial_regs = [0] * 32
 198         initial_regs[1] = 0xdeadbeefcafec0de
 199         with Program(lst, bigendian=False) as program:
 200             sim = self.run_tst_program(program, initial_regs)
 201             self.assertEqual(sim.gpr(2),
 202                              SelectableInt(0x605060704070206, 64))
 203             self.assertEqual(sim.gpr(3),
 204                              SelectableInt(0x1800000013, 64))
 205             self.assertEqual(sim.gpr(4),
 206                              SelectableInt(0x2b, 64))
 207
 208     def test_cntlz(self):
 209         lst = ["cntlzd 2, 1",
 210                "cntlzw 4, 3"]
 211         initial_regs = [0] * 32
 212         initial_regs[1] = 0x0000beeecaffc0de
 213         initial_regs[3] = 0x0000000000ffc0de
 214         with Program(lst, bigendian=False) as program:
 215             sim = self.run_tst_program(program, initial_regs)
 216             self.assertEqual(sim.gpr(2), SelectableInt(16, 64))
 217             self.assertEqual(sim.gpr(4), SelectableInt(8, 64))
 218
 219     def test_cmpeqb(self):
 220         lst = ["cmpeqb cr0, 2, 1",
 221                "cmpeqb cr1, 3, 1"]
 222         initial_regs = [0] * 32
 223         initial_regs[1] = 0x0102030405060708
 224         initial_regs[2] = 0x04
 225         initial_regs[3] = 0x10
 226         with Program(lst, bigendian=False) as program:
 227             sim = self.run_tst_program(program, initial_regs)
 228             self.assertEqual(sim.crl[0].get_range().value,
 229                              SelectableInt(4, 4))
 230             self.assertEqual(sim.crl[1].get_range().value,
 231                              SelectableInt(0, 4))
 232
 233     def test_mtcrf(self):
 234         for i in range(4):
 235             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for
 236             #     i=0, 1, 2, 3
 237             # The positions of the CR fields have been verified using
 238             # QEMU and 'cmp crx, a, b' instructions
 239             lst = ["addis 1, 0, 0x7654",
 240                    "mtcrf %d, 1" % (1 << (7-i)),
 241                    ]
 242             with Program(lst, bigendian=False) as program:
 243                 sim = self.run_tst_program(program)
 244             print("cr", sim.cr)
 245             expected = (7-i)
 246             # check CR[0]/1/2/3 as well
 247             print("cr%d" % i, sim.crl[i].asint(True))
 248             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
 249             # check CR itself
 250             self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))
 251
 252     def run_tst_program(self, prog, initial_regs=[0] * 32):
 253         simulator = run_tst(prog, initial_regs)
 254         simulator.gpr.dump()
 255         return simulator
 256
 257
 258 class TestGetSetMaskedReg(FHDLTestCase):
 259     def test_get_set_masked_reg(self):
 260         regs = [0x123456789abcdef, 0xfedcba9876543210,
 261                 0x2468ace13579bdf, 0xfdb975310eca8642]
 262         set_masked_reg(regs, base=2, offs=5, ew_bits=16, value=0x369c)
 263         self.assertEqual(list(map(hex, regs)), [
 264             "0x123456789abcdef", "0xfedcba9876543210",
 265             "0x2468ace13579bdf", "0xfdb97531369c8642"])
 266         self.assertEqual(hex(get_masked_reg(regs, base=2, offs=5, ew_bits=16)),
 267                          "0x369c")
 268         self.assertEqual(hex(get_masked_reg(regs, base=2, offs=0, ew_bits=16)),
 269                          "0x9bdf")
 270
 271
 272 if __name__ == "__main__":
 273     unittest.main()