4 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.helpers
import fp64toselectable
6 from openpower
.decoder
.isa
.remap_preduce_yield
import preduce_y
7 from openpower
.decoder
.isa
.test_caller
import run_tst
8 from openpower
.decoder
.selectable_int
import SelectableInt
9 from openpower
.simulator
.program
import Program
10 from openpower
.insndb
.asm
import SVP64Asm
20 class DecoderTestCase(FHDLTestCase
):
22 def _check_regs(self
, sim
, expected
):
24 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
26 def test_sv_remap1(self
):
27 """>>> lst = ["svshape 7, 1, 1, 7, 0",
28 "svremap 31, 0, 1, 0, 0, 0, 0",
33 lst
= SVP64Asm(["svshape 7, 1, 1, 7, 0",
34 "svremap 31, 0, 1, 0, 0, 0, 0",
40 vec
= [1, 2, 3, 4, 9, 5, 6]
44 for i
, x
in enumerate(vec
):
47 with
Program(lst
, bigendian
=False) as program
:
48 sim
= self
.run_tst_program(program
, initial_regs
=gprs
)
49 print("spr svshape0", sim
.spr
['SVSHAPE0'])
50 print(" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
51 print(" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
52 print(" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
53 print("spr svshape1", sim
.spr
['SVSHAPE1'])
54 print("spr svshape2", sim
.spr
['SVSHAPE2'])
55 print("spr svshape3", sim
.spr
['SVSHAPE3'])
57 val
= sim
.gpr(i
).value
60 # confirm that the results are as expected
61 expected
= preduce_y(vec
)
62 for i
, v
in enumerate(res
):
63 self
.assertEqual(v
, expected
[i
])
65 def test_sv_remap2(self
):
66 """>>> lst = ["svshape 7, 1, 1, 7, 0",
67 "svremap 31, 1, 0, 0, 0, 0, 0", # different order
70 REMAP sv.subf RT,RA,RB - inverted application of RA/RB
71 left/right due to subf
73 lst
= SVP64Asm(["svshape 7, 1, 1, 7, 0",
74 "svremap 31, 1, 0, 0, 0, 0, 0",
80 vec
= [1, 2, 3, 4, 9, 5, 6]
84 for i
, x
in enumerate(vec
):
87 with
Program(lst
, bigendian
=False) as program
:
88 sim
= self
.run_tst_program(program
, initial_regs
=gprs
)
89 print("spr svshape0", sim
.spr
['SVSHAPE0'])
90 print(" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
91 print(" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
92 print(" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
93 print("spr svshape1", sim
.spr
['SVSHAPE1'])
94 print("spr svshape2", sim
.spr
['SVSHAPE2'])
95 print("spr svshape3", sim
.spr
['SVSHAPE3'])
97 val
= sim
.gpr(i
).value
100 # confirm that the results are as expected, mask with 64-bit
101 expected
= preduce_y(vec
, operation
=operator
.sub
)
102 for i
, v
in enumerate(res
):
103 self
.assertEqual(v
& 0xffffffffffffffff,
104 expected
[i
] & 0xffffffffffffffff)
106 def test_sv_remap3(self
):
107 """>>> lst = ["svshape 7, 1, 1, 7, 0",
108 "svremap 31, 0, 1, 0, 0, 0, 0",
109 "sv.fcpsgn *0, *8, *16"
111 REMAP sv.subf RT,RA,RB - inverted application of RA/RB
112 left/right due to subf
114 lst
= SVP64Asm(["svshape 7, 1, 1, 7, 0",
115 "svremap 31, 0, 1, 0, 0, 0, 0",
116 "sv.fcpsgn *0, *0, *0"
121 vec
= [-1.0, 2.0, 3.0, -4.0, 9.0, -5.0, 6.0]
125 for i
, x
in enumerate(vec
):
126 fprs
[i
] = fp64toselectable(x
)
128 with
Program(lst
, bigendian
=False) as program
:
129 sim
= self
.run_tst_program(program
, initial_fprs
=fprs
)
130 print("spr svshape0", sim
.spr
['SVSHAPE0'])
131 print(" xdimsz", sim
.spr
['SVSHAPE0'].xdimsz
)
132 print(" ydimsz", sim
.spr
['SVSHAPE0'].ydimsz
)
133 print(" zdimsz", sim
.spr
['SVSHAPE0'].zdimsz
)
134 print("spr svshape1", sim
.spr
['SVSHAPE1'])
135 print("spr svshape2", sim
.spr
['SVSHAPE2'])
136 print("spr svshape3", sim
.spr
['SVSHAPE3'])
137 # confirm that the results are as expected
138 expected
= preduce_y(vec
, operation
=signcopy
)
140 val
= sim
.fpr(i
).value
142 print("i", i
, float(sim
.fpr(i
)), vec
[i
], expected
[i
])
143 for i
, v
in enumerate(res
):
144 self
.assertEqual(v
& 0xffffffffffffffff,
145 fp64toselectable(expected
[i
]).value
)
147 def run_tst_program(self
, prog
, initial_regs
=None,
151 if initial_regs
is None:
152 initial_regs
= [0] * 32
153 simulator
= run_tst(prog
, initial_regs
, mem
=initial_mem
,
154 initial_fprs
=initial_fprs
,
165 if __name__
== "__main__":