src/openpower/decoder/isa/test_caller_svp64_predication.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from openpower.decoder.isa.caller import ISACaller
   6 from openpower.decoder.power_decoder import (create_pdecode)
   7 from openpower.decoder.power_decoder2 import (PowerDecode2)
   8 from openpower.simulator.program import Program
   9 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  10 from openpower.decoder.selectable_int import SelectableInt
  11 from openpower.decoder.orderedset import OrderedSet
  12 from openpower.decoder.isa.all import ISA
  13 from openpower.decoder.isa.test_caller import Register, run_tst
  14 from openpower.sv.trans.svp64 import SVP64Asm
  15 from openpower.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def tst_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "sv.stw 5.v, 0(1.v)",
  30                         "sv.lwz 9.v, 0(1.v)"])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print(sim.gpr(1))
  42             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  43             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  44
  45     def test_sv_extsw_intpred(self):
  46         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
  47         # works as follows, where any zeros indicate "skip element"
  48         #       - sources are 9 and 10
  49         #       - dests are 5 and 6
  50         #       - source mask says "pick first element from source (5)
  51         #       - dest mask says "pick *second* element from dest (10)
  52         #
  53         # therefore the operation that's carried out is:
  54         #       GPR(10) = extsb(GPR(5))
  55         #
  56         # this is a type of back-to-back VREDUCE and VEXPAND but it applies
  57         # to *operations*, not just MVs like in traditional Vector ISAs
  58         # ascii graphic:
  59         #
  60         #   reg num        0 1 2 3 4 5 6 7 8 9 10
  61         #   src ~r3=0b01                     Y N
  62         #                                    |
  63         #                              +-----+
  64         #                              |
  65         #   dest r3=0b10             N Y
  66
  67         isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
  68                        ])
  69         lst = list(isa)
  70         print ("listing", lst)
  71
  72         # initial values in GPR regfile
  73         initial_regs = [0] * 32
  74         initial_regs[3] = 0b10   # predicate mask
  75         initial_regs[9] = 0x91   # source ~r3 is 0b01 so this will be used
  76         initial_regs[10] = 0x90  # this gets skipped
  77         # SVSTATE (in this case, VL=2)
  78         svstate = SVP64State()
  79         svstate.vl[0:7] = 2 # VL
  80         svstate.maxvl[0:7] = 2 # MAXVL
  81         print ("SVSTATE", bin(svstate.spr.asint()))
  82         # copy before running
  83         expected_regs = deepcopy(initial_regs)
  84         expected_regs[5] = 0x0                   # dest r3 is 0b10: skip
  85         expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1
  86
  87         with Program(lst, bigendian=False) as program:
  88             sim = self.run_tst_program(program, initial_regs, svstate)
  89             self._check_regs(sim, expected_regs)
  90
  91     def test_sv_extsw_intpred_dz(self):
  92         # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
  93         isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
  94                        ])
  95         lst = list(isa)
  96         print ("listing", lst)
  97
  98         # initial values in GPR regfile
  99         initial_regs = [0] * 32
 100         initial_regs[3] = 0b01   # predicate mask (dest)
 101         initial_regs[5] = 0xfeed # going to be overwritten
 102         initial_regs[6] = 0xbeef # going to be overwritten (with zero)
 103         initial_regs[9] = 0x91   # dest r3 is 0b01 so this will be used
 104         initial_regs[10] = 0x90  # this gets read but the output gets zero'd
 105         # SVSTATE (in this case, VL=2)
 106         svstate = SVP64State()
 107         svstate.vl[0:7] = 2 # VL
 108         svstate.maxvl[0:7] = 2 # MAXVL
 109         print ("SVSTATE", bin(svstate.spr.asint()))
 110         # copy before running
 111         expected_regs = deepcopy(initial_regs)
 112         expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
 113         expected_regs[6] = 0                     # 2nd bit of r3 is 1: zero
 114
 115         with Program(lst, bigendian=False) as program:
 116             sim = self.run_tst_program(program, initial_regs, svstate)
 117             self._check_regs(sim, expected_regs)
 118
 119     def test_sv_add_intpred(self):
 120         # adds, integer predicated mask r3=0b10
 121         #       1 = 5 + 9   => not to be touched (skipped)
 122         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 123         isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
 124                        ])
 125         lst = list(isa)
 126         print ("listing", lst)
 127
 128         # initial values in GPR regfile
 129         initial_regs = [0] * 32
 130         initial_regs[1] = 0xbeef   # not to be altered
 131         initial_regs[3] = 0b10   # predicate mask
 132         initial_regs[9] = 0x1234
 133         initial_regs[10] = 0x1111
 134         initial_regs[5] = 0x4321
 135         initial_regs[6] = 0x2223
 136         # SVSTATE (in this case, VL=2)
 137         svstate = SVP64State()
 138         svstate.vl[0:7] = 2 # VL
 139         svstate.maxvl[0:7] = 2 # MAXVL
 140         print ("SVSTATE", bin(svstate.spr.asint()))
 141         # copy before running
 142         expected_regs = deepcopy(initial_regs)
 143         expected_regs[1] = 0xbeef
 144         expected_regs[2] = 0x3334
 145
 146         with Program(lst, bigendian=False) as program:
 147             sim = self.run_tst_program(program, initial_regs, svstate)
 148             self._check_regs(sim, expected_regs)
 149
 150     def test_sv_add_cr_pred(self):
 151         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
 152         #       1 = 5 + 9   => not to be touched (skipped)
 153         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 154         isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
 155                        ])
 156         lst = list(isa)
 157         print ("listing", lst)
 158
 159         # initial values in GPR regfile
 160         initial_regs = [0] * 32
 161         initial_regs[1] = 0xbeef   # not to be altered
 162         initial_regs[9] = 0x1234
 163         initial_regs[10] = 0x1111
 164         initial_regs[5] = 0x4321
 165         initial_regs[6] = 0x2223
 166         # SVSTATE (in this case, VL=2)
 167         svstate = SVP64State()
 168         svstate.vl[0:7] = 2 # VL
 169         svstate.maxvl[0:7] = 2 # MAXVL
 170         print ("SVSTATE", bin(svstate.spr.asint()))
 171         # copy before running
 172         expected_regs = deepcopy(initial_regs)
 173         expected_regs[1] = 0xbeef
 174         expected_regs[2] = 0x3334
 175
 176         # set up CR predicate - CR4.eq=1 and CR5.eq=0
 177         cr = (0b0010) << ((7-4)*4) # CR4.eq (we hope)
 178
 179         with Program(lst, bigendian=False) as program:
 180             sim = self.run_tst_program(program, initial_regs, svstate,
 181                                        initial_cr=cr)
 182             self._check_regs(sim, expected_regs)
 183
 184     def test_intpred_vcompress(self):
 185         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 186         #   src r3=0b101                     Y  N  Y
 187         #                                    |     |
 188         #                            +-------+     |
 189         #                            | +-----------+
 190         #                            | |
 191         #   dest always              Y Y Y
 192
 193         isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
 194         lst = list(isa)
 195         print("listing", lst)
 196
 197         # initial values in GPR regfile
 198         initial_regs = [0] * 32
 199         initial_regs[3] = 0b101  # predicate mask
 200         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 201         initial_regs[10] = 0x91  # this gets skipped
 202         initial_regs[11] = 0x92  # source r3 is 0b101 so this will be used
 203         # SVSTATE (in this case, VL=3)
 204         svstate = SVP64State()
 205         svstate.vl[0:7] = 3  # VL
 206         svstate.maxvl[0:7] = 3  # MAXVL
 207         print("SVSTATE", bin(svstate.spr.asint()))
 208         # copy before running
 209         expected_regs = deepcopy(initial_regs)
 210         expected_regs[5] = 0xffff_ffff_ffff_ff90  # (from r9)
 211         expected_regs[6] = 0xffff_ffff_ffff_ff92  # (from r11)
 212         expected_regs[7] = 0x0  # (VL loop runs out before we can use it)
 213
 214         with Program(lst, bigendian=False) as program:
 215             sim = self.run_tst_program(program, initial_regs, svstate)
 216             self._check_regs(sim, expected_regs)
 217
 218     def test_intpred_vexpand(self):
 219         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 220         #   src always                       Y  Y  Y
 221         #                                    |  |
 222         #                            +-------+  |
 223         #                            |   +------+
 224         #                            |   |
 225         #   dest r3=0b101            Y N Y
 226
 227         isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
 228         lst = list(isa)
 229         print("listing", lst)
 230
 231         # initial values in GPR regfile
 232         initial_regs = [0] * 32
 233         initial_regs[3] = 0b101  # predicate mask
 234         initial_regs[9] = 0x90   # source is "always", so this will be used
 235         initial_regs[10] = 0x91  # likewise
 236         initial_regs[11] = 0x92  # the VL loop runs out before we can use it
 237         # SVSTATE (in this case, VL=3)
 238         svstate = SVP64State()
 239         svstate.vl[0:7] = 3  # VL
 240         svstate.maxvl[0:7] = 3  # MAXVL
 241         print("SVSTATE", bin(svstate.spr.asint()))
 242         # copy before running
 243         expected_regs = deepcopy(initial_regs)
 244         expected_regs[5] = 0xffff_ffff_ffff_ff90  # 1st bit of r3 is 1
 245         expected_regs[6] = 0x0  # skip
 246         expected_regs[7] = 0xffff_ffff_ffff_ff91  # 3nd bit of r3 is 1
 247
 248         with Program(lst, bigendian=False) as program:
 249             sim = self.run_tst_program(program, initial_regs, svstate)
 250             self._check_regs(sim, expected_regs)
 251
 252     def test_intpred_twinpred(self):
 253         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 254         #   src r3=0b101                     Y  N  Y
 255         #                                    |
 256         #                              +-----+
 257         #                              |
 258         #   dest ~r3=0b010           N Y N
 259
 260         isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
 261         lst = list(isa)
 262         print("listing", lst)
 263
 264         # initial values in GPR regfile
 265         initial_regs = [0] * 32
 266         initial_regs[3] = 0b101  # predicate mask
 267         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 268         initial_regs[10] = 0x91  # this gets skipped
 269         initial_regs[11] = 0x92  # VL loop runs out before we can use it
 270         # SVSTATE (in this case, VL=3)
 271         svstate = SVP64State()
 272         svstate.vl[0:7] = 3  # VL
 273         svstate.maxvl[0:7] = 3  # MAXVL
 274         print("SVSTATE", bin(svstate.spr.asint()))
 275         # copy before running
 276         expected_regs = deepcopy(initial_regs)
 277         expected_regs[5] = 0x0  # dest ~r3 is 0b010: skip
 278         expected_regs[6] = 0xffff_ffff_ffff_ff90  # 2nd bit of ~r3 is 1
 279         expected_regs[7] = 0x0  # dest ~r3 is 0b010: skip
 280
 281         with Program(lst, bigendian=False) as program:
 282             sim = self.run_tst_program(program, initial_regs, svstate)
 283             self._check_regs(sim, expected_regs)
 284
 285     # checks that we are able to resume in the middle of a VL loop,
 286     # after an interrupt, or after the user has updated src/dst step
 287     # let's assume the user has prepared src/dst step before running this
 288     # vector instruction
 289     def test_intpred_reentrant(self):
 290         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11 12
 291         #   srcstep=1                           v
 292         #   src r3=0b0101                    Y  N  Y  N
 293         #                                    :     |
 294         #                              + - - +     |
 295         #                              :   +-------+
 296         #                              :   |
 297         #   dest ~r3=0b1010          N Y N Y
 298         #   dststep=2                    ^
 299
 300         isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
 301         lst = list(isa)
 302         print("listing", lst)
 303
 304         # initial values in GPR regfile
 305         initial_regs = [0] * 32
 306         initial_regs[3] = 0b0101  # mask
 307         initial_regs[9] = 0x90   # srcstep starts at 2, so this gets skipped
 308         initial_regs[10] = 0x91  # skip
 309         initial_regs[11] = 0x92  # this will be used
 310         initial_regs[12] = 0x93  # skip
 311
 312         # SVSTATE (in this case, VL=4)
 313         svstate = SVP64State()
 314         svstate.vl[0:7] = 4  # VL
 315         svstate.maxvl[0:7] = 4  # MAXVL
 316         # set src/dest step on the middle of the loop
 317         svstate.srcstep[0:7] = 1
 318         svstate.dststep[0:7] = 2
 319         print("SVSTATE", bin(svstate.spr.asint()))
 320         # copy before running
 321         expected_regs = deepcopy(initial_regs)
 322         expected_regs[5] = 0x0  # skip
 323         expected_regs[6] = 0x0  # dststep starts at 3, so this gets skipped
 324         expected_regs[7] = 0x0  # skip
 325         expected_regs[8] = 0xffff_ffff_ffff_ff92  # this will be used
 326
 327         with Program(lst, bigendian=False) as program:
 328             sim = self.run_tst_program(program, initial_regs, svstate)
 329             self._check_regs(sim, expected_regs)
 330
 331     def test_shift_one_by_r3_dest(self):
 332         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 333         #   src r30=0b100                    N  N  Y
 334         #                                          |
 335         #                              +-----------+
 336         #                              |
 337         #   dest r3=1: 1<<r3=0b010   N Y N
 338
 339         isa = SVP64Asm(['sv.extsb/dm=1<<r3/sm=r30 5.v, 9.v'])
 340         lst = list(isa)
 341         print("listing", lst)
 342
 343         # initial values in GPR regfile
 344         initial_regs = [0] * 32
 345         initial_regs[3] = 1  # dest mask = 1<<r3 = 0b010
 346         initial_regs[30] = 0b100  # source mask
 347         initial_regs[9] = 0x90   # skipped
 348         initial_regs[10] = 0x91  # skipped
 349         initial_regs[11] = 0x92  # 3rd bit of r30 is 1
 350         # SVSTATE (in this case, VL=3)
 351         svstate = SVP64State()
 352         svstate.vl[0:7] = 3  # VL
 353         svstate.maxvl[0:7] = 3  # MAXVL
 354         print("SVSTATE", bin(svstate.spr.asint()))
 355         # copy before running
 356         expected_regs = deepcopy(initial_regs)
 357         expected_regs[5] = 0x0  # skip
 358         expected_regs[6] = 0xffff_ffff_ffff_ff92  # r3 is 1, so this is used
 359         expected_regs[7] = 0x0  # skip
 360
 361         with Program(lst, bigendian=False) as program:
 362             sim = self.run_tst_program(program, initial_regs, svstate)
 363             self._check_regs(sim, expected_regs)
 364
 365     def test_shift_one_by_r3_source(self):
 366         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 367         #   src r3=2: 1<<r3=0b100            N  N  Y
 368         #                                          |
 369         #                              +-----------+
 370         #                              |
 371         #   dest r30=0b010           N Y N
 372
 373         isa = SVP64Asm(['sv.extsb/sm=1<<r3/dm=r30 5.v, 9.v'])
 374         lst = list(isa)
 375         print("listing", lst)
 376
 377         # initial values in GPR regfile
 378         initial_regs = [0] * 32
 379         initial_regs[3] = 2  # source mask = 1<<r3 = 0b100
 380         initial_regs[30] = 0b010  # dest mask
 381         initial_regs[9] = 0x90   # skipped
 382         initial_regs[10] = 0x91  # skipped
 383         initial_regs[11] = 0x92  # r3 is 2, so this will be used
 384         # SVSTATE (in this case, VL=3)
 385         svstate = SVP64State()
 386         svstate.vl[0:7] = 3  # VL
 387         svstate.maxvl[0:7] = 3  # MAXVL
 388         print("SVSTATE", bin(svstate.spr.asint()))
 389         # copy before running
 390         expected_regs = deepcopy(initial_regs)
 391         expected_regs[5] = 0x0  # skip
 392         expected_regs[6] = 0xffff_ffff_ffff_ff92  # 2nd bit of r30 is 1
 393         expected_regs[7] = 0x0  # skip
 394
 395         with Program(lst, bigendian=False) as program:
 396             sim = self.run_tst_program(program, initial_regs, svstate)
 397             self._check_regs(sim, expected_regs)
 398
 399     # checks reentrant CR predication
 400     def test_crpred_reentrant(self):
 401         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11 12
 402         #   srcstep=1                           v
 403         #   src cr4.eq=1                     Y  N  Y  N
 404         #       cr6.eq=1                     :     |
 405         #                              + - - +     |
 406         #                              :   +-------+
 407         #   dest cr5.lt=1              :   |
 408         #        cr7.lt=1            N Y N Y
 409         #   dststep=2                    ^
 410
 411         isa = SVP64Asm(['sv.extsb/sm=eq/dm=lt 5.v, 9.v'])
 412         lst = list(isa)
 413         print("listing", lst)
 414
 415         # initial values in GPR regfile
 416         initial_regs = [0] * 32
 417         initial_regs[9] = 0x90  # srcstep starts at 2, so this gets skipped
 418         initial_regs[10] = 0x91  # skip
 419         initial_regs[11] = 0x92  # this will be used
 420         initial_regs[12] = 0x93  # skip
 421
 422         cr = CRFields()
 423         # set up CR predicate
 424         # CR4.eq=1 and CR6.eq=1
 425         cr.crl[4][CRFields.EQ] = 1
 426         cr.crl[6][CRFields.EQ] = 1
 427         # CR5.lt=1 and CR7.lt=1
 428         cr.crl[5][CRFields.LT] = 1
 429         cr.crl[7][CRFields.LT] = 1
 430         # SVSTATE (in this case, VL=4)
 431         svstate = SVP64State()
 432         svstate.vl[0:7] = 4  # VL
 433         svstate.maxvl[0:7] = 4  # MAXVL
 434         # set src/dest step on the middle of the loop
 435         svstate.srcstep[0:7] = 1
 436         svstate.dststep[0:7] = 2
 437         print("SVSTATE", bin(svstate.spr.asint()))
 438         # copy before running
 439         expected_regs = deepcopy(initial_regs)
 440         expected_regs[5] = 0x0  # skip
 441         expected_regs[6] = 0x0  # dststep starts at 3, so this gets skipped
 442         expected_regs[7] = 0x0  # skip
 443         expected_regs[8] = 0xffff_ffff_ffff_ff92  # this will be used
 444
 445         with Program(lst, bigendian=False) as program:
 446             sim = self.run_tst_program(program, initial_regs, svstate,
 447                                        initial_cr=cr.cr.asint())
 448             self._check_regs(sim, expected_regs)
 449
 450     def run_tst_program(self, prog, initial_regs=None,
 451                               svstate=None,
 452                               initial_cr=0):
 453         if initial_regs is None:
 454             initial_regs = [0] * 32
 455         simulator = run_tst(prog, initial_regs, svstate=svstate,
 456                             initial_cr=initial_cr)
 457         simulator.gpr.dump()
 458         return simulator
 459
 460
 461 if __name__ == "__main__":
 462     unittest.main()