src/openpower/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from nmutil.util import sel
  12
  13 from nmutil.picker import PriorityPicker
  14 from nmutil.iocontrol import RecordObject
  15 from nmutil.extend import exts
  16
  17 from openpower.exceptions import LDSTException
  18
  19 from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder
  20 from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra
  21 from openpower.decoder.power_svp64_rm import SVP64RMModeDecode
  22 from openpower.decoder.power_regspec_map import regspec_decode_read
  23 from openpower.decoder.power_regspec_map import regspec_decode_write
  24 from openpower.decoder.power_decoder import create_pdecode
  25 from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
  26                                      CRInSel, CROutSel,
  27                                      LdstLen, In1Sel, In2Sel, In3Sel,
  28                                      OutSel, SPRfull, SPRreduced,
  29                                      RC, LDSTMode,
  30                                      SVEXTRA, SVEtype, SVPtype)
  31 from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
  32                                          Decode2ToOperand)
  33 from openpower.sv.svp64 import SVP64Rec
  34 from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
  35                         SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
  36
  37 from openpower.consts import FastRegsEnum
  38 from openpower.consts import XERRegsEnum
  39 from openpower.consts import TT
  40 from openpower.state import CoreState
  41 from openpower.util import spr_to_fast
  42
  43
  44 def decode_spr_num(spr):
  45     return Cat(spr[5:10], spr[0:5])
  46
  47
  48 def instr_is_priv(m, op, insn):
  49     """determines if the instruction is privileged or not
  50     """
  51     comb = m.d.comb
  52     is_priv_insn = Signal(reset_less=True)
  53     with m.Switch(op):
  54         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  55                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  56             comb += is_priv_insn.eq(1)
  57         with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  58         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  59             with m.If(insn[20]):  # field XFX.spr[-1] i think
  60                 comb += is_priv_insn.eq(1)
  61     return is_priv_insn
  62
  63
  64 class SPRMap(Elaboratable):
  65     """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
  66     """
  67
  68     def __init__(self, regreduce_en):
  69         self.regreduce_en = regreduce_en
  70         if regreduce_en:
  71             SPR = SPRreduced
  72         else:
  73             SPR = SPRfull
  74
  75         self.spr_i = Signal(10, reset_less=True)
  76         self.spr_o = Data(SPR, name="spr_o")
  77         self.fast_o = Data(3, name="fast_o")
  78
  79     def elaborate(self, platform):
  80         m = Module()
  81         if self.regreduce_en:
  82             SPR = SPRreduced
  83         else:
  84             SPR = SPRfull
  85         with m.Switch(self.spr_i):
  86             for i, x in enumerate(SPR):
  87                 with m.Case(x.value):
  88                     m.d.comb += self.spr_o.data.eq(i)
  89                     m.d.comb += self.spr_o.ok.eq(1)
  90             for x, v in spr_to_fast.items():
  91                 with m.Case(x.value):
  92                     m.d.comb += self.fast_o.data.eq(v)
  93                     m.d.comb += self.fast_o.ok.eq(1)
  94         return m
  95
  96
  97 class DecodeA(Elaboratable):
  98     """DecodeA from instruction
  99
 100     decodes register RA, implicit and explicit CSRs
 101     """
 102
 103     def __init__(self, dec, regreduce_en):
 104         self.regreduce_en = regreduce_en
 105         if self.regreduce_en:
 106             SPR = SPRreduced
 107         else:
 108             SPR = SPRfull
 109         self.dec = dec
 110         self.sel_in = Signal(In1Sel, reset_less=True)
 111         self.insn_in = Signal(32, reset_less=True)
 112         self.reg_out = Data(5, name="reg_a")
 113         self.spr_out = Data(SPR, "spr_a")
 114         self.fast_out = Data(3, "fast_a")
 115         self.sv_nz = Signal(1)
 116
 117     def elaborate(self, platform):
 118         m = Module()
 119         comb = m.d.comb
 120         op = self.dec.op
 121         reg = self.reg_out
 122         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 123
 124         # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
 125         ra = Signal(5, reset_less=True)
 126         comb += ra.eq(self.dec.RA)
 127         with m.If((self.sel_in == In1Sel.RA) |
 128                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
 129                    ((ra != Const(0, 5)) | (self.sv_nz != Const(0, 1))))):
 130             comb += reg.data.eq(ra)
 131             comb += reg.ok.eq(1)
 132
 133         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 134         # moved it to 1st position (in1_sel)... because
 135         rs = Signal(5, reset_less=True)
 136         comb += rs.eq(self.dec.RS)
 137         with m.If(self.sel_in == In1Sel.RS):
 138             comb += reg.data.eq(rs)
 139             comb += reg.ok.eq(1)
 140
 141         # decode Fast-SPR based on instruction type
 142         with m.Switch(op.internal_op):
 143
 144             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 145             with m.Case(MicrOp.OP_BC):
 146                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 147                     # constant: CTR
 148                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 149                     comb += self.fast_out.ok.eq(1)
 150             with m.Case(MicrOp.OP_BCREG):
 151                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 152                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 153                 with m.If(xo9 & ~xo5):
 154                     # constant: CTR
 155                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 156                     comb += self.fast_out.ok.eq(1)
 157
 158             # MFSPR move from SPRs
 159             with m.Case(MicrOp.OP_MFSPR):
 160                 spr = Signal(10, reset_less=True)
 161                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 162                 comb += sprmap.spr_i.eq(spr)
 163                 comb += self.spr_out.eq(sprmap.spr_o)
 164                 comb += self.fast_out.eq(sprmap.fast_o)
 165
 166         return m
 167
 168
 169 class DecodeAImm(Elaboratable):
 170     """DecodeA immediate from instruction
 171
 172     decodes register RA, whether immediate-zero, implicit and
 173     explicit CSRs.  SVP64 mode requires 2 extra bits
 174     """
 175
 176     def __init__(self, dec):
 177         self.dec = dec
 178         self.sel_in = Signal(In1Sel, reset_less=True)
 179         self.immz_out = Signal(reset_less=True)
 180         self.sv_nz = Signal(1) # EXTRA bits from SVP64
 181
 182     def elaborate(self, platform):
 183         m = Module()
 184         comb = m.d.comb
 185
 186         # zero immediate requested
 187         ra = Signal(5, reset_less=True)
 188         comb += ra.eq(self.dec.RA)
 189         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 190                     (ra == Const(0, 5)) &
 191                     (self.sv_nz == Const(0, 1))):
 192             comb += self.immz_out.eq(1)
 193
 194         return m
 195
 196
 197 class DecodeB(Elaboratable):
 198     """DecodeB from instruction
 199
 200     decodes register RB, different forms of immediate (signed, unsigned),
 201     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 202     by industry-standard convention, "lane 2" is where fully-decoded
 203     immediates are muxed in.
 204     """
 205
 206     def __init__(self, dec):
 207         self.dec = dec
 208         self.sel_in = Signal(In2Sel, reset_less=True)
 209         self.insn_in = Signal(32, reset_less=True)
 210         self.reg_out = Data(7, "reg_b")
 211         self.reg_isvec = Signal(1, name="reg_b_isvec") # TODO: in reg_out
 212         self.fast_out = Data(3, "fast_b")
 213
 214     def elaborate(self, platform):
 215         m = Module()
 216         comb = m.d.comb
 217         op = self.dec.op
 218         reg = self.reg_out
 219
 220         # select Register B field
 221         with m.Switch(self.sel_in):
 222             with m.Case(In2Sel.RB):
 223                 comb += reg.data.eq(self.dec.RB)
 224                 comb += reg.ok.eq(1)
 225             with m.Case(In2Sel.RS):
 226                 # for M-Form shiftrot
 227                 comb += reg.data.eq(self.dec.RS)
 228                 comb += reg.ok.eq(1)
 229
 230         # decode SPR2 based on instruction type
 231         # BCREG implicitly uses LR or TAR for 2nd reg
 232         # CTR however is already in fast_spr1 *not* 2.
 233         with m.If(op.internal_op == MicrOp.OP_BCREG):
 234             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 235             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 236             with m.If(~xo9):
 237                 comb += self.fast_out.data.eq(FastRegsEnum.LR)
 238                 comb += self.fast_out.ok.eq(1)
 239             with m.Elif(xo5):
 240                 comb += self.fast_out.data.eq(FastRegsEnum.TAR)
 241                 comb += self.fast_out.ok.eq(1)
 242
 243         return m
 244
 245
 246 class DecodeBImm(Elaboratable):
 247     """DecodeB immediate from instruction
 248     """
 249     def __init__(self, dec):
 250         self.dec = dec
 251         self.sel_in = Signal(In2Sel, reset_less=True)
 252         self.imm_out = Data(64, "imm_b")
 253
 254     def elaborate(self, platform):
 255         m = Module()
 256         comb = m.d.comb
 257
 258         # select Register B Immediate
 259         with m.Switch(self.sel_in):
 260             with m.Case(In2Sel.CONST_UI): # unsigned
 261                 comb += self.imm_out.data.eq(self.dec.UI)
 262                 comb += self.imm_out.ok.eq(1)
 263             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 264                 si = Signal(16, reset_less=True)
 265                 comb += si.eq(self.dec.SI)
 266                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 267                 comb += self.imm_out.ok.eq(1)
 268             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 269                 si_hi = Signal(32, reset_less=True)
 270                 comb += si_hi.eq(self.dec.SI << 16)
 271                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 272                 comb += self.imm_out.ok.eq(1)
 273             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 274                 ui = Signal(16, reset_less=True)
 275                 comb += ui.eq(self.dec.UI)
 276                 comb += self.imm_out.data.eq(ui << 16)
 277                 comb += self.imm_out.ok.eq(1)
 278             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 279                 li = Signal(26, reset_less=True)
 280                 comb += li.eq(self.dec.LI << 2)
 281                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 282                 comb += self.imm_out.ok.eq(1)
 283             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 284                 bd = Signal(16, reset_less=True)
 285                 comb += bd.eq(self.dec.BD << 2)
 286                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 287                 comb += self.imm_out.ok.eq(1)
 288             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 289                 ds = Signal(16, reset_less=True)
 290                 comb += ds.eq(self.dec.DS << 2)
 291                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 292                 comb += self.imm_out.ok.eq(1)
 293             with m.Case(In2Sel.CONST_M1): # signed (-1)
 294                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 295                 comb += self.imm_out.ok.eq(1)
 296             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 297                 comb += self.imm_out.data.eq(self.dec.sh)
 298                 comb += self.imm_out.ok.eq(1)
 299             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 300                 comb += self.imm_out.data.eq(self.dec.SH32)
 301                 comb += self.imm_out.ok.eq(1)
 302
 303         return m
 304
 305
 306 class DecodeC(Elaboratable):
 307     """DecodeC from instruction
 308
 309     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 310     """
 311
 312     def __init__(self, dec):
 313         self.dec = dec
 314         self.sel_in = Signal(In3Sel, reset_less=True)
 315         self.insn_in = Signal(32, reset_less=True)
 316         self.reg_out = Data(5, "reg_c")
 317
 318     def elaborate(self, platform):
 319         m = Module()
 320         comb = m.d.comb
 321         op = self.dec.op
 322         reg = self.reg_out
 323
 324         # select Register C field
 325         with m.Switch(self.sel_in):
 326             with m.Case(In3Sel.RB):
 327                 # for M-Form shiftrot
 328                 comb += reg.data.eq(self.dec.RB)
 329                 comb += reg.ok.eq(1)
 330             with m.Case(In3Sel.RS):
 331                 comb += reg.data.eq(self.dec.RS)
 332                 comb += reg.ok.eq(1)
 333
 334         return m
 335
 336
 337 class DecodeOut(Elaboratable):
 338     """DecodeOut from instruction
 339
 340     decodes output register RA, RT or SPR
 341     """
 342
 343     def __init__(self, dec, regreduce_en):
 344         self.regreduce_en = regreduce_en
 345         if self.regreduce_en:
 346             SPR = SPRreduced
 347         else:
 348             SPR = SPRfull
 349         self.dec = dec
 350         self.sel_in = Signal(OutSel, reset_less=True)
 351         self.insn_in = Signal(32, reset_less=True)
 352         self.reg_out = Data(5, "reg_o")
 353         self.spr_out = Data(SPR, "spr_o")
 354         self.fast_out = Data(3, "fast_o")
 355
 356     def elaborate(self, platform):
 357         m = Module()
 358         comb = m.d.comb
 359         m.submodules.sprmap = sprmap = SPRMap(self.regreduce_en)
 360         op = self.dec.op
 361         reg = self.reg_out
 362
 363         # select Register out field
 364         with m.Switch(self.sel_in):
 365             with m.Case(OutSel.RT):
 366                 comb += reg.data.eq(self.dec.RT)
 367                 comb += reg.ok.eq(1)
 368             with m.Case(OutSel.RA):
 369                 comb += reg.data.eq(self.dec.RA)
 370                 comb += reg.ok.eq(1)
 371             with m.Case(OutSel.SPR):
 372                 spr = Signal(10, reset_less=True)
 373                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 374                 # MFSPR move to SPRs - needs mapping
 375                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 376                     comb += sprmap.spr_i.eq(spr)
 377                     comb += self.spr_out.eq(sprmap.spr_o)
 378                     comb += self.fast_out.eq(sprmap.fast_o)
 379
 380         # determine Fast Reg
 381         with m.Switch(op.internal_op):
 382
 383             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 384             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 385                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 386                     # constant: CTR
 387                     comb += self.fast_out.data.eq(FastRegsEnum.CTR)
 388                     comb += self.fast_out.ok.eq(1)
 389
 390             # RFID 1st spr (fast)
 391             with m.Case(MicrOp.OP_RFID):
 392                 comb += self.fast_out.data.eq(FastRegsEnum.SRR0)  # SRR0
 393                 comb += self.fast_out.ok.eq(1)
 394
 395         return m
 396
 397
 398 class DecodeOut2(Elaboratable):
 399     """DecodeOut2 from instruction
 400
 401     decodes output registers (2nd one).  note that RA is *implicit* below,
 402     which now causes problems with SVP64
 403
 404     TODO: SVP64 is a little more complex, here.  svp64 allows extending
 405     by one more destination by having one more EXTRA field.  RA-as-src
 406     is not the same as RA-as-dest.  limited in that it's the same first
 407     5 bits (from the v3.0B opcode), but still kinda cool.  mostly used
 408     for operations that have src-as-dest: mostly this is LD/ST-with-update
 409     but there are others.
 410     """
 411
 412     def __init__(self, dec):
 413         self.dec = dec
 414         self.sel_in = Signal(OutSel, reset_less=True)
 415         self.lk = Signal(reset_less=True)
 416         self.insn_in = Signal(32, reset_less=True)
 417         self.reg_out = Data(5, "reg_o2")
 418         self.fast_out = Data(3, "fast_o2")
 419
 420     def elaborate(self, platform):
 421         m = Module()
 422         comb = m.d.comb
 423         op = self.dec.op
 424         #m.submodules.svdec = svdec = SVP64RegExtra()
 425
 426         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
 427         #reg = Signal(5, reset_less=True)
 428
 429         if hasattr(self.dec.op, "upd"):
 430             # update mode LD/ST uses read-reg A also as an output
 431             with m.If(self.dec.op.upd == LDSTMode.update):
 432                 comb += self.reg_out.data.eq(self.dec.RA)
 433                 comb += self.reg_out.ok.eq(1)
 434
 435         # B, BC or BCREG: potential implicit register (LR) output
 436         # these give bl, bcl, bclrl, etc.
 437         with m.Switch(op.internal_op):
 438
 439             # BC* implicit register (LR)
 440             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 441                 with m.If(self.lk):  # "link" mode
 442                     comb += self.fast_out.data.eq(FastRegsEnum.LR)  # LR
 443                     comb += self.fast_out.ok.eq(1)
 444
 445             # RFID 2nd spr (fast)
 446             with m.Case(MicrOp.OP_RFID):
 447                 comb += self.fast_out.data.eq(FastRegsEnum.SRR1)  # SRR1
 448                 comb += self.fast_out.ok.eq(1)
 449
 450         return m
 451
 452
 453 class DecodeRC(Elaboratable):
 454     """DecodeRc from instruction
 455
 456     decodes Record bit Rc
 457     """
 458
 459     def __init__(self, dec):
 460         self.dec = dec
 461         self.sel_in = Signal(RC, reset_less=True)
 462         self.insn_in = Signal(32, reset_less=True)
 463         self.rc_out = Data(1, "rc")
 464
 465     def elaborate(self, platform):
 466         m = Module()
 467         comb = m.d.comb
 468
 469         # select Record bit out field
 470         with m.Switch(self.sel_in):
 471             with m.Case(RC.RC):
 472                 comb += self.rc_out.data.eq(self.dec.Rc)
 473                 comb += self.rc_out.ok.eq(1)
 474             with m.Case(RC.ONE):
 475                 comb += self.rc_out.data.eq(1)
 476                 comb += self.rc_out.ok.eq(1)
 477             with m.Case(RC.NONE):
 478                 comb += self.rc_out.data.eq(0)
 479                 comb += self.rc_out.ok.eq(1)
 480
 481         return m
 482
 483
 484 class DecodeOE(Elaboratable):
 485     """DecodeOE from instruction
 486
 487     decodes OE field: uses RC decode detection which might not be good
 488
 489     -- For now, use "rc" in the decode table to decide whether oe exists.
 490     -- This is not entirely correct architecturally: For mulhd and
 491     -- mulhdu, the OE field is reserved. It remains to be seen what an
 492     -- actual POWER9 does if we set it on those instructions, for now we
 493     -- test that further down when assigning to the multiplier oe input.
 494     """
 495
 496     def __init__(self, dec):
 497         self.dec = dec
 498         self.sel_in = Signal(RC, reset_less=True)
 499         self.insn_in = Signal(32, reset_less=True)
 500         self.oe_out = Data(1, "oe")
 501
 502     def elaborate(self, platform):
 503         m = Module()
 504         comb = m.d.comb
 505         op = self.dec.op
 506
 507         with m.Switch(op.internal_op):
 508
 509             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 510             # also rotate
 511             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 512             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 513             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 514                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 515                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 516                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 517                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 518                         MicrOp.OP_EXTSWSLI):
 519                 pass
 520
 521             # all other ops decode OE field
 522             with m.Default():
 523                 # select OE bit out field
 524                 with m.Switch(self.sel_in):
 525                     with m.Case(RC.RC):
 526                         comb += self.oe_out.data.eq(self.dec.OE)
 527                         comb += self.oe_out.ok.eq(1)
 528
 529         return m
 530
 531
 532 class DecodeCRIn(Elaboratable):
 533     """Decodes input CR from instruction
 534
 535     CR indices - insn fields - (not the data *in* the CR) require only 3
 536     bits because they refer to CR0-CR7
 537     """
 538
 539     def __init__(self, dec):
 540         self.dec = dec
 541         self.sel_in = Signal(CRInSel, reset_less=True)
 542         self.insn_in = Signal(32, reset_less=True)
 543         self.cr_bitfield = Data(3, "cr_bitfield")
 544         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 545         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 546         self.whole_reg = Data(8,  "cr_fxm")
 547         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 548
 549     def elaborate(self, platform):
 550         m = Module()
 551         comb = m.d.comb
 552         op = self.dec.op
 553         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 554                                                        reverse_o=True)
 555
 556         # zero-initialisation
 557         comb += self.cr_bitfield.ok.eq(0)
 558         comb += self.cr_bitfield_b.ok.eq(0)
 559         comb += self.cr_bitfield_o.ok.eq(0)
 560         comb += self.whole_reg.ok.eq(0)
 561         comb += self.sv_override.eq(0)
 562
 563         # select the relevant CR bitfields
 564         with m.Switch(self.sel_in):
 565             with m.Case(CRInSel.NONE):
 566                 pass  # No bitfield activated
 567             with m.Case(CRInSel.CR0):
 568                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 569                 comb += self.cr_bitfield.ok.eq(1)
 570                 comb += self.sv_override.eq(1)
 571             with m.Case(CRInSel.CR1):
 572                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 573                 comb += self.cr_bitfield.ok.eq(1)
 574                 comb += self.sv_override.eq(2)
 575             with m.Case(CRInSel.BI):
 576                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 577                 comb += self.cr_bitfield.ok.eq(1)
 578             with m.Case(CRInSel.BFA):
 579                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 580                 comb += self.cr_bitfield.ok.eq(1)
 581             with m.Case(CRInSel.BA_BB):
 582                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 583                 comb += self.cr_bitfield.ok.eq(1)
 584                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 585                 comb += self.cr_bitfield_b.ok.eq(1)
 586                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 587                 comb += self.cr_bitfield_o.ok.eq(1)
 588             with m.Case(CRInSel.BC):
 589                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 590                 comb += self.cr_bitfield.ok.eq(1)
 591             with m.Case(CRInSel.WHOLE_REG):
 592                 comb += self.whole_reg.ok.eq(1)
 593                 move_one = Signal(reset_less=True)
 594                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 595                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 596                     # must one-hot the FXM field
 597                     comb += ppick.i.eq(self.dec.FXM)
 598                     comb += self.whole_reg.data.eq(ppick.o)
 599                 with m.Else():
 600                     # otherwise use all of it
 601                     comb += self.whole_reg.data.eq(0xff)
 602
 603         return m
 604
 605
 606 class DecodeCROut(Elaboratable):
 607     """Decodes input CR from instruction
 608
 609     CR indices - insn fields - (not the data *in* the CR) require only 3
 610     bits because they refer to CR0-CR7
 611     """
 612
 613     def __init__(self, dec):
 614         self.dec = dec
 615         self.rc_in = Signal(reset_less=True)
 616         self.sel_in = Signal(CROutSel, reset_less=True)
 617         self.insn_in = Signal(32, reset_less=True)
 618         self.cr_bitfield = Data(3, "cr_bitfield")
 619         self.whole_reg = Data(8,  "cr_fxm")
 620         self.sv_override = Signal(2, reset_less=True) # do not do EXTRA spec
 621
 622     def elaborate(self, platform):
 623         m = Module()
 624         comb = m.d.comb
 625         op = self.dec.op
 626         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 627                                                        reverse_o=True)
 628
 629         comb += self.cr_bitfield.ok.eq(0)
 630         comb += self.whole_reg.ok.eq(0)
 631         comb += self.sv_override.eq(0)
 632
 633         # please note these MUST match (setting of cr_bitfield.ok) exactly
 634         # with write_cr0 below in PowerDecoder2.  the reason it's separated
 635         # is to avoid having duplicate copies of DecodeCROut in multiple
 636         # PowerDecoderSubsets.  register decoding should be a one-off in
 637         # PowerDecoder2.  see https://bugs.libre-soc.org/show_bug.cgi?id=606
 638
 639         with m.Switch(self.sel_in):
 640             with m.Case(CROutSel.NONE):
 641                 pass  # No bitfield activated
 642             with m.Case(CROutSel.CR0):
 643                 comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering)
 644                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 645                 comb += self.sv_override.eq(1)
 646             with m.Case(CROutSel.CR1):
 647                 comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering)
 648                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 649                 comb += self.sv_override.eq(2)
 650             with m.Case(CROutSel.BF):
 651                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 652                 comb += self.cr_bitfield.ok.eq(1)
 653             with m.Case(CROutSel.BT):
 654                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 655                 comb += self.cr_bitfield.ok.eq(1)
 656             with m.Case(CROutSel.WHOLE_REG):
 657                 comb += self.whole_reg.ok.eq(1)
 658                 move_one = Signal(reset_less=True)
 659                 comb += move_one.eq(self.insn_in[20])
 660                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 661                     with m.If(move_one):
 662                         # must one-hot the FXM field
 663                         comb += ppick.i.eq(self.dec.FXM)
 664                         with m.If(ppick.en_o):
 665                             comb += self.whole_reg.data.eq(ppick.o)
 666                         with m.Else():
 667                             comb += self.whole_reg.data.eq(0b00000001) # CR7
 668                     with m.Else():
 669                         comb += self.whole_reg.data.eq(self.dec.FXM)
 670                 with m.Else():
 671                     # otherwise use all of it
 672                     comb += self.whole_reg.data.eq(0xff)
 673
 674         return m
 675
 676 # dictionary of Input Record field names that, if they exist,
 677 # will need a corresponding CSV Decoder file column (actually, PowerOp)
 678 # to be decoded (this includes the single bit names)
 679 record_names = {'insn_type': 'internal_op',
 680                 'fn_unit': 'function_unit',
 681                 'rc': 'rc_sel',
 682                 'oe': 'rc_sel',
 683                 'zero_a': 'in1_sel',
 684                 'imm_data': 'in2_sel',
 685                 'invert_in': 'inv_a',
 686                 'invert_out': 'inv_out',
 687                 'rc': 'cr_out',
 688                 'oe': 'cr_in',
 689                 'output_carry': 'cry_out',
 690                 'input_carry': 'cry_in',
 691                 'is_32bit': 'is_32b',
 692                 'is_signed': 'sgn',
 693                 'lk': 'lk',
 694                 'data_len': 'ldst_len',
 695                 'byte_reverse': 'br',
 696                 'sign_extend': 'sgn_ext',
 697                 'ldst_mode': 'upd',
 698                 }
 699
 700
 701 class PowerDecodeSubset(Elaboratable):
 702     """PowerDecodeSubset: dynamic subset decoder
 703
 704     only fields actually requested are copied over. hence, "subset" (duh).
 705     """
 706     def __init__(self, dec, opkls=None, fn_name=None, final=False, state=None,
 707                             svp64_en=True, regreduce_en=False):
 708
 709         self.svp64_en = svp64_en
 710         self.regreduce_en = regreduce_en
 711         if svp64_en:
 712             self.sv_rm = SVP64Rec(name="dec_svp64") # SVP64 RM field
 713         self.sv_a_nz = Signal(1)
 714         self.final = final
 715         self.opkls = opkls
 716         self.fn_name = fn_name
 717         if opkls is None:
 718             opkls = Decode2ToOperand
 719         self.do = opkls(fn_name)
 720         col_subset = self.get_col_subset(self.do)
 721
 722         # only needed for "main" PowerDecode2
 723         if not self.final:
 724             self.e = Decode2ToExecute1Type(name=self.fn_name, do=self.do,
 725                                            regreduce_en=regreduce_en)
 726
 727         # create decoder if one not already given
 728         if dec is None:
 729             dec = create_pdecode(name=fn_name, col_subset=col_subset,
 730                                       row_subset=self.rowsubsetfn)
 731         self.dec = dec
 732
 733         # state information needed by the Decoder
 734         if state is None:
 735             state = CoreState("dec2")
 736         self.state = state
 737
 738     def get_col_subset(self, do):
 739         subset = { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
 740         for k, v in record_names.items():
 741             if hasattr(do, k):
 742                 subset.add(v)
 743         print ("get_col_subset", self.fn_name, do.fields, subset)
 744         return subset
 745
 746     def rowsubsetfn(self, opcode, row):
 747         """select per-Function-Unit subset of opcodes to be processed
 748
 749         normally this just looks at the "unit" column.  MMU is different
 750         in that it processes specific SPR set/get operations that the SPR
 751         pipeline should not.
 752         """
 753         return (row['unit'] == self.fn_name or
 754                 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
 755                 # by the MMU pipeline so we direct those opcodes to MMU **AND**
 756                 # SPR pipelines, then selectively weed out the SPRs that should
 757                 # or should not not go to each pipeline, further down.
 758                 # really this should be done by modifying the CSV syntax
 759                 # to support multiple tasks (unit column multiple entries)
 760                 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
 761                (self.fn_name == 'MMU' and row['unit'] == 'SPR' and
 762                 row['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
 763                 )
 764
 765     def ports(self):
 766         ports = self.dec.ports() + self.e.ports()
 767         if self.svp64_en:
 768             ports += self.sv_rm.ports()
 769         return ports
 770
 771     def needs_field(self, field, op_field):
 772         if self.final:
 773             do = self.do
 774         else:
 775             do = self.e_tmp.do
 776         return hasattr(do, field) and self.op_get(op_field) is not None
 777
 778     def do_copy(self, field, val, final=False):
 779         if final or self.final:
 780             do = self.do
 781         else:
 782             do = self.e_tmp.do
 783         if hasattr(do, field) and val is not None:
 784             return getattr(do, field).eq(val)
 785         return []
 786
 787     def op_get(self, op_field):
 788         return getattr(self.dec.op, op_field, None)
 789
 790     def elaborate(self, platform):
 791         if self.regreduce_en:
 792             SPR = SPRreduced
 793         else:
 794             SPR = SPRfull
 795         m = Module()
 796         comb = m.d.comb
 797         state = self.state
 798         op, do = self.dec.op, self.do
 799         msr, cia = state.msr, state.pc
 800         # fill in for a normal instruction (not an exception)
 801         # copy over if non-exception, non-privileged etc. is detected
 802         if not self.final:
 803             if self.fn_name is None:
 804                 name = "tmp"
 805             else:
 806                 name = self.fn_name + "tmp"
 807             self.e_tmp = Decode2ToExecute1Type(name=name, opkls=self.opkls,
 808                                            regreduce_en=self.regreduce_en)
 809
 810         # set up submodule decoders
 811         m.submodules.dec = self.dec
 812         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
 813         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 814
 815         # copy instruction through...
 816         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
 817             comb += i.eq(self.dec.opcode_in)
 818
 819         # ...and subdecoders' input fields
 820         comb += dec_rc.sel_in.eq(op.rc_sel)
 821         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 822
 823         # copy "state" over
 824         comb += self.do_copy("msr", msr)
 825         comb += self.do_copy("cia", cia)
 826
 827         # set up instruction type
 828         # no op: defaults to OP_ILLEGAL
 829         internal_op = self.op_get("internal_op")
 830         comb += self.do_copy("insn_type", internal_op)
 831
 832         # function unit for decoded instruction: requires minor redirect
 833         # for SPR set/get
 834         fn = self.op_get("function_unit")
 835         spr = Signal(10, reset_less=True)
 836         comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 837
 838         # Microwatt doesn't implement the partition table
 839         # instead has PRTBL register (SPR) to point to process table
 840         is_spr_mv = Signal()
 841         is_mmu_spr = Signal()
 842         comb += is_spr_mv.eq((internal_op == MicrOp.OP_MTSPR) |
 843                              (internal_op == MicrOp.OP_MFSPR))
 844         comb += is_mmu_spr.eq((spr == SPR.DSISR.value) |
 845                               (spr == SPR.DAR.value) |
 846                               (spr == SPR.PRTBL.value) |
 847                               (spr == SPR.PIDR.value))
 848         # MMU must receive MMU SPRs
 849         with m.If(is_spr_mv & (fn == Function.SPR) & is_mmu_spr):
 850             comb += self.do_copy("fn_unit", Function.NONE)
 851             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 852         # SPR pipe must *not* receive MMU SPRs
 853         with m.Elif(is_spr_mv & (fn == Function.MMU) & ~is_mmu_spr):
 854             comb += self.do_copy("fn_unit", Function.NONE)
 855             comb += self.do_copy("insn_type", MicrOp.OP_ILLEGAL)
 856         # all others ok
 857         with m.Else():
 858             comb += self.do_copy("fn_unit", fn)
 859
 860         # immediates
 861         if self.needs_field("zero_a", "in1_sel"):
 862             m.submodules.dec_ai = dec_ai = DecodeAImm(self.dec)
 863             comb += dec_ai.sv_nz.eq(self.sv_a_nz)
 864             comb += dec_ai.sel_in.eq(op.in1_sel)
 865             comb += self.do_copy("zero_a", dec_ai.immz_out)  # RA==0 detected
 866         if self.needs_field("imm_data", "in2_sel"):
 867             m.submodules.dec_bi = dec_bi = DecodeBImm(self.dec)
 868             comb += dec_bi.sel_in.eq(op.in2_sel)
 869             comb += self.do_copy("imm_data", dec_bi.imm_out) # imm in RB
 870
 871         # rc and oe out
 872         comb += self.do_copy("rc", dec_rc.rc_out)
 873         comb += self.do_copy("oe", dec_oe.oe_out)
 874
 875         # CR in/out - note: these MUST match with what happens in
 876         # DecodeCROut!
 877         rc_out = self.dec_rc.rc_out.data
 878         with m.Switch(op.cr_out):
 879             with m.Case(CROutSel.CR0, CROutSel.CR1):
 880                 comb += self.do_copy("write_cr0", rc_out) # only when RC=1
 881             with m.Case(CROutSel.BF, CROutSel.BT):
 882                 comb += self.do_copy("write_cr0", 1)
 883
 884         comb += self.do_copy("input_cr", self.op_get("cr_in"))   # CR in
 885         comb += self.do_copy("output_cr", self.op_get("cr_out"))  # CR out
 886
 887         # decoded/selected instruction flags
 888         comb += self.do_copy("data_len", self.op_get("ldst_len"))
 889         comb += self.do_copy("invert_in", self.op_get("inv_a"))
 890         comb += self.do_copy("invert_out", self.op_get("inv_out"))
 891         comb += self.do_copy("input_carry", self.op_get("cry_in"))
 892         comb += self.do_copy("output_carry", self.op_get("cry_out"))
 893         comb += self.do_copy("is_32bit", self.op_get("is_32b"))
 894         comb += self.do_copy("is_signed", self.op_get("sgn"))
 895         lk = self.op_get("lk")
 896         if lk is not None:
 897             with m.If(lk):
 898                 comb += self.do_copy("lk", self.dec.LK)  # XXX TODO: accessor
 899
 900         comb += self.do_copy("byte_reverse", self.op_get("br"))
 901         comb += self.do_copy("sign_extend", self.op_get("sgn_ext"))
 902         comb += self.do_copy("ldst_mode", self.op_get("upd"))  # LD/ST mode
 903
 904         return m
 905
 906
 907 class PowerDecode2(PowerDecodeSubset):
 908     """PowerDecode2: the main instruction decoder.
 909
 910     whilst PowerDecode is responsible for decoding the actual opcode, this
 911     module encapsulates further specialist, sparse information and
 912     expansion of fields that is inconvenient to have in the CSV files.
 913     for example: the encoding of the immediates, which are detected
 914     and expanded out to their full value from an annotated (enum)
 915     representation.
 916
 917     implicit register usage is also set up, here.  for example: OP_BC
 918     requires implicitly reading CTR, OP_RFID requires implicitly writing
 919     to SRR1 and so on.
 920
 921     in addition, PowerDecoder2 is responsible for detecting whether
 922     instructions are illegal (or privileged) or not, and instead of
 923     just leaving at that, *replacing* the instruction to execute with
 924     a suitable alternative (trap).
 925
 926     LDSTExceptions are done the cycle _after_ they're detected (after
 927     they come out of LDSTCompUnit).  basically despite the instruction
 928     being decoded, the results of the decode are completely ignored
 929     and "exception.happened" used to set the "actual" instruction to
 930     "OP_TRAP".  the LDSTException data structure gets filled in,
 931     in the CompTrapOpSubset and that's what it fills in SRR.
 932
 933     to make this work, TestIssuer must notice "exception.happened"
 934     after the (failed) LD/ST and copies the LDSTException info from
 935     the output, into here (PowerDecoder2).  without incrementing PC.
 936     """
 937
 938     def __init__(self, dec, opkls=None, fn_name=None, final=False,
 939                             state=None, svp64_en=True, regreduce_en=False):
 940         super().__init__(dec, opkls, fn_name, final, state, svp64_en,
 941                          regreduce_en=False)
 942         self.ldst_exc = LDSTException("dec2_exc")
 943
 944         if self.svp64_en:
 945             self.cr_out_isvec = Signal(1, name="cr_out_isvec")
 946             self.cr_in_isvec = Signal(1, name="cr_in_isvec")
 947             self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec")
 948             self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec")
 949             self.in1_isvec = Signal(1, name="reg_a_isvec")
 950             self.in2_isvec = Signal(1, name="reg_b_isvec")
 951             self.in3_isvec = Signal(1, name="reg_c_isvec")
 952             self.o_isvec = Signal(1, name="reg_o_isvec")
 953             self.o2_isvec = Signal(1, name="reg_o2_isvec")
 954             self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector
 955             self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector
 956             self.loop_continue = Signal(1, name="loop_continue")
 957             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
 958         else:
 959             self.no_in_vec = Const(1, 1)
 960             self.no_out_vec = Const(1, 1)
 961             self.loop_continue = Const(0, 1)
 962
 963     def get_col_subset(self, opkls):
 964         subset = super().get_col_subset(opkls)
 965         subset.add("asmcode")
 966         subset.add("in1_sel")
 967         subset.add("in2_sel")
 968         subset.add("in3_sel")
 969         subset.add("out_sel")
 970         if self.svp64_en:
 971             subset.add("sv_in1")
 972             subset.add("sv_in2")
 973             subset.add("sv_in3")
 974             subset.add("sv_out")
 975             subset.add("sv_out2")
 976             subset.add("sv_cr_in")
 977             subset.add("sv_cr_out")
 978             subset.add("SV_Etype")
 979             subset.add("SV_Ptype")
 980         subset.add("lk")
 981         subset.add("internal_op")
 982         subset.add("form")
 983         return subset
 984
 985     def elaborate(self, platform):
 986         m = super().elaborate(platform)
 987         comb = m.d.comb
 988         state = self.state
 989         e_out, op, do_out = self.e, self.dec.op, self.e.do
 990         dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
 991         rc_out = self.dec_rc.rc_out.data
 992         e = self.e_tmp
 993         do = e.do
 994
 995         # fill in for a normal instruction (not an exception)
 996         # copy over if non-exception, non-privileged etc. is detected
 997
 998         # set up submodule decoders
 999         m.submodules.dec_a = dec_a = DecodeA(self.dec, self.regreduce_en)
1000         m.submodules.dec_b = dec_b = DecodeB(self.dec)
1001         m.submodules.dec_c = dec_c = DecodeC(self.dec)
1002         m.submodules.dec_o = dec_o = DecodeOut(self.dec, self.regreduce_en)
1003         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
1004         m.submodules.dec_cr_in = self.dec_cr_in = DecodeCRIn(self.dec)
1005         m.submodules.dec_cr_out = self.dec_cr_out = DecodeCROut(self.dec)
1006         comb += dec_a.sv_nz.eq(self.sv_a_nz)
1007
1008         if self.svp64_en:
1009             # and SVP64 Extra decoders
1010             m.submodules.crout_svdec = crout_svdec = SVP64CRExtra()
1011             m.submodules.crin_svdec = crin_svdec = SVP64CRExtra()
1012             m.submodules.crin_svdec_b = crin_svdec_b = SVP64CRExtra()
1013             m.submodules.crin_svdec_o = crin_svdec_o = SVP64CRExtra()
1014             m.submodules.in1_svdec = in1_svdec = SVP64RegExtra()
1015             m.submodules.in2_svdec = in2_svdec = SVP64RegExtra()
1016             m.submodules.in3_svdec = in3_svdec = SVP64RegExtra()
1017             m.submodules.o_svdec = o_svdec = SVP64RegExtra()
1018             m.submodules.o2_svdec = o2_svdec = SVP64RegExtra()
1019
1020             # debug access to crout_svdec (used in get_pdecode_cr_out)
1021             self.crout_svdec = crout_svdec
1022
1023             # and SVP64 RM mode decoder
1024             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
1025
1026         # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1027         reg = Signal(5, reset_less=True)
1028
1029         # copy instruction through...
1030         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
1031                   self.dec_cr_in.insn_in, self.dec_cr_out.insn_in,
1032                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in]:
1033             comb += i.eq(self.dec.opcode_in)
1034
1035         # CR setup
1036         comb += self.dec_cr_in.sel_in.eq(op.cr_in)
1037         comb += self.dec_cr_out.sel_in.eq(op.cr_out)
1038         comb += self.dec_cr_out.rc_in.eq(rc_out)
1039
1040         # CR register info
1041         comb += self.do_copy("read_cr_whole", self.dec_cr_in.whole_reg)
1042         comb += self.do_copy("write_cr_whole", self.dec_cr_out.whole_reg)
1043
1044         # ...and subdecoders' input fields
1045         comb += dec_a.sel_in.eq(op.in1_sel)
1046         comb += dec_b.sel_in.eq(op.in2_sel)
1047         comb += dec_c.sel_in.eq(op.in3_sel)
1048         comb += dec_o.sel_in.eq(op.out_sel)
1049         comb += dec_o2.sel_in.eq(op.out_sel)
1050         if hasattr(do, "lk"):
1051             comb += dec_o2.lk.eq(do.lk)
1052
1053         if self.svp64_en:
1054             # now do the SVP64 munging.  op.SV_Etype and op.sv_in1 comes from
1055             # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1056             # which in turn were auto-generated by sv_analysis.py
1057             extra = self.sv_rm.extra            # SVP64 extra bits 10:18
1058
1059             #######
1060             # CR out
1061             comb += crout_svdec.idx.eq(op.sv_cr_out)  # SVP64 CR out
1062             comb += self.cr_out_isvec.eq(crout_svdec.isvec)
1063
1064             #######
1065             # CR in - selection slightly different due to shared CR field sigh
1066             cr_a_idx = Signal(SVEXTRA)
1067             cr_b_idx = Signal(SVEXTRA)
1068
1069             # these change slightly, when decoding BA/BB.  really should have
1070             # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1071             comb += cr_a_idx.eq(op.sv_cr_in)
1072             comb += cr_b_idx.eq(SVEXTRA.NONE)
1073             with m.If(op.sv_cr_in == SVEXTRA.Idx_1_2.value):
1074                 comb += cr_a_idx.eq(SVEXTRA.Idx1)
1075                 comb += cr_b_idx.eq(SVEXTRA.Idx2)
1076
1077             comb += self.cr_in_isvec.eq(crin_svdec.isvec)
1078             comb += self.cr_in_b_isvec.eq(crin_svdec_b.isvec)
1079             comb += self.cr_in_o_isvec.eq(crin_svdec_o.isvec)
1080
1081             # indices are slightly different, BA/BB mess sorted above
1082             comb += crin_svdec.idx.eq(cr_a_idx)       # SVP64 CR in A
1083             comb += crin_svdec_b.idx.eq(cr_b_idx)     # SVP64 CR in B
1084             comb += crin_svdec_o.idx.eq(op.sv_cr_out) # SVP64 CR out
1085
1086             # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1087             srcstep = Signal.like(self.state.svstate.srcstep)
1088             dststep = Signal.like(self.state.svstate.dststep)
1089             comb += srcstep.eq(self.state.svstate.srcstep)
1090             comb += dststep.eq(self.state.svstate.dststep)
1091
1092             # registers a, b, c and out and out2 (LD/ST EA)
1093             for to_reg, fromreg, svdec, out in (
1094                 (e.read_reg1, dec_a.reg_out, in1_svdec, False),
1095                 (e.read_reg2, dec_b.reg_out, in2_svdec, False),
1096                 (e.read_reg3, dec_c.reg_out, in3_svdec, False),
1097                 (e.write_reg, dec_o.reg_out, o_svdec, True),
1098                 (e.write_ea, dec_o2.reg_out, o2_svdec, True)):
1099                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1100                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1101                 comb += svdec.reg_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1102                 comb += to_reg.ok.eq(fromreg.ok)
1103                 # detect if Vectorised: add srcstep/dststep if yes.
1104                 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1105                 with m.If(svdec.isvec):
1106                     step = dststep if out else srcstep
1107                     comb += to_reg.data.eq(step+svdec.reg_out)
1108                 with m.Else():
1109                     comb += to_reg.data.eq(svdec.reg_out)
1110
1111             comb += in1_svdec.idx.eq(op.sv_in1)  # SVP64 reg #1 (in1_sel)
1112             comb += in2_svdec.idx.eq(op.sv_in2)  # SVP64 reg #2 (in2_sel)
1113             comb += in3_svdec.idx.eq(op.sv_in3)  # SVP64 reg #3 (in3_sel)
1114             comb += o_svdec.idx.eq(op.sv_out)    # SVP64 output (out_sel)
1115             comb += o2_svdec.idx.eq(op.sv_out2)  # SVP64 output (implicit)
1116             # XXX TODO - work out where this should come from.  the problem is
1117             # that LD-with-update is implied (computed from "is instruction in
1118             # "update mode" rather than specified cleanly as its own CSV column
1119
1120             # output reg-is-vectorised (and when no in/out is vectorised)
1121             comb += self.in1_isvec.eq(in1_svdec.isvec)
1122             comb += self.in2_isvec.eq(in2_svdec.isvec)
1123             comb += self.in3_isvec.eq(in3_svdec.isvec)
1124             comb += self.o_isvec.eq(o_svdec.isvec)
1125             comb += self.o2_isvec.eq(o2_svdec.isvec)
1126             # TODO add SPRs here.  must be True when *all* are scalar
1127             l = map(lambda svdec: svdec.isvec, [in1_svdec, in2_svdec, in3_svdec,
1128                                         crin_svdec, crin_svdec_b, crin_svdec_o])
1129             comb += self.no_in_vec.eq(~Cat(*l).bool()) # all input scalar
1130             l = map(lambda svdec: svdec.isvec, [o2_svdec, o_svdec, crout_svdec])
1131             comb += self.no_out_vec.eq(~Cat(*l).bool()) # all output scalar
1132             # now create a general-purpose "test" as to whether looping
1133             # should continue.  this doesn't include predication bit-tests
1134             loop = self.loop_continue
1135             with m.Switch(op.SV_Ptype):
1136                 with m.Case(SVPtype.P2.value):
1137                     # twin-predication
1138                     # TODO: *and cache-inhibited LD/ST!*
1139                     comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
1140                 with m.Case(SVPtype.P1.value):
1141                     # single-predication, test relies on dest only
1142                     comb += loop.eq(~self.no_out_vec)
1143                 with m.Default():
1144                     # not an SV operation, no looping
1145                     comb += loop.eq(0)
1146
1147             # condition registers (CR)
1148             for to_reg, cr, name, svdec, out in (
1149                 (e.read_cr1, self.dec_cr_in, "cr_bitfield", crin_svdec, 0),
1150                 (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", crin_svdec_b, 0),
1151                 (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", crin_svdec_o, 0),
1152                 (e.write_cr, self.dec_cr_out, "cr_bitfield", crout_svdec, 1)):
1153                 fromreg = getattr(cr, name)
1154                 comb += svdec.extra.eq(extra)        # EXTRA field of SVP64 RM
1155                 comb += svdec.etype.eq(op.SV_Etype)  # EXTRA2/3 for this insn
1156                 comb += svdec.cr_in.eq(fromreg.data) # 3-bit (CR0/BC/BFA)
1157                 with m.If(svdec.isvec):
1158                     # check if this is CR0 or CR1: treated differently
1159                     # (does not "listen" to EXTRA2/3 spec for a start)
1160                     # also: the CRs start from completely different locations
1161                     step = dststep if out else srcstep
1162                     with m.If(cr.sv_override == 1): # CR0
1163                         offs = SVP64CROffs.CR0
1164                         comb += to_reg.data.eq(step+offs)
1165                     with m.Elif(cr.sv_override == 2): # CR1
1166                         offs = SVP64CROffs.CR1
1167                         comb += to_reg.data.eq(step+1)
1168                     with m.Else():
1169                         comb += to_reg.data.eq(step+svdec.cr_out) # 7-bit out
1170                 with m.Else():
1171                     comb += to_reg.data.eq(svdec.cr_out) # 7-bit output
1172                 comb += to_reg.ok.eq(fromreg.ok)
1173
1174             # sigh must determine if RA is nonzero (7 bit)
1175             comb += self.sv_a_nz.eq(e.read_reg1.data != Const(0, 7))
1176         else:
1177             # connect up to/from read/write GPRs
1178             for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out),
1179                                     (e.read_reg2, dec_b.reg_out),
1180                                     (e.read_reg3, dec_c.reg_out),
1181                                     (e.write_reg, dec_o.reg_out),
1182                                     (e.write_ea, dec_o2.reg_out)):
1183                 comb += to_reg.data.eq(fromreg.data)
1184                 comb += to_reg.ok.eq(fromreg.ok)
1185
1186             # connect up to/from read/write CRs
1187             for to_reg, cr, name in (
1188                         (e.read_cr1, self.dec_cr_in, "cr_bitfield", ),
1189                         (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ),
1190                         (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ),
1191                         (e.write_cr, self.dec_cr_out, "cr_bitfield", )):
1192                 fromreg = getattr(cr, name)
1193                 comb += to_reg.data.eq(fromreg.data)
1194                 comb += to_reg.ok.eq(fromreg.ok)
1195
1196         # SPRs out
1197         comb += e.read_spr1.eq(dec_a.spr_out)
1198         comb += e.write_spr.eq(dec_o.spr_out)
1199
1200         # Fast regs out
1201         comb += e.read_fast1.eq(dec_a.fast_out)
1202         comb += e.read_fast2.eq(dec_b.fast_out)
1203         comb += e.write_fast1.eq(dec_o.fast_out)
1204         comb += e.write_fast2.eq(dec_o2.fast_out)
1205
1206         if self.svp64_en:
1207             # connect up SVP64 RM Mode decoding
1208             fn = self.op_get("function_unit")
1209             comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type
1210             comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
1211             comb += rm_dec.rc_in.eq(rc_out) # Rc=1
1212             comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
1213
1214         # sigh this is exactly the sort of thing for which the
1215         # decoder is designed to not need.  MTSPR, MFSPR and others need
1216         # access to the XER bits.  however setting e.oe is not appropriate
1217         with m.If(op.internal_op == MicrOp.OP_MFSPR):
1218             comb += e.xer_in.eq(0b111) # SO, CA, OV
1219         with m.If(op.internal_op == MicrOp.OP_CMP):
1220             comb += e.xer_in.eq(1<<XERRegsEnum.SO) # SO
1221         with m.If(op.internal_op == MicrOp.OP_MTSPR):
1222             comb += e.xer_out.eq(1)
1223
1224         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1225         with m.If(op.internal_op == MicrOp.OP_TRAP):
1226             # *DO NOT* call self.trap here.  that would reset absolutely
1227             # everything including destroying read of RA and RB.
1228             comb += self.do_copy("trapaddr", 0x70) # strip first nibble
1229
1230         ####################
1231         # ok so the instruction's been decoded, blah blah, however
1232         # now we need to determine if it's actually going to go ahead...
1233         # *or* if in fact it's a privileged operation, whether there's
1234         # an external interrupt, etc. etc.  this is a simple priority
1235         # if-elif-elif sequence.  decrement takes highest priority,
1236         # EINT next highest, privileged operation third.
1237
1238         # check if instruction is privileged
1239         is_priv_insn = instr_is_priv(m, op.internal_op, e.do.insn)
1240
1241         # different IRQ conditions
1242         ext_irq_ok = Signal()
1243         dec_irq_ok = Signal()
1244         priv_ok = Signal()
1245         illeg_ok = Signal()
1246         ldst_exc = self.ldst_exc
1247
1248         comb += ext_irq_ok.eq(ext_irq & msr[MSR.EE]) # v3.0B p944 (MSR.EE)
1249         comb += dec_irq_ok.eq(dec_spr[63] & msr[MSR.EE]) # 6.5.11 p1076
1250         comb += priv_ok.eq(is_priv_insn & msr[MSR.PR])
1251         comb += illeg_ok.eq(op.internal_op == MicrOp.OP_ILLEGAL)
1252
1253         # LD/ST exceptions.  TestIssuer copies the exception info at us
1254         # after a failed LD/ST.
1255         with m.If(ldst_exc.happened):
1256             with m.If(ldst_exc.alignment):
1257                 self.trap(m, TT.PRIV, 0x600)
1258             with m.Elif(ldst_exc.instr_fault):
1259                 with m.If(ldst_exc.segment_fault):
1260                     self.trap(m, TT.PRIV, 0x480)
1261                 with m.Else():
1262                     # pass exception info to trap to create SRR1
1263                     self.trap(m, TT.MEMEXC, 0x400, ldst_exc)
1264             with m.Else():
1265                 with m.If(ldst_exc.segment_fault):
1266                     self.trap(m, TT.PRIV, 0x380)
1267                 with m.Else():
1268                     self.trap(m, TT.PRIV, 0x300)
1269
1270         # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1271         with m.Elif(dec_irq_ok):
1272             self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
1273
1274         # external interrupt? only if MSR.EE set
1275         with m.Elif(ext_irq_ok):
1276             self.trap(m, TT.EINT, 0x500)
1277
1278         # privileged instruction trap
1279         with m.Elif(priv_ok):
1280             self.trap(m, TT.PRIV, 0x700)
1281
1282         # illegal instruction must redirect to trap. this is done by
1283         # *overwriting* the decoded instruction and starting again.
1284         # (note: the same goes for interrupts and for privileged operations,
1285         # just with different trapaddr and traptype)
1286         with m.Elif(illeg_ok):
1287             # illegal instruction trap
1288             self.trap(m, TT.ILLEG, 0x700)
1289
1290         # no exception, just copy things to the output
1291         with m.Else():
1292             comb += e_out.eq(e)
1293
1294         ####################
1295         # follow-up after trap/irq to set up SRR0/1
1296
1297         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1298         # Note: OP_SC could actually be modified to just be a trap
1299         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
1300                   (do_out.insn_type == MicrOp.OP_SC)):
1301             # TRAP write fast1 = SRR0
1302             comb += e_out.write_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1303             comb += e_out.write_fast1.ok.eq(1)
1304             # TRAP write fast2 = SRR1
1305             comb += e_out.write_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1306             comb += e_out.write_fast2.ok.eq(1)
1307
1308         # RFID: needs to read SRR0/1
1309         with m.If(do_out.insn_type == MicrOp.OP_RFID):
1310             # TRAP read fast1 = SRR0
1311             comb += e_out.read_fast1.data.eq(FastRegsEnum.SRR0)  # SRR0
1312             comb += e_out.read_fast1.ok.eq(1)
1313             # TRAP read fast2 = SRR1
1314             comb += e_out.read_fast2.data.eq(FastRegsEnum.SRR1)  # SRR1
1315             comb += e_out.read_fast2.ok.eq(1)
1316
1317         # annoying simulator bug
1318         if hasattr(e_out, "asmcode") and hasattr(self.dec.op, "asmcode"):
1319             comb += e_out.asmcode.eq(self.dec.op.asmcode)
1320
1321         return m
1322
1323     def trap(self, m, traptype, trapaddr, ldst_exc=None):
1324         """trap: this basically "rewrites" the decoded instruction as a trap
1325         """
1326         comb = m.d.comb
1327         op, e = self.dec.op, self.e
1328         comb += e.eq(0)  # reset eeeeeverything
1329
1330         # start again
1331         comb += self.do_copy("insn", self.dec.opcode_in, True)
1332         comb += self.do_copy("insn_type", MicrOp.OP_TRAP, True)
1333         comb += self.do_copy("fn_unit", Function.TRAP, True)
1334         comb += self.do_copy("trapaddr", trapaddr >> 4, True) # bottom 4 bits
1335         comb += self.do_copy("traptype", traptype, True)  # request type
1336         comb += self.do_copy("ldst_exc", ldst_exc, True)  # request type
1337         comb += self.do_copy("msr", self.state.msr, True) # copy of MSR "state"
1338         comb += self.do_copy("cia", self.state.pc, True)  # copy of PC "state"
1339
1340
1341
1342 def get_rdflags(e, cu):
1343     rdl = []
1344     for idx in range(cu.n_src):
1345         regfile, regname, _ = cu.get_in_spec(idx)
1346         rdflag, read = regspec_decode_read(e, regfile, regname)
1347         rdl.append(rdflag)
1348     print("rdflags", rdl)
1349     return Cat(*rdl)
1350
1351
1352 if __name__ == '__main__':
1353     pdecode = create_pdecode()
1354     dec2 = PowerDecode2(pdecode)
1355     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
1356     with open("dec2.il", "w") as f:
1357         f.write(vl)