1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from nmutil
.util
import sel
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from openpower
.exceptions
import LDSTException
19 from openpower
.decoder
.power_svp64_prefix
import SVP64PrefixDecoder
20 from openpower
.decoder
.power_svp64_extra
import SVP64CRExtra
, SVP64RegExtra
21 from openpower
.decoder
.power_svp64_rm
import (SVP64RMModeDecode
,
22 sv_input_record_layout
,
24 from openpower
.sv
.svp64
import SVP64Rec
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_decoder
import (create_pdecode
,
28 create_pdecode_svp64_ldst
,
30 from openpower
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
32 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
33 OutSel
, SPRfull
, SPRreduced
,
34 RC
, SVP64LDSTmode
, LDSTMode
,
35 SVEXTRA
, SVEtype
, SVPtype
)
36 from openpower
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
39 from openpower
.consts
import (MSR
, SPEC
, EXTRA2
, EXTRA3
, SVP64P
, field
,
40 SPEC_SIZE
, SPECb
, SPEC_AUG_SIZE
, SVP64CROffs
,
41 FastRegsEnum
, XERRegsEnum
, TT
)
43 from openpower
.state
import CoreState
44 from openpower
.util
import (spr_to_fast
, log
)
47 def decode_spr_num(spr
):
48 return Cat(spr
[5:10], spr
[0:5])
51 def instr_is_priv(m
, op
, insn
):
52 """determines if the instruction is privileged or not
55 is_priv_insn
= Signal(reset_less
=True)
57 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
58 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
59 comb
+= is_priv_insn
.eq(1)
60 with m
.Case(MicrOp
.OP_TLBIE
):
61 comb
+= is_priv_insn
.eq(1)
62 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
63 with m
.If(insn
[20]): # field XFX.spr[-1] i think
64 comb
+= is_priv_insn
.eq(1)
68 class SPRMap(Elaboratable
):
69 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
72 def __init__(self
, regreduce_en
):
73 self
.regreduce_en
= regreduce_en
79 self
.spr_i
= Signal(10, reset_less
=True)
80 self
.spr_o
= Data(SPR
, name
="spr_o")
81 self
.fast_o
= Data(3, name
="fast_o")
83 def elaborate(self
, platform
):
89 with m
.Switch(self
.spr_i
):
90 for i
, x
in enumerate(SPR
):
92 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
93 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
94 for x
, v
in spr_to_fast
.items():
96 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
97 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
101 class DecodeA(Elaboratable
):
102 """DecodeA from instruction
104 decodes register RA, implicit and explicit CSRs
107 def __init__(self
, dec
, op
, regreduce_en
):
108 self
.regreduce_en
= regreduce_en
109 if self
.regreduce_en
:
115 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
116 self
.insn_in
= Signal(32, reset_less
=True)
117 self
.reg_out
= Data(5, name
="reg_a")
118 self
.spr_out
= Data(SPR
, "spr_a")
119 self
.fast_out
= Data(3, "fast_a")
120 self
.sv_nz
= Signal(1)
122 def elaborate(self
, platform
):
127 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
129 # select Register A field, if *full 7 bits* are zero (2 more from SVP64)
130 ra
= Signal(5, reset_less
=True)
131 comb
+= ra
.eq(self
.dec
.RA
)
132 with m
.If((self
.sel_in
== In1Sel
.RA
) |
133 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
134 ((ra
!= Const(0, 5)) |
(self
.sv_nz
!= Const(0, 1))))):
135 comb
+= reg
.data
.eq(ra
)
138 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
139 # moved it to 1st position (in1_sel)... because
140 rs
= Signal(5, reset_less
=True)
141 comb
+= rs
.eq(self
.dec
.RS
)
142 with m
.If(self
.sel_in
== In1Sel
.RS
):
143 comb
+= reg
.data
.eq(rs
)
146 # select Register FRA field,
147 fra
= Signal(5, reset_less
=True)
148 comb
+= fra
.eq(self
.dec
.FRA
)
149 with m
.If(self
.sel_in
== In1Sel
.FRA
):
150 comb
+= reg
.data
.eq(fra
)
153 # select Register FRS field,
154 frs
= Signal(5, reset_less
=True)
155 comb
+= frs
.eq(self
.dec
.FRS
)
156 with m
.If(self
.sel_in
== In1Sel
.FRS
):
157 comb
+= reg
.data
.eq(frs
)
160 # decode Fast-SPR based on instruction type
161 with m
.Switch(op
.internal_op
):
163 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
164 with m
.Case(MicrOp
.OP_BC
):
165 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
167 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
168 comb
+= self
.fast_out
.ok
.eq(1)
169 with m
.Case(MicrOp
.OP_BCREG
):
170 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
171 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
172 with m
.If(xo9
& ~xo5
):
174 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
175 comb
+= self
.fast_out
.ok
.eq(1)
177 # MFSPR move from SPRs
178 with m
.Case(MicrOp
.OP_MFSPR
):
179 spr
= Signal(10, reset_less
=True)
180 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
181 comb
+= sprmap
.spr_i
.eq(spr
)
182 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
183 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
188 class DecodeAImm(Elaboratable
):
189 """DecodeA immediate from instruction
191 decodes register RA, whether immediate-zero, implicit and
192 explicit CSRs. SVP64 mode requires 2 extra bits
195 def __init__(self
, dec
):
197 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
198 self
.immz_out
= Signal(reset_less
=True)
199 self
.sv_nz
= Signal(1) # EXTRA bits from SVP64
201 def elaborate(self
, platform
):
205 # zero immediate requested
206 ra
= Signal(5, reset_less
=True)
207 comb
+= ra
.eq(self
.dec
.RA
)
208 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
209 (ra
== Const(0, 5)) &
210 (self
.sv_nz
== Const(0, 1))):
211 comb
+= self
.immz_out
.eq(1)
216 class DecodeB(Elaboratable
):
217 """DecodeB from instruction
219 decodes register RB, different forms of immediate (signed, unsigned),
220 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
221 by industry-standard convention, "lane 2" is where fully-decoded
222 immediates are muxed in.
225 def __init__(self
, dec
, op
):
228 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
229 self
.insn_in
= Signal(32, reset_less
=True)
230 self
.reg_out
= Data(7, "reg_b")
231 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
232 self
.fast_out
= Data(3, "fast_b")
234 def elaborate(self
, platform
):
240 # select Register B field
241 with m
.Switch(self
.sel_in
):
242 with m
.Case(In2Sel
.FRB
):
243 comb
+= reg
.data
.eq(self
.dec
.FRB
)
245 with m
.Case(In2Sel
.RB
):
246 comb
+= reg
.data
.eq(self
.dec
.RB
)
248 with m
.Case(In2Sel
.RS
):
249 # for M-Form shiftrot
250 comb
+= reg
.data
.eq(self
.dec
.RS
)
253 # decode SPR2 based on instruction type
254 # BCREG implicitly uses LR or TAR for 2nd reg
255 # CTR however is already in fast_spr1 *not* 2.
256 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
257 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
258 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
260 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
)
261 comb
+= self
.fast_out
.ok
.eq(1)
263 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.TAR
)
264 comb
+= self
.fast_out
.ok
.eq(1)
269 class DecodeBImm(Elaboratable
):
270 """DecodeB immediate from instruction
273 def __init__(self
, dec
):
275 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
276 self
.imm_out
= Data(64, "imm_b")
278 def elaborate(self
, platform
):
282 # select Register B Immediate
283 with m
.Switch(self
.sel_in
):
284 with m
.Case(In2Sel
.CONST_UI
): # unsigned
285 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
286 comb
+= self
.imm_out
.ok
.eq(1)
287 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
288 si
= Signal(16, reset_less
=True)
289 comb
+= si
.eq(self
.dec
.SI
)
290 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
291 comb
+= self
.imm_out
.ok
.eq(1)
292 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
293 si_hi
= Signal(32, reset_less
=True)
294 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
295 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
296 comb
+= self
.imm_out
.ok
.eq(1)
297 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
298 ui
= Signal(16, reset_less
=True)
299 comb
+= ui
.eq(self
.dec
.UI
)
300 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
301 comb
+= self
.imm_out
.ok
.eq(1)
302 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
303 li
= Signal(26, reset_less
=True)
304 comb
+= li
.eq(self
.dec
.LI
<< 2)
305 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
306 comb
+= self
.imm_out
.ok
.eq(1)
307 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
308 bd
= Signal(16, reset_less
=True)
309 comb
+= bd
.eq(self
.dec
.BD
<< 2)
310 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
311 comb
+= self
.imm_out
.ok
.eq(1)
312 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
313 ds
= Signal(16, reset_less
=True)
314 comb
+= ds
.eq(self
.dec
.DS
<< 2)
315 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
316 comb
+= self
.imm_out
.ok
.eq(1)
317 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
318 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
319 comb
+= self
.imm_out
.ok
.eq(1)
320 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
321 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
322 comb
+= self
.imm_out
.ok
.eq(1)
323 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
324 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
325 comb
+= self
.imm_out
.ok
.eq(1)
326 with m
.Case(In2Sel
.CONST_XBI
): # unsigned - for grevi
327 comb
+= self
.imm_out
.data
.eq(self
.dec
.FormXB
.XBI
)
328 comb
+= self
.imm_out
.ok
.eq(1)
333 class DecodeC(Elaboratable
):
334 """DecodeC from instruction
336 decodes register RC. this is "lane 3" into some CompUnits (not many)
339 def __init__(self
, dec
, op
):
342 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
343 self
.insn_in
= Signal(32, reset_less
=True)
344 self
.reg_out
= Data(5, "reg_c")
346 def elaborate(self
, platform
):
352 # select Register C field
353 with m
.Switch(self
.sel_in
):
354 with m
.Case(In3Sel
.RB
):
355 # for M-Form shiftrot
356 comb
+= reg
.data
.eq(self
.dec
.RB
)
358 with m
.Case(In3Sel
.FRS
):
359 comb
+= reg
.data
.eq(self
.dec
.FRS
)
361 with m
.Case(In3Sel
.FRC
):
362 comb
+= reg
.data
.eq(self
.dec
.FRC
)
364 with m
.Case(In3Sel
.RS
):
365 comb
+= reg
.data
.eq(self
.dec
.RS
)
367 with m
.Case(In3Sel
.RC
):
368 comb
+= reg
.data
.eq(self
.dec
.RC
)
370 with m
.Case(In3Sel
.RT
):
371 # for TLI-form ternlogi
372 comb
+= reg
.data
.eq(self
.dec
.RT
)
378 class DecodeOut(Elaboratable
):
379 """DecodeOut from instruction
381 decodes output register RA, RT or SPR
384 def __init__(self
, dec
, op
, regreduce_en
):
385 self
.regreduce_en
= regreduce_en
386 if self
.regreduce_en
:
392 self
.sel_in
= Signal(OutSel
, reset_less
=True)
393 self
.insn_in
= Signal(32, reset_less
=True)
394 self
.reg_out
= Data(5, "reg_o")
395 self
.spr_out
= Data(SPR
, "spr_o")
396 self
.fast_out
= Data(3, "fast_o")
398 def elaborate(self
, platform
):
401 m
.submodules
.sprmap
= sprmap
= SPRMap(self
.regreduce_en
)
405 # select Register out field
406 with m
.Switch(self
.sel_in
):
407 with m
.Case(OutSel
.FRT
):
408 comb
+= reg
.data
.eq(self
.dec
.FRT
)
410 with m
.Case(OutSel
.RT
):
411 comb
+= reg
.data
.eq(self
.dec
.RT
)
413 with m
.Case(OutSel
.RA
):
414 comb
+= reg
.data
.eq(self
.dec
.RA
)
416 with m
.Case(OutSel
.SPR
):
417 spr
= Signal(10, reset_less
=True)
418 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
419 # MFSPR move to SPRs - needs mapping
420 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
421 comb
+= sprmap
.spr_i
.eq(spr
)
422 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
423 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
426 with m
.Switch(op
.internal_op
):
428 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
429 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
430 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
432 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.CTR
)
433 comb
+= self
.fast_out
.ok
.eq(1)
435 # RFID 1st spr (fast)
436 with m
.Case(MicrOp
.OP_RFID
):
437 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
438 comb
+= self
.fast_out
.ok
.eq(1)
443 class DecodeOut2(Elaboratable
):
444 """DecodeOut2 from instruction
446 decodes output registers (2nd one). note that RA is *implicit* below,
447 which now causes problems with SVP64
449 TODO: SVP64 is a little more complex, here. svp64 allows extending
450 by one more destination by having one more EXTRA field. RA-as-src
451 is not the same as RA-as-dest. limited in that it's the same first
452 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
453 for operations that have src-as-dest: mostly this is LD/ST-with-update
454 but there are others.
457 def __init__(self
, dec
, op
):
460 self
.sel_in
= Signal(OutSel
, reset_less
=True)
461 self
.svp64_fft_mode
= Signal(reset_less
=True) # SVP64 FFT mode
462 self
.lk
= Signal(reset_less
=True)
463 self
.insn_in
= Signal(32, reset_less
=True)
464 self
.reg_out
= Data(5, "reg_o2")
465 self
.fp_madd_en
= Signal(reset_less
=True) # FFT instruction detected
466 self
.fast_out
= Data(3, "fast_o2")
467 self
.fast_out3
= Data(3, "fast_o3")
469 def elaborate(self
, platform
):
473 #m.submodules.svdec = svdec = SVP64RegExtra()
475 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
476 #reg = Signal(5, reset_less=True)
478 if hasattr(op
, "upd"):
479 # update mode LD/ST uses read-reg A also as an output
480 with m
.If(op
.upd
== LDSTMode
.update
):
481 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
482 comb
+= self
.reg_out
.ok
.eq(1)
484 # B, BC or BCREG: potential implicit register (LR) output
485 # these give bl, bcl, bclrl, etc.
486 with m
.Switch(op
.internal_op
):
488 # BC* implicit register (LR)
489 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
490 with m
.If(self
.lk
): # "link" mode
491 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.LR
) # LR
492 comb
+= self
.fast_out
.ok
.eq(1)
494 # RFID 2nd and 3rd spr (fast)
495 with m
.Case(MicrOp
.OP_RFID
):
496 comb
+= self
.fast_out
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
497 comb
+= self
.fast_out
.ok
.eq(1)
498 comb
+= self
.fast_out3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
499 comb
+= self
.fast_out3
.ok
.eq(1)
501 # SVP64 FFT mode, FP mul-add: 2nd output reg (FRS) same as FRT
502 # will be offset by VL in hardware
503 # with m.Case(MicrOp.OP_FP_MADD):
504 with m
.If(self
.svp64_fft_mode
):
505 comb
+= self
.reg_out
.data
.eq(self
.dec
.FRT
)
506 comb
+= self
.reg_out
.ok
.eq(1)
507 comb
+= self
.fp_madd_en
.eq(1)
512 class DecodeRC(Elaboratable
):
513 """DecodeRc from instruction
515 decodes Record bit Rc
518 def __init__(self
, dec
):
520 self
.sel_in
= Signal(RC
, reset_less
=True)
521 self
.insn_in
= Signal(32, reset_less
=True)
522 self
.rc_out
= Data(1, "rc")
524 def elaborate(self
, platform
):
528 # select Record bit out field
529 with m
.Switch(self
.sel_in
):
531 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
532 comb
+= self
.rc_out
.ok
.eq(1)
534 comb
+= self
.rc_out
.data
.eq(1)
535 comb
+= self
.rc_out
.ok
.eq(1)
536 with m
.Case(RC
.NONE
):
537 comb
+= self
.rc_out
.data
.eq(0)
538 comb
+= self
.rc_out
.ok
.eq(1)
543 class DecodeOE(Elaboratable
):
544 """DecodeOE from instruction
546 decodes OE field: uses RC decode detection which might not be good
548 -- For now, use "rc" in the decode table to decide whether oe exists.
549 -- This is not entirely correct architecturally: For mulhd and
550 -- mulhdu, the OE field is reserved. It remains to be seen what an
551 -- actual POWER9 does if we set it on those instructions, for now we
552 -- test that further down when assigning to the multiplier oe input.
555 def __init__(self
, dec
, op
):
558 self
.sel_in
= Signal(RC
, reset_less
=True)
559 self
.insn_in
= Signal(32, reset_less
=True)
560 self
.oe_out
= Data(1, "oe")
562 def elaborate(self
, platform
):
567 with m
.Switch(op
.internal_op
):
569 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
571 # XXX ARGH! ignoring OE causes incompatibility with microwatt
572 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
573 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
574 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
575 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
576 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
577 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
581 # all other ops decode OE field
583 # select OE bit out field
584 with m
.Switch(self
.sel_in
):
586 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
587 comb
+= self
.oe_out
.ok
.eq(1)
592 class DecodeCRIn(Elaboratable
):
593 """Decodes input CR from instruction
595 CR indices - insn fields - (not the data *in* the CR) require only 3
596 bits because they refer to CR0-CR7
599 def __init__(self
, dec
, op
):
602 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
603 self
.insn_in
= Signal(32, reset_less
=True)
604 self
.cr_bitfield
= Data(3, "cr_bitfield")
605 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
606 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
607 self
.whole_reg
= Data(8, "cr_fxm")
608 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
610 def elaborate(self
, platform
):
614 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
617 # zero-initialisation
618 comb
+= self
.cr_bitfield
.ok
.eq(0)
619 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
620 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
621 comb
+= self
.whole_reg
.ok
.eq(0)
622 comb
+= self
.sv_override
.eq(0)
624 # select the relevant CR bitfields
625 with m
.Switch(self
.sel_in
):
626 with m
.Case(CRInSel
.NONE
):
627 pass # No bitfield activated
628 with m
.Case(CRInSel
.CR0
):
629 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
630 comb
+= self
.cr_bitfield
.ok
.eq(1)
631 comb
+= self
.sv_override
.eq(1)
632 with m
.Case(CRInSel
.CR1
):
633 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
634 comb
+= self
.cr_bitfield
.ok
.eq(1)
635 comb
+= self
.sv_override
.eq(2)
636 with m
.Case(CRInSel
.BI
):
637 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
638 comb
+= self
.cr_bitfield
.ok
.eq(1)
639 with m
.Case(CRInSel
.BFA
):
640 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
641 comb
+= self
.cr_bitfield
.ok
.eq(1)
642 with m
.Case(CRInSel
.BA_BB
):
643 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
644 comb
+= self
.cr_bitfield
.ok
.eq(1)
645 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
646 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
647 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
648 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
649 with m
.Case(CRInSel
.BC
):
650 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
651 comb
+= self
.cr_bitfield
.ok
.eq(1)
652 with m
.Case(CRInSel
.WHOLE_REG
):
653 comb
+= self
.whole_reg
.ok
.eq(1)
654 move_one
= Signal(reset_less
=True)
655 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
656 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
657 # must one-hot the FXM field
658 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
659 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
661 # otherwise use all of it
662 comb
+= self
.whole_reg
.data
.eq(0xff)
667 class DecodeCROut(Elaboratable
):
668 """Decodes input CR from instruction
670 CR indices - insn fields - (not the data *in* the CR) require only 3
671 bits because they refer to CR0-CR7
674 def __init__(self
, dec
, op
):
677 self
.rc_in
= Signal(reset_less
=True)
678 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
679 self
.insn_in
= Signal(32, reset_less
=True)
680 self
.cr_bitfield
= Data(3, "cr_bitfield")
681 self
.whole_reg
= Data(8, "cr_fxm")
682 self
.sv_override
= Signal(2, reset_less
=True) # do not do EXTRA spec
684 def elaborate(self
, platform
):
688 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
691 comb
+= self
.cr_bitfield
.ok
.eq(0)
692 comb
+= self
.whole_reg
.ok
.eq(0)
693 comb
+= self
.sv_override
.eq(0)
695 # please note these MUST match (setting of cr_bitfield.ok) exactly
696 # with write_cr0 below in PowerDecoder2. the reason it's separated
697 # is to avoid having duplicate copies of DecodeCROut in multiple
698 # PowerDecoderSubsets. register decoding should be a one-off in
699 # PowerDecoder2. see https://bugs.libre-soc.org/show_bug.cgi?id=606
701 with m
.Switch(self
.sel_in
):
702 with m
.Case(CROutSel
.NONE
):
703 pass # No bitfield activated
704 with m
.Case(CROutSel
.CR0
):
705 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
706 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
707 comb
+= self
.sv_override
.eq(1)
708 with m
.Case(CROutSel
.CR1
):
709 comb
+= self
.cr_bitfield
.data
.eq(1) # CR1 (MSB0 numbering)
710 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
711 comb
+= self
.sv_override
.eq(2)
712 with m
.Case(CROutSel
.BF
):
713 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
714 comb
+= self
.cr_bitfield
.ok
.eq(1)
715 with m
.Case(CROutSel
.BT
):
716 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
717 comb
+= self
.cr_bitfield
.ok
.eq(1)
718 with m
.Case(CROutSel
.WHOLE_REG
):
719 comb
+= self
.whole_reg
.ok
.eq(1)
720 move_one
= Signal(reset_less
=True)
721 comb
+= move_one
.eq(self
.insn_in
[20])
722 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
724 # must one-hot the FXM field
725 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
726 with m
.If(ppick
.en_o
):
727 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
729 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
731 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
733 # otherwise use all of it
734 comb
+= self
.whole_reg
.data
.eq(0xff)
739 # dictionary of Input Record field names that, if they exist,
740 # will need a corresponding CSV Decoder file column (actually, PowerOp)
741 # to be decoded (this includes the single bit names)
742 record_names
= {'insn_type': 'internal_op',
743 'fn_unit': 'function_unit',
744 'SV_Ptype': 'SV_Ptype',
748 'imm_data': 'in2_sel',
749 'invert_in': 'inv_a',
750 'invert_out': 'inv_out',
753 'output_carry': 'cry_out',
754 'input_carry': 'cry_in',
755 'is_32bit': 'is_32b',
758 'data_len': 'ldst_len',
760 'byte_reverse': 'br',
761 'sign_extend': 'sgn_ext',
766 class PowerDecodeSubset(Elaboratable
):
767 """PowerDecodeSubset: dynamic subset decoder
769 only fields actually requested are copied over. hence, "subset" (duh).
772 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None,
773 svp64_en
=True, regreduce_en
=False):
775 self
.svp64_en
= svp64_en
776 self
.regreduce_en
= regreduce_en
778 self
.is_svp64_mode
= Signal() # mark decoding as SVP64 Mode
779 self
.use_svp64_ldst_dec
= Signal() # must use LDST decoder
780 self
.use_svp64_fft
= Signal() # FFT Mode
781 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
782 self
.rm_dec
= SVP64RMModeDecode("svp64_rm_dec")
783 # set these to the predicate mask bits needed for the ALU
784 self
.pred_sm
= Signal() # TODO expand to SIMD mask width
785 self
.pred_dm
= Signal() # TODO expand to SIMD mask width
786 self
.sv_a_nz
= Signal(1)
789 self
.fn_name
= fn_name
791 opkls
= Decode2ToOperand
792 self
.do
= opkls(fn_name
)
794 col_subset
= self
.get_col_subset(self
.do
)
795 row_subset
= self
.rowsubsetfn
800 # "conditions" for Decoders, to enable some weird and wonderful
801 # alternatives. useful for PCR (Program Compatibility Register)
802 # amongst other things
804 conditions
= {'SVP64BREV': self
.use_svp64_ldst_dec
,
805 'SVP64FFT': self
.use_svp64_fft
,
810 # only needed for "main" PowerDecode2
812 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
,
813 regreduce_en
=regreduce_en
)
815 # create decoder if one not already given
817 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
818 row_subset
=row_subset
,
819 conditions
=conditions
)
822 # set up a copy of the PowerOp
823 self
.op
= PowerOp
.like(self
.dec
.op
)
825 # state information needed by the Decoder
827 state
= CoreState("dec2")
830 def get_col_subset(self
, do
):
831 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
832 for k
, v
in record_names
.items():
835 log("get_col_subset", self
.fn_name
, do
.fields
, subset
)
838 def rowsubsetfn(self
, opcode
, row
):
839 """select per-Function-Unit subset of opcodes to be processed
841 normally this just looks at the "unit" column. MMU is different
842 in that it processes specific SPR set/get operations that the SPR
845 return (row
['unit'] == self
.fn_name
or
846 # sigh a dreadful hack: MTSPR and MFSPR need to be processed
847 # by the MMU pipeline so we direct those opcodes to MMU **AND**
848 # SPR pipelines, then selectively weed out the SPRs that should
849 # or should not not go to each pipeline, further down.
850 # really this should be done by modifying the CSV syntax
851 # to support multiple tasks (unit column multiple entries)
852 # see https://bugs.libre-soc.org/show_bug.cgi?id=310
853 (self
.fn_name
== 'MMU' and row
['unit'] == 'SPR' and
854 row
['internal op'] in ['OP_MTSPR', 'OP_MFSPR'])
858 ports
= self
.dec
.ports() + self
.e
.ports()
860 ports
+= self
.sv_rm
.ports()
861 ports
.append(self
.is_svp64_mode
)
862 ports
.append(self
.use_svp64_ldst_dec
)
863 ports
.append(self
.use_svp64_fft
)
866 def needs_field(self
, field
, op_field
):
871 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
873 def do_get(self
, field
, final
=False):
874 if final
or self
.final
:
878 return getattr(do
, field
, None)
880 def do_copy(self
, field
, val
, final
=False):
881 df
= self
.do_get(field
, final
)
882 if df
is not None and val
is not None:
886 def op_get(self
, op_field
):
887 return getattr(self
.op
, op_field
, None)
889 def elaborate(self
, platform
):
890 if self
.regreduce_en
:
897 op
, do
= self
.dec
.op
, self
.do
898 msr
, cia
, svstate
= state
.msr
, state
.pc
, state
.svstate
899 # fill in for a normal instruction (not an exception)
900 # copy over if non-exception, non-privileged etc. is detected
902 if self
.fn_name
is None:
905 name
= self
.fn_name
+ "tmp"
906 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
,
907 regreduce_en
=self
.regreduce_en
)
909 # set up submodule decoders
910 m
.submodules
.dec
= dec
= self
.dec
911 m
.submodules
.dec_rc
= self
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
912 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
, op
)
915 # and SVP64 RM mode decoder
916 m
.submodules
.sv_rm_dec
= rm_dec
= self
.rm_dec
918 # copy op from decoder
919 comb
+= self
.op
.eq(self
.dec
.op
)
921 # copy instruction through...
922 for i
in [do
.insn
, dec_rc
.insn_in
, dec_oe
.insn_in
, ]:
923 comb
+= i
.eq(self
.dec
.opcode_in
)
925 # ...and subdecoders' input fields
926 comb
+= dec_rc
.sel_in
.eq(self
.op_get("rc_sel"))
927 comb
+= dec_oe
.sel_in
.eq(self
.op_get("rc_sel")) # XXX should be OE sel
930 comb
+= self
.do_copy("msr", msr
)
931 comb
+= self
.do_copy("cia", cia
)
932 comb
+= self
.do_copy("svstate", svstate
)
934 # set up instruction type
935 # no op: defaults to OP_ILLEGAL
936 internal_op
= self
.op_get("internal_op")
937 comb
+= self
.do_copy("insn_type", internal_op
)
939 # function unit for decoded instruction: requires minor redirect
941 fn
= self
.op_get("function_unit")
942 spr
= Signal(10, reset_less
=True)
943 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
945 # Microwatt doesn't implement the partition table
946 # instead has PRTBL register (SPR) to point to process table
948 is_mmu_spr
= Signal()
949 comb
+= is_spr_mv
.eq((internal_op
== MicrOp
.OP_MTSPR
) |
950 (internal_op
== MicrOp
.OP_MFSPR
))
951 comb
+= is_mmu_spr
.eq((spr
== SPR
.DSISR
.value
) |
952 (spr
== SPR
.DAR
.value
) |
953 (spr
== SPR
.PRTBL
.value
) |
954 (spr
== SPR
.PIDR
.value
))
955 # MMU must receive MMU SPRs
956 with m
.If(is_spr_mv
& (fn
== Function
.SPR
) & is_mmu_spr
):
957 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
958 comb
+= self
.do_copy("insn_type", internal_op
)
959 # SPR pipe must *not* receive MMU SPRs
960 with m
.Elif(is_spr_mv
& (fn
== Function
.MMU
) & ~is_mmu_spr
):
961 comb
+= self
.do_copy("fn_unit", Function
.NONE
)
962 comb
+= self
.do_copy("insn_type", MicrOp
.OP_ILLEGAL
)
965 comb
+= self
.do_copy("fn_unit", fn
)
968 if self
.needs_field("zero_a", "in1_sel"):
969 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
970 comb
+= dec_ai
.sv_nz
.eq(self
.sv_a_nz
)
971 comb
+= dec_ai
.sel_in
.eq(self
.op_get("in1_sel"))
972 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
973 if self
.needs_field("imm_data", "in2_sel"):
974 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
975 comb
+= dec_bi
.sel_in
.eq(self
.op_get("in2_sel"))
976 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
979 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
981 # OE only enabled when SVP64 not active
982 with m
.If(~self
.is_svp64_mode
):
983 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
985 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
987 # CR in/out - note: these MUST match with what happens in
989 rc_out
= self
.dec_rc
.rc_out
.data
990 with m
.Switch(self
.op_get("cr_out")):
991 with m
.Case(CROutSel
.CR0
, CROutSel
.CR1
):
992 comb
+= self
.do_copy("write_cr0", rc_out
) # only when RC=1
993 with m
.Case(CROutSel
.BF
, CROutSel
.BT
):
994 comb
+= self
.do_copy("write_cr0", 1)
996 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
997 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1000 # connect up SVP64 RM Mode decoding. however... we need a shorter
1001 # path, for the LDST bit-reverse detection. so perform partial
1002 # decode when SVP64 is detected. then, bit-reverse mode can be
1003 # quickly determined, and the Decoder result MUXed over to
1004 # the alternative decoder, svdecldst. what a mess... *sigh*
1005 sv_ptype
= self
.op_get("SV_Ptype")
1006 fn
= self
.op_get("function_unit")
1007 # detect major opcode for LDs: include 58 here. from CSV files.
1008 # BLECH! TODO: these should be done using "mini decoders",
1009 # using row and column subsets
1010 is_major_ld
= Signal()
1011 # bits... errr... MSB0 0..5 which is 26:32 python
1013 comb
+= major
.eq(self
.dec
.opcode_in
[26:32])
1014 comb
+= is_major_ld
.eq((major
== 34) |
(major
== 35) |
1015 (major
== 50) |
(major
== 51) |
1016 (major
== 48) |
(major
== 49) |
1017 (major
== 42) |
(major
== 43) |
1018 (major
== 40) |
(major
== 41) |
1019 (major
== 32) |
(major
== 33) |
1021 with m
.If(self
.is_svp64_mode
& is_major_ld
):
1022 # straight-up: "it's a LD". this gives enough info
1023 # for SVP64 RM Mode decoding to detect LD/ST, and
1024 # consequently detect the SHIFT mode. sigh
1025 comb
+= rm_dec
.fn_in
.eq(Function
.LDST
)
1027 comb
+= rm_dec
.fn_in
.eq(fn
) # decode needs to know Fn type
1028 comb
+= rm_dec
.ptype_in
.eq(sv_ptype
) # Single/Twin predicated
1029 comb
+= rm_dec
.rc_in
.eq(rc_out
) # Rc=1
1030 comb
+= rm_dec
.rm_in
.eq(self
.sv_rm
) # SVP64 RM mode
1031 if self
.needs_field("imm_data", "in2_sel"):
1032 bzero
= dec_bi
.imm_out
.ok
& ~dec_bi
.imm_out
.data
.bool()
1033 comb
+= rm_dec
.ldst_imz_in
.eq(bzero
) # B immediate is zero
1035 # main PowerDecoder2 determines if different SVP64 modes enabled
1037 # if shift mode requested
1038 shiftmode
= rm_dec
.ldstmode
== SVP64LDSTmode
.SHIFT
1039 comb
+= self
.use_svp64_ldst_dec
.eq(shiftmode
)
1040 # detect if SVP64 FFT mode enabled (really bad hack),
1041 # exclude fcfids and others
1042 # XXX this is a REALLY bad hack, REALLY has to be done better.
1043 # likely with a sub-decoder.
1044 xo5
= Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
1045 comb
+= xo5
.eq(self
.dec
.opcode_in
[5])
1046 xo
= Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
1047 comb
+= xo
.eq(self
.dec
.opcode_in
[1:6])
1048 comb
+= self
.use_svp64_fft
.eq((major
== 59) & (xo5
== 0b0) &
1051 # decoded/selected instruction flags
1052 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1053 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1054 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1055 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1056 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1057 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1058 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1059 lk
= self
.op_get("lk")
1062 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1064 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1065 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1066 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1067 comb
+= self
.do_copy("reserve", self
.op_get("rsrv")) # atomic
1069 # copy over SVP64 input record fields (if they exist)
1071 # TODO, really do we have to do these explicitly?? sigh
1072 # for (field, _) in sv_input_record_layout:
1073 # comb += self.do_copy(field, self.rm_dec.op_get(field))
1074 comb
+= self
.do_copy("sv_saturate", self
.rm_dec
.saturate
)
1075 comb
+= self
.do_copy("sv_Ptype", self
.rm_dec
.ptype_in
)
1076 comb
+= self
.do_copy("sv_ldstmode", self
.rm_dec
.ldstmode
)
1077 # these get set up based on incoming mask bits. TODO:
1078 # pass in multiple bits (later, when SIMD backends are enabled)
1079 with m
.If(self
.rm_dec
.pred_sz
):
1080 comb
+= self
.do_copy("sv_pred_sz", ~self
.pred_sm
)
1081 with m
.If(self
.rm_dec
.pred_dz
):
1082 comb
+= self
.do_copy("sv_pred_dz", ~self
.pred_dm
)
1087 class PowerDecode2(PowerDecodeSubset
):
1088 """PowerDecode2: the main instruction decoder.
1090 whilst PowerDecode is responsible for decoding the actual opcode, this
1091 module encapsulates further specialist, sparse information and
1092 expansion of fields that is inconvenient to have in the CSV files.
1093 for example: the encoding of the immediates, which are detected
1094 and expanded out to their full value from an annotated (enum)
1097 implicit register usage is also set up, here. for example: OP_BC
1098 requires implicitly reading CTR, OP_RFID requires implicitly writing
1101 in addition, PowerDecoder2 is responsible for detecting whether
1102 instructions are illegal (or privileged) or not, and instead of
1103 just leaving at that, *replacing* the instruction to execute with
1104 a suitable alternative (trap).
1106 LDSTExceptions are done the cycle _after_ they're detected (after
1107 they come out of LDSTCompUnit). basically despite the instruction
1108 being decoded, the results of the decode are completely ignored
1109 and "exception.happened" used to set the "actual" instruction to
1110 "OP_TRAP". the LDSTException data structure gets filled in,
1111 in the CompTrapOpSubset and that's what it fills in SRR.
1113 to make this work, TestIssuer must notice "exception.happened"
1114 after the (failed) LD/ST and copies the LDSTException info from
1115 the output, into here (PowerDecoder2). without incrementing PC.
1117 also instr_fault works the same way: the instruction is "rewritten"
1118 so that the "fake" op that gets created is OP_FETCH_FAILED
1121 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False,
1122 state
=None, svp64_en
=True, regreduce_en
=False):
1123 super().__init
__(dec
, opkls
, fn_name
, final
, state
, svp64_en
,
1125 self
.ldst_exc
= LDSTException("dec2_exc") # rewrites as OP_TRAP
1126 self
.instr_fault
= Signal() # rewrites instruction as OP_FETCH_FAILED
1129 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
1130 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
1131 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
1132 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
1133 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1134 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1135 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1136 self
.o_isvec
= Signal(7, name
="reg_o_isvec")
1137 self
.o2_isvec
= Signal(7, name
="reg_o2_isvec")
1138 self
.in1_step
= Signal(7, name
="reg_a_step")
1139 self
.in2_step
= Signal(7, name
="reg_b_step")
1140 self
.in3_step
= Signal(7, name
="reg_c_step")
1141 self
.o_step
= Signal(7, name
="reg_o_step")
1142 self
.o2_step
= Signal(7, name
="reg_o2_step")
1143 self
.remap_active
= Signal(5, name
="remap_active") # per reg
1144 self
.no_in_vec
= Signal(1, name
="no_in_vec") # no inputs vector
1145 self
.no_out_vec
= Signal(1, name
="no_out_vec") # no outputs vector
1146 self
.loop_continue
= Signal(1, name
="loop_continue")
1148 self
.no_in_vec
= Const(1, 1)
1149 self
.no_out_vec
= Const(1, 1)
1150 self
.loop_continue
= Const(0, 1)
1152 def get_col_subset(self
, opkls
):
1153 subset
= super().get_col_subset(opkls
)
1154 subset
.add("asmcode")
1155 subset
.add("in1_sel")
1156 subset
.add("in2_sel")
1157 subset
.add("in3_sel")
1158 subset
.add("out_sel")
1160 subset
.add("sv_in1")
1161 subset
.add("sv_in2")
1162 subset
.add("sv_in3")
1163 subset
.add("sv_out")
1164 subset
.add("sv_out2")
1165 subset
.add("sv_cr_in")
1166 subset
.add("sv_cr_out")
1167 subset
.add("SV_Etype")
1168 subset
.add("SV_Ptype")
1169 # from SVP64RMModeDecode
1170 for (field
, _
) in sv_input_record_layout
:
1173 subset
.add("internal_op")
1177 def elaborate(self
, platform
):
1178 m
= super().elaborate(platform
)
1181 op
, e_out
, do_out
= self
.op
, self
.e
, self
.e
.do
1182 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1183 rc_out
= self
.dec_rc
.rc_out
.data
1187 # fill in for a normal instruction (not an exception)
1188 # copy over if non-exception, non-privileged etc. is detected
1190 # set up submodule decoders
1191 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
, op
, self
.regreduce_en
)
1192 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
, op
)
1193 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
, op
)
1194 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
, op
, self
.regreduce_en
)
1195 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
, op
)
1196 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
, op
)
1197 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
, op
)
1198 comb
+= dec_a
.sv_nz
.eq(self
.sv_a_nz
)
1201 # and SVP64 Extra decoders
1202 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1203 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1204 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1205 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1206 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1207 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1208 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1209 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1210 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1212 # debug access to cr svdec (used in get_pdecode_cr_in/out)
1213 self
.crout_svdec
= crout_svdec
1214 self
.crin_svdec
= crin_svdec
1216 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1217 reg
= Signal(5, reset_less
=True)
1219 # copy instruction through...
1220 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1221 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
,
1222 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1223 comb
+= i
.eq(self
.dec
.opcode_in
)
1226 comb
+= self
.dec_cr_in
.sel_in
.eq(self
.op_get("cr_in"))
1227 comb
+= self
.dec_cr_out
.sel_in
.eq(self
.op_get("cr_out"))
1228 comb
+= self
.dec_cr_out
.rc_in
.eq(rc_out
)
1231 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1232 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1234 # ...and subdecoders' input fields
1235 comb
+= dec_a
.sel_in
.eq(self
.op_get("in1_sel"))
1236 comb
+= dec_b
.sel_in
.eq(self
.op_get("in2_sel"))
1237 comb
+= dec_c
.sel_in
.eq(self
.op_get("in3_sel"))
1238 comb
+= dec_o
.sel_in
.eq(self
.op_get("out_sel"))
1239 comb
+= dec_o2
.sel_in
.eq(self
.op_get("out_sel"))
1241 comb
+= dec_o2
.svp64_fft_mode
.eq(self
.use_svp64_fft
)
1242 if hasattr(do
, "lk"):
1243 comb
+= dec_o2
.lk
.eq(do
.lk
)
1246 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1247 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1248 # which in turn were auto-generated by sv_analysis.py
1249 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1254 comb
+= crout_svdec
.idx
.eq(self
.op_get("sv_cr_out"))
1255 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1258 # CR in - selection slightly different due to shared CR field sigh
1259 cr_a_idx
= Signal(SVEXTRA
)
1260 cr_b_idx
= Signal(SVEXTRA
)
1262 # these change slightly, when decoding BA/BB. really should have
1263 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1264 comb
+= cr_a_idx
.eq(self
.op_get("sv_cr_in"))
1265 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1266 with m
.If(self
.op_get("sv_cr_in") == SVEXTRA
.Idx_1_2
.value
):
1267 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1268 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1270 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1271 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1272 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1274 # indices are slightly different, BA/BB mess sorted above
1275 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1276 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1278 comb
+= crin_svdec_o
.idx
.eq(self
.op_get("sv_cr_out"))
1280 # get SVSTATE srcstep (TODO: elwidth etc.) needed below
1281 vl
= Signal
.like(self
.state
.svstate
.vl
)
1282 srcstep
= Signal
.like(self
.state
.svstate
.srcstep
)
1283 dststep
= Signal
.like(self
.state
.svstate
.dststep
)
1284 comb
+= vl
.eq(self
.state
.svstate
.vl
)
1285 comb
+= srcstep
.eq(self
.state
.svstate
.srcstep
)
1286 comb
+= dststep
.eq(self
.state
.svstate
.dststep
)
1288 in1_step
, in2_step
= self
.in1_step
, self
.in2_step
1289 in3_step
= self
.in3_step
1290 o_step
, o2_step
= self
.o_step
, self
.o2_step
1292 # registers a, b, c and out and out2 (LD/ST EA)
1293 sv_etype
= self
.op_get("SV_Etype")
1294 for i
, stuff
in enumerate((
1295 ("RA", e
.read_reg1
, dec_a
.reg_out
, in1_svdec
, in1_step
, False),
1296 ("RB", e
.read_reg2
, dec_b
.reg_out
, in2_svdec
, in2_step
, False),
1297 ("RC", e
.read_reg3
, dec_c
.reg_out
, in3_svdec
, in3_step
, False),
1298 ("RT", e
.write_reg
, dec_o
.reg_out
, o_svdec
, o_step
, True),
1299 ("EA", e
.write_ea
, dec_o2
.reg_out
, o2_svdec
, o2_step
, True))):
1300 rname
, to_reg
, fromreg
, svdec
, remapstep
, out
= stuff
1301 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1302 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1303 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1304 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1305 # *screaam* FFT mode needs an extra offset for RB
1306 # similar to FRS/FRT (below). all of this needs cleanup
1307 offs
= Signal(7, name
="offs_"+rname
, reset_less
=True)
1310 # when FFT sv.ffmadd detected, and REMAP not in use,
1311 # automagically add on an extra offset to RB.
1312 # however when REMAP is active, the FFT REMAP
1313 # schedule takes care of this offset.
1314 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1315 with m
.If(~self
.remap_active
[i
]):
1316 with m
.If(svdec
.isvec
):
1317 comb
+= offs
.eq(vl
) # VL for Vectors
1318 # detect if Vectorised: add srcstep/dststep if yes.
1319 # to_reg is 7-bits, outs get dststep added, ins get srcstep
1320 with m
.If(svdec
.isvec
):
1321 selectstep
= dststep
if out
else srcstep
1322 step
= Signal(7, name
="step_%s" % rname
.lower())
1323 with m
.If(self
.remap_active
[i
]):
1324 comb
+= step
.eq(remapstep
)
1326 comb
+= step
.eq(selectstep
)
1327 # reverse gear goes the opposite way
1328 with m
.If(self
.rm_dec
.reverse_gear
):
1329 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
+(vl
-1-step
))
1331 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1333 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1335 # SVP64 in/out fields
1336 comb
+= in1_svdec
.idx
.eq(self
.op_get("sv_in1")) # reg #1 (in1_sel)
1337 comb
+= in2_svdec
.idx
.eq(self
.op_get("sv_in2")) # reg #2 (in2_sel)
1338 comb
+= in3_svdec
.idx
.eq(self
.op_get("sv_in3")) # reg #3 (in3_sel)
1339 comb
+= o_svdec
.idx
.eq(self
.op_get("sv_out")) # output (out_sel)
1341 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out2"))
1342 # XXX TODO - work out where this should come from. the problem is
1343 # that LD-with-update is implied (computed from "is instruction in
1344 # "update mode" rather than specified cleanly as its own CSV column
1346 # output reg-is-vectorised (and when no in/out is vectorised)
1347 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1348 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1349 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1350 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1351 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1353 # urrr... don't ask... the implicit register FRS in FFT mode
1354 # "tracks" FRT exactly except it's offset by VL. rather than
1355 # mess up the above with if-statements, override it here.
1356 # same trick is applied to FRA, above, but it's a lot cleaner, there
1357 with m
.If(dec_o2
.reg_out
.ok
& dec_o2
.fp_madd_en
):
1359 with m
.If(~self
.remap_active
[4]):
1360 with m
.If(o2_svdec
.isvec
):
1361 comb
+= offs
.eq(vl
) # VL for Vectors
1363 comb
+= offs
.eq(1) # add 1 if scalar
1364 svdec
= o_svdec
# yes take source as o_svdec...
1365 with m
.If(svdec
.isvec
):
1366 step
= Signal(7, name
="step_%s" % rname
.lower())
1367 with m
.If(self
.remap_active
[4]):
1368 comb
+= step
.eq(o2_step
)
1370 comb
+= step
.eq(dststep
)
1371 # reverse gear goes the opposite way
1372 with m
.If(self
.rm_dec
.reverse_gear
):
1373 roffs
= offs
+(vl
-1-step
)
1374 comb
+= to_reg
.data
.eq(roffs
+svdec
.reg_out
)
1376 comb
+= to_reg
.data
.eq(offs
+step
+svdec
.reg_out
)
1378 comb
+= to_reg
.data
.eq(offs
+svdec
.reg_out
)
1379 # ... but write to *second* output
1380 comb
+= self
.o2_isvec
.eq(svdec
.isvec
)
1381 comb
+= o2_svdec
.idx
.eq(self
.op_get("sv_out"))
1383 # TODO add SPRs here. must be True when *all* are scalar
1384 l
= map(lambda svdec
: svdec
.isvec
, [in1_svdec
, in2_svdec
, in3_svdec
,
1385 crin_svdec
, crin_svdec_b
,
1387 comb
+= self
.no_in_vec
.eq(~
Cat(*l
).bool()) # all input scalar
1388 l
= map(lambda svdec
: svdec
.isvec
, [
1389 o2_svdec
, o_svdec
, crout_svdec
])
1390 # in mapreduce mode, scalar out is *allowed*
1391 with m
.If(self
.rm_dec
.mode
== SVP64RMMode
.MAPREDUCE
.value
):
1392 comb
+= self
.no_out_vec
.eq(0)
1395 comb
+= self
.no_out_vec
.eq(~
Cat(*l
).bool())
1396 # now create a general-purpose "test" as to whether looping
1397 # should continue. this doesn't include predication bit-tests
1398 loop
= self
.loop_continue
1399 with m
.Switch(self
.op_get("SV_Ptype")):
1400 with m
.Case(SVPtype
.P2
.value
):
1402 # TODO: *and cache-inhibited LD/ST!*
1403 comb
+= loop
.eq(~
(self
.no_in_vec | self
.no_out_vec
))
1404 with m
.Case(SVPtype
.P1
.value
):
1405 # single-predication, test relies on dest only
1406 comb
+= loop
.eq(~self
.no_out_vec
)
1408 # not an SV operation, no looping
1411 # condition registers (CR)
1412 for to_reg
, cr
, name
, svdec
, out
in (
1413 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", crin_svdec
, 0),
1414 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", crin_svdec_b
, 0),
1415 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", crin_svdec_o
, 0),
1416 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", crout_svdec
, 1)):
1417 fromreg
= getattr(cr
, name
)
1418 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1419 comb
+= svdec
.etype
.eq(sv_etype
) # EXTRA2/3 for this insn
1420 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1421 with m
.If(svdec
.isvec
):
1422 # check if this is CR0 or CR1: treated differently
1423 # (does not "listen" to EXTRA2/3 spec for a start)
1424 # also: the CRs start from completely different locations
1425 step
= dststep
if out
else srcstep
1426 with m
.If(cr
.sv_override
== 1): # CR0
1427 offs
= SVP64CROffs
.CR0
1428 comb
+= to_reg
.data
.eq(step
+offs
)
1429 with m
.Elif(cr
.sv_override
== 2): # CR1
1430 offs
= SVP64CROffs
.CR1
1431 comb
+= to_reg
.data
.eq(step
+1)
1433 comb
+= to_reg
.data
.eq(step
+svdec
.cr_out
) # 7-bit out
1435 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1436 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1438 # sigh must determine if RA is nonzero (7 bit)
1439 comb
+= self
.sv_a_nz
.eq(e
.read_reg1
.data
!= Const(0, 7))
1441 # connect up to/from read/write GPRs
1442 for to_reg
, fromreg
in ((e
.read_reg1
, dec_a
.reg_out
),
1443 (e
.read_reg2
, dec_b
.reg_out
),
1444 (e
.read_reg3
, dec_c
.reg_out
),
1445 (e
.write_reg
, dec_o
.reg_out
),
1446 (e
.write_ea
, dec_o2
.reg_out
)):
1447 comb
+= to_reg
.data
.eq(fromreg
.data
)
1448 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1450 # connect up to/from read/write CRs
1451 for to_reg
, cr
, name
in (
1452 (e
.read_cr1
, self
.dec_cr_in
, "cr_bitfield", ),
1453 (e
.read_cr2
, self
.dec_cr_in
, "cr_bitfield_b", ),
1454 (e
.read_cr3
, self
.dec_cr_in
, "cr_bitfield_o", ),
1455 (e
.write_cr
, self
.dec_cr_out
, "cr_bitfield", )):
1456 fromreg
= getattr(cr
, name
)
1457 comb
+= to_reg
.data
.eq(fromreg
.data
)
1458 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1461 comb
+= self
.rm_dec
.ldst_ra_vec
.eq(self
.in1_isvec
) # RA is vector
1464 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1465 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1467 # Fast regs out including SRR0/1/SVSRR0
1468 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1469 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1470 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
) # SRR0 (OP_RFID)
1471 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
) # SRR1 (ditto)
1472 comb
+= e
.write_fast3
.eq(dec_o2
.fast_out3
) # SVSRR0 (ditto)
1474 # sigh this is exactly the sort of thing for which the
1475 # decoder is designed to not need. MTSPR, MFSPR and others need
1476 # access to the XER bits. however setting e.oe is not appropriate
1477 internal_op
= self
.op_get("internal_op")
1478 with m
.If(internal_op
== MicrOp
.OP_MFSPR
):
1479 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1480 with m
.If(internal_op
== MicrOp
.OP_CMP
):
1481 comb
+= e
.xer_in
.eq(1 << XERRegsEnum
.SO
) # SO
1482 with m
.If(internal_op
== MicrOp
.OP_MTSPR
):
1483 comb
+= e
.xer_out
.eq(1)
1485 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1486 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1487 # *DO NOT* call self.trap here. that would reset absolutely
1488 # everything including destroying read of RA and RB.
1489 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1491 ####################
1492 # ok so the instruction's been decoded, blah blah, however
1493 # now we need to determine if it's actually going to go ahead...
1494 # *or* if in fact it's a privileged operation, whether there's
1495 # an external interrupt, etc. etc. this is a simple priority
1496 # if-elif-elif sequence. decrement takes highest priority,
1497 # EINT next highest, privileged operation third.
1499 # check if instruction is privileged
1500 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1502 # different IRQ conditions
1503 ext_irq_ok
= Signal()
1504 dec_irq_ok
= Signal()
1507 ldst_exc
= self
.ldst_exc
1509 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1510 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1511 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1512 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1514 # absolute top priority: check for an instruction failed
1515 with m
.If(self
.instr_fault
):
1516 comb
+= self
.e
.eq(0) # reset eeeeeverything
1517 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1518 comb
+= self
.do_copy("insn_type", MicrOp
.OP_FETCH_FAILED
, True)
1519 comb
+= self
.do_copy("fn_unit", Function
.MMU
, True)
1520 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # PC
1521 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # MSR
1522 # special override on internal_op, due to being a "fake" op
1523 comb
+= self
.dec
.op
.internal_op
.eq(MicrOp
.OP_FETCH_FAILED
)
1525 # LD/ST exceptions. TestIssuer copies the exception info at us
1526 # after a failed LD/ST.
1527 with m
.Elif(ldst_exc
.happened
):
1528 with m
.If(ldst_exc
.alignment
):
1529 self
.trap(m
, TT
.PRIV
, 0x600)
1530 with m
.Elif(ldst_exc
.instr_fault
):
1531 with m
.If(ldst_exc
.segment_fault
):
1532 self
.trap(m
, TT
.PRIV
, 0x480)
1534 # pass exception info to trap to create SRR1
1535 self
.trap(m
, TT
.MEMEXC
, 0x400, ldst_exc
)
1537 with m
.If(ldst_exc
.segment_fault
):
1538 self
.trap(m
, TT
.PRIV
, 0x380)
1540 self
.trap(m
, TT
.PRIV
, 0x300)
1542 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1543 with m
.Elif(dec_irq_ok
):
1544 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1546 # external interrupt? only if MSR.EE set
1547 with m
.Elif(ext_irq_ok
):
1548 self
.trap(m
, TT
.EINT
, 0x500)
1550 # privileged instruction trap
1551 with m
.Elif(priv_ok
):
1552 self
.trap(m
, TT
.PRIV
, 0x700)
1554 # illegal instruction must redirect to trap. this is done by
1555 # *overwriting* the decoded instruction and starting again.
1556 # (note: the same goes for interrupts and for privileged operations,
1557 # just with different trapaddr and traptype)
1558 with m
.Elif(illeg_ok
):
1559 # illegal instruction trap
1560 self
.trap(m
, TT
.ILLEG
, 0x700)
1562 # no exception, just copy things to the output
1566 ####################
1567 # follow-up after trap/irq to set up SRR0/1
1569 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1570 # Note: OP_SC could actually be modified to just be a trap
1571 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1572 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1573 # TRAP write fast1 = SRR0
1574 comb
+= e_out
.write_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1575 comb
+= e_out
.write_fast1
.ok
.eq(1)
1576 # TRAP write fast2 = SRR1
1577 comb
+= e_out
.write_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1578 comb
+= e_out
.write_fast2
.ok
.eq(1)
1579 # TRAP write fast2 = SRR1
1580 comb
+= e_out
.write_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1581 comb
+= e_out
.write_fast3
.ok
.eq(1)
1583 # RFID: needs to read SRR0/1
1584 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1585 # TRAP read fast1 = SRR0
1586 comb
+= e_out
.read_fast1
.data
.eq(FastRegsEnum
.SRR0
) # SRR0
1587 comb
+= e_out
.read_fast1
.ok
.eq(1)
1588 # TRAP read fast2 = SRR1
1589 comb
+= e_out
.read_fast2
.data
.eq(FastRegsEnum
.SRR1
) # SRR1
1590 comb
+= e_out
.read_fast2
.ok
.eq(1)
1591 # TRAP read fast2 = SVSRR0
1592 comb
+= e_out
.read_fast3
.data
.eq(FastRegsEnum
.SVSRR0
) # SVSRR0
1593 comb
+= e_out
.read_fast3
.ok
.eq(1)
1595 # annoying simulator bug.
1596 # asmcode may end up getting used for perfcounters?
1597 asmcode
= self
.op_get("asmcode")
1598 if hasattr(e_out
, "asmcode") and asmcode
is not None:
1599 comb
+= e_out
.asmcode
.eq(asmcode
)
1603 def trap(self
, m
, traptype
, trapaddr
, ldst_exc
=None):
1604 """trap: this basically "rewrites" the decoded instruction as a trap
1608 comb
+= e
.eq(0) # reset eeeeeverything
1611 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1612 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1613 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1614 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1615 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1616 comb
+= self
.do_copy("ldst_exc", ldst_exc
, True) # request type
1617 comb
+= self
.do_copy("msr", self
.state
.msr
,
1618 True) # copy of MSR "state"
1619 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1620 comb
+= self
.do_copy("svstate", self
.state
.svstate
, True) # SVSTATE
1623 def get_rdflags(m
, e
, cu
):
1624 """returns a sequential list of the read "ok" flags for a given FU.
1625 this list is in order of the CompUnit input specs
1628 for idx
in range(cu
.n_src
):
1629 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1630 decinfo
= regspec_decode_read(m
, e
, regfile
, regname
)
1631 rdl
.append(decinfo
.okflag
)
1636 if __name__
== '__main__':
1637 pdecode
= create_pdecode()
1638 dec2
= PowerDecode2(pdecode
, svp64_en
=True)
1639 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1640 with
open("dec2.il", "w") as f
: