change ternaryi to correct register fields
[openpower-isa.git] / src / openpower / sv / sv_analysis.py
1 #!/usr/bin/env python2
2 #
3 # NOTE that this program is python2 compatible, please do not stop it
4 # from working by adding syntax that prevents that.
5 #
6 # Initial version written by lkcl Oct 2020
7 # This program analyses the Power 9 op codes and looks at in/out register uses
8 # The results are displayed:
9 # https://libre-soc.org/openpower/opcode_regs_deduped/
10 #
11 # It finds .csv files in the directory isatables/
12 # then goes through the categories and creates svp64 CSV augmentation
13 # tables on a per-opcode basis
14
15 import csv
16 import os
17 from os.path import dirname, join
18 from glob import glob
19 from collections import OrderedDict
20 from openpower.decoder.power_svp64 import SVP64RM
21 from openpower.decoder.power_enums import find_wiki_file, get_csv
22
23
24 # Write an array of dictionaries to the CSV file name:
25 def write_csv(name, items, headers):
26 file_path = find_wiki_file(name)
27 with open(file_path, 'w') as csvfile:
28 writer = csv.DictWriter(csvfile, headers, lineterminator="\n")
29 writer.writeheader()
30 writer.writerows(items)
31
32 # This will return True if all values are true.
33 # Not sure what this is about
34
35
36 def blank_key(row):
37 # for v in row.values():
38 # if 'SPR' in v: # skip all SPRs
39 # return True
40 for v in row.values():
41 if v:
42 return False
43 return True
44
45 # General purpose registers have names like: RA, RT, R1, ...
46 # Floating point registers names like: FRT, FRA, FR1, ..., FRTp, ...
47 # Return True if field is a register
48
49
50 def isreg(field):
51 return (field.startswith('R') or field.startswith('FR') or
52 field == 'SPR')
53
54
55 # These are the attributes of the instructions,
56 # register names
57 keycolumns = ['unit', 'in1', 'in2', 'in3', 'out', 'CR in', 'CR out',
58 ] # don't think we need these: 'ldst len', 'rc', 'lk']
59
60 tablecols = ['unit', 'in', 'outcnt', 'CR in', 'CR out', 'imm'
61 ] # don't think we need these: 'ldst len', 'rc', 'lk']
62
63
64 def create_key(row):
65 res = OrderedDict()
66 #print ("row", row)
67 for key in keycolumns:
68 # registers IN - special-case: count number of regs RA/RB/RC/RS
69 if key in ['in1', 'in2', 'in3']:
70 if 'in' not in res:
71 res['in'] = 0
72 if row['unit'] == 'BRANCH': # branches must not include Vector SPRs
73 continue
74 if isreg(row[key]):
75 res['in'] += 1
76
77 # registers OUT
78 if key == 'out':
79 # If upd is 1 then increment the count of outputs
80 if 'outcnt' not in res:
81 res['outcnt'] = 0
82 if isreg(row[key]):
83 res['outcnt'] += 1
84 if row['upd'] == '1':
85 res['outcnt'] += 1
86
87 # CRs (Condition Register) (CR0 .. CR7)
88 if key.startswith('CR'):
89 if row[key].startswith('NONE'):
90 res[key] = '0'
91 else:
92 res[key] = '1'
93 if row['comment'].startswith('cr'):
94 res['crop'] = '1'
95 # unit
96 if key == 'unit':
97 if row[key] == 'LDST': # we care about LDST units
98 res[key] = row[key]
99 else:
100 res[key] = 'OTHER'
101 # LDST len (LoadStore length)
102 if key.startswith('ldst'):
103 if row[key].startswith('NONE'):
104 res[key] = '0'
105 else:
106 res[key] = '1'
107 # rc, lk
108 if key in ['rc', 'lk']:
109 if row[key] == 'ONE':
110 res[key] = '1'
111 elif row[key] == 'NONE':
112 res[key] = '0'
113 else:
114 res[key] = 'R'
115 if key == 'lk':
116 res[key] = row[key]
117
118 # Convert the numerics 'in' & 'outcnt' to strings
119 res['in'] = str(res['in'])
120 res['outcnt'] = str(res['outcnt'])
121
122 # constants
123 if row['in2'].startswith('CONST_'):
124 res['imm'] = "1" # row['in2'].split("_")[1]
125 else:
126 res['imm'] = ''
127
128 return res
129
130 #
131
132
133 def dformat(d):
134 res = []
135 for k, v in d.items():
136 res.append("%s: %s" % (k, v))
137 return ' '.join(res)
138
139
140 def tformat(d):
141 return ' | '.join(d) + " |"
142
143
144 def keyname(row):
145 res = []
146 if row['unit'] != 'OTHER':
147 res.append(row['unit'])
148 if row['in'] != '0':
149 res.append('%sR' % row['in'])
150 if row['outcnt'] != '0':
151 res.append('%sW' % row['outcnt'])
152 if row['CR in'] == '1' and row['CR out'] == '1':
153 if 'crop' in row:
154 res.append("CR=2R1W")
155 else:
156 res.append("CRio")
157 elif row['CR in'] == '1':
158 res.append("CRi")
159 elif row['CR out'] == '1':
160 res.append("CRo")
161 elif 'imm' in row and row['imm']:
162 res.append("imm")
163 return '-'.join(res)
164
165
166 def process_csvs():
167 csvs = {}
168 csvs_svp64 = {}
169 bykey = {}
170 primarykeys = set()
171 dictkeys = OrderedDict()
172 immediates = {}
173 insns = {} # dictionary of CSV row, by instruction
174 insn_to_csv = {}
175
176 print("# OpenPOWER ISA register 'profile's")
177 print('')
178 print("this page is auto-generated, do not edit")
179 print("created by http://libre-soc.org/openpower/sv_analysis.py")
180 print('')
181
182 # Expand that (all .csv files)
183 pth = find_wiki_file("*.csv")
184
185 # Ignore those containing: valid test sprs
186 for fname in glob(pth):
187 print("sv analysis checking", fname)
188 _, name = os.path.split(fname)
189 if '-' in name:
190 continue
191 if 'valid' in fname:
192 continue
193 if 'test' in fname:
194 continue
195 if fname.endswith('sprs.csv'):
196 continue
197 if fname.endswith('minor_19_valid.csv'):
198 continue
199 if 'RM' in fname:
200 continue
201 csvname = os.path.split(fname)[1]
202 csvname_ = csvname.split(".")[0]
203 # csvname is something like: minor_59.csv, fname the whole path
204 csv = get_csv(fname)
205 csvs[fname] = csv
206 csvs_svp64[csvname_] = []
207 for row in csv:
208 if blank_key(row):
209 continue
210 print("row", row)
211 insn_name = row['comment']
212 condition = row['CONDITIONS']
213 # skip instructions that are not suitable
214 if insn_name.startswith("l") and insn_name.endswith("br"):
215 continue # skip pseudo-alias lxxxbr
216 if insn_name in ['mcrxr', 'mcrxrx', 'darn']:
217 continue
218 if insn_name in ['bctar', 'bcctr']:
219 continue
220 if 'rfid' in insn_name:
221 continue
222 if insn_name in ['setvl', ]: # SVP64 opcodes
223 continue
224
225 insns[(insn_name, condition)] = row # accumulate csv data
226 insn_to_csv[insn_name] = csvname_ # CSV file name by instruction
227 dkey = create_key(row)
228 key = tuple(dkey.values())
229 # print("key=", key)
230 dictkeys[key] = dkey
231 primarykeys.add(key)
232 if key not in bykey:
233 bykey[key] = []
234 bykey[key].append((csvname, row['opcode'], insn_name, condition,
235 row['form'].upper() + '-Form'))
236
237 # detect immediates, collate them (useful info)
238 if row['in2'].startswith('CONST_'):
239 imm = row['in2'].split("_")[1]
240 if key not in immediates:
241 immediates[key] = set()
242 immediates[key].add(imm)
243
244 primarykeys = list(primarykeys)
245 primarykeys.sort()
246
247 # mapping to old SVPrefix "Forms"
248 mapsto = {'3R-1W-CRo': 'RM-1P-3S1D',
249 '2R-1W-CRio': 'RM-1P-2S1D',
250 '2R-1W-CRi': 'RM-1P-3S1D',
251 '2R-1W-CRo': 'RM-1P-2S1D',
252 '2R': 'non-SV',
253 '2R-1W': 'RM-1P-2S1D',
254 '1R-CRio': 'RM-2P-2S1D',
255 '2R-CRio': 'RM-1P-2S1D',
256 '2R-CRo': 'RM-1P-2S1D',
257 '1R': 'non-SV',
258 '1R-1W-CRio': 'RM-2P-1S1D',
259 '1R-1W-CRo': 'RM-2P-1S1D',
260 '1R-1W': 'RM-2P-1S1D',
261 '1R-1W-imm': 'RM-2P-1S1D',
262 '1R-CRo': 'RM-2P-1S1D',
263 '1R-imm': 'non-SV',
264 '1W-CRo': 'RM-1P-1D',
265 '1W': 'non-SV',
266 '1W-CRi': 'RM-2P-1S1D',
267 'CRio': 'RM-2P-1S1D',
268 'CR=2R1W': 'RM-1P-2S1D',
269 'CRi': 'non-SV',
270 'imm': 'non-SV',
271 '': 'non-SV',
272 'LDST-2R-imm': 'LDSTRM-2P-2S',
273 'LDST-2R-1W-imm': 'LDSTRM-2P-2S1D',
274 'LDST-2R-1W': 'LDSTRM-2P-2S1D',
275 'LDST-2R-2W': 'LDSTRM-2P-2S1D',
276 'LDST-1R-1W-imm': 'LDSTRM-2P-1S1D',
277 'LDST-1R-2W-imm': 'LDSTRM-2P-1S2D',
278 'LDST-3R': 'LDSTRM-2P-3S',
279 'LDST-3R-CRo': 'LDSTRM-2P-3S', # st*x
280 'LDST-3R-1W': 'LDSTRM-2P-2S1D', # st*x
281 }
282 print("# map to old SV Prefix")
283 print('')
284 print('[[!table data="""')
285 for key in primarykeys:
286 name = keyname(dictkeys[key])
287 value = mapsto.get(name, "-")
288 print(tformat([name, value + " "]))
289 print('"""]]')
290 print('')
291
292 print("# keys")
293 print('')
294 print('[[!table data="""')
295 print(tformat(tablecols) + " imms | name |")
296
297 # print out the keys and the table from which they're derived
298 for key in primarykeys:
299 name = keyname(dictkeys[key])
300 row = tformat(dictkeys[key].values())
301 imms = list(immediates.get(key, ""))
302 imms.sort()
303 row += " %s | " % ("/".join(imms))
304 row += " %s |" % name
305 print(row)
306 print('"""]]')
307 print('')
308
309 # print out, by remap name, all the instructions under that category
310 for key in primarykeys:
311 name = keyname(dictkeys[key])
312 value = mapsto.get(name, "-")
313 print("## %s (%s)" % (name, value))
314 print('')
315 print('[[!table data="""')
316 print(tformat(['CSV', 'opcode', 'asm', 'form']))
317 rows = bykey[key]
318 rows.sort()
319 for row in rows:
320 print(tformat(row))
321 print('"""]]')
322 print('')
323
324 # for fname, csv in csvs.items():
325 # print (fname)
326
327 # for insn, row in insns.items():
328 # print (insn, row)
329
330 print("# svp64 remaps")
331 svp64 = OrderedDict()
332 # create a CSV file, per category, with SV "augmentation" info
333 # XXX note: 'out2' not added here, needs to be added to CSV files
334 # KEEP TRACK OF THESE https://bugs.libre-soc.org/show_bug.cgi?id=619
335 csvcols = ['insn', 'CONDITIONS', 'Ptype', 'Etype', '0', '1', '2', '3']
336 csvcols += ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out'] # temporary
337 for key in primarykeys:
338 # get the decoded key containing row-analysis, and name/value
339 dkey = dictkeys[key]
340 name = keyname(dkey)
341 value = mapsto.get(name, "-")
342 if value == 'non-SV':
343 continue
344
345 # print out svp64 tables by category
346 print("* **%s**: %s" % (name, value))
347
348 # store csv entries by svp64 RM category
349 if value not in svp64:
350 svp64[value] = []
351
352 rows = bykey[key]
353 rows.sort()
354
355 for row in rows:
356 # for idx in range(len(row)):
357 # if row[idx] == 'NONE':
358 # row[idx] = ''
359 # get the instruction
360 print(key, row)
361 insn_name = row[2]
362 condition = row[3]
363 insn = insns[(insn_name, condition)]
364 # start constructing svp64 CSV row
365 res = OrderedDict()
366 res['insn'] = insn_name
367 res['CONDITIONS'] = condition
368 res['Ptype'] = value.split('-')[1] # predication type (RM-xN-xxx)
369 # get whether R_xxx_EXTRAn fields are 2-bit or 3-bit
370 res['Etype'] = 'EXTRA2'
371 # go through each register matching to Rxxxx_EXTRAx
372 for k in ['0', '1', '2', '3']:
373 res[k] = ''
374 # create "fake" out2 (TODO, needs to be added to CSV files)
375 # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
376 res['out2'] = 'NONE'
377 if insn['upd'] == '1': # LD/ST with update has RA as out2
378 res['out2'] = 'RA'
379
380 # temporary useful info
381 regs = []
382 for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
383 if insn[k].startswith('CONST'):
384 res[k] = ''
385 regs.append('')
386 else:
387 res[k] = insn[k]
388 if insn[k] == 'RA_OR_ZERO':
389 regs.append('RA')
390 elif insn[k] != 'NONE':
391 regs.append(insn[k])
392 else:
393 regs.append('')
394
395 print("regs", insn_name, regs)
396
397 # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0
398 if insn_name.startswith("lf"):
399 dRT = 'd:FRT'
400 dCR = 'd:CR1'
401 else:
402 dRT = 'd:RT'
403 dCR = 'd:CR0'
404 if insn_name.startswith("stf"):
405 sRS = 's:FRS'
406 dCR = 'd:CR1'
407 else:
408 sRS = 's:RS'
409 dCR = 'd:CR0'
410
411 # sigh now the fun begins. this isn't the sanest way to do it
412 # but the patterns are pretty regular.
413
414 if value == 'LDSTRM-2P-1S1D':
415 res['Etype'] = 'EXTRA3' # RM EXTRA3 type
416 res['0'] = dRT # RT: Rdest_EXTRA3
417 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
418
419 elif value == 'LDSTRM-2P-1S2D':
420 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
421 res['0'] = dRT # RT: Rdest_EXTRA3
422 res['1'] = 'd:RA' # RA: Rdest2_EXTRA2
423 res['2'] = 's:RA' # RA: Rsrc1_EXTRA2
424
425 elif value == 'LDSTRM-2P-2S':
426 # stw, std, sth, stb
427 res['Etype'] = 'EXTRA3' # RM EXTRA2 type
428 res['0'] = sRS # RS: Rdest1_EXTRA2
429 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
430
431 elif value == 'LDSTRM-2P-2S1D':
432 if 'st' in insn_name and 'x' not in insn_name: # stwu/stbu etc
433 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
434 res['0'] = 'd:RA' # RA: Rdest1_EXTRA2
435 res['1'] = sRS # RS: Rdsrc1_EXTRA2
436 res['2'] = 's:RA' # RA: Rsrc2_EXTRA2
437 elif 'st' in insn_name and 'x' in insn_name: # stwux
438 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
439 res['0'] = 'd:RA' # RA: Rdest1_EXTRA2
440 # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2
441 res['1'] = sRS+'s:RA'
442 res['2'] = 's:RB' # RB: Rsrc2_EXTRA2
443 elif 'u' in insn_name: # ldux etc.
444 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
445 res['0'] = dRT # RT: Rdest1_EXTRA2
446 res['1'] = 'd:RA' # RA: Rdest2_EXTRA2
447 res['2'] = 's:RB' # RB: Rsrc1_EXTRA2
448 else:
449 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
450 res['0'] = dRT # RT: Rdest1_EXTRA2
451 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
452 res['2'] = 's:RB' # RB: Rsrc2_EXTRA2
453
454 elif value == 'LDSTRM-2P-3S':
455 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
456 if 'cx' in insn_name:
457 res['0'] = sRS+dCR # RS: Rsrc1_EXTRA2 CR0: dest
458 else:
459 res['0'] = sRS # RS: Rsrc1_EXTRA2
460 res['1'] = 's:RA' # RA: Rsrc2_EXTRA2
461 res['2'] = 's:RB' # RA: Rsrc3_EXTRA2
462
463 elif value == 'RM-2P-1S1D':
464 res['Etype'] = 'EXTRA3' # RM EXTRA3 type
465 if insn_name == 'mtspr':
466 res['0'] = 'd:SPR' # SPR: Rdest1_EXTRA3
467 res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
468 elif insn_name == 'mfspr':
469 res['0'] = 'd:RS' # RS: Rdest1_EXTRA3
470 res['1'] = 's:SPR' # SPR: Rsrc1_EXTRA3
471 elif name == 'CRio' and insn_name == 'mcrf':
472 res['0'] = 'd:BF' # BFA: Rdest1_EXTRA3
473 res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
474 elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
475 res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
476 res['1'] = 's:CR' # CR: Rsrc1_EXTRA3
477 elif insn_name == 'setb':
478 res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
479 res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3
480 elif insn_name.startswith('cmp'): # cmpi
481 res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
482 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
483 elif regs == ['RA', '', '', 'RT', '', '']:
484 res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
485 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
486 elif regs == ['RA', '', '', 'RT', '', 'CR0']:
487 res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3
488 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
489 elif (regs == ['RS', '', '', 'RA', '', 'CR0'] or
490 regs == ['', '', 'RS', 'RA', '', 'CR0']):
491 res['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
492 res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
493 elif regs == ['RS', '', '', 'RA', '', '']:
494 res['0'] = 'd:RA' # RA: Rdest1_EXTRA3
495 res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
496 elif regs == ['', 'FRB', '', 'FRT', '0', 'CR1']:
497 res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
498 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
499 elif regs == ['', 'FRB', '', '', '', 'CR1']:
500 res['0'] = 'd:CR1' # CR1: Rdest1_EXTRA3
501 res['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3
502 elif regs == ['', 'FRB', '', '', '', 'BF']:
503 res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
504 res['1'] = 's:FRB' # FRA: Rsrc1_EXTRA3
505 elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
506 res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
507 res['1'] = 's:FRB' # FRB: Rsrc1_EXTRA3
508 elif insn_name.startswith('bc'):
509 res['0'] = 'd:BI' # BI: Rdest1_EXTRA3
510 res['1'] = 's:BI' # BI: Rsrc1_EXTRA3
511 else:
512 res['0'] = 'TODO'
513
514 elif value == 'RM-1P-2S1D':
515 res['Etype'] = 'EXTRA3' # RM EXTRA3 type
516 if insn_name.startswith('cr'):
517 res['0'] = 'd:BT' # BT: Rdest1_EXTRA3
518 res['1'] = 's:BA' # BA: Rsrc1_EXTRA3
519 res['2'] = 's:BB' # BB: Rsrc2_EXTRA3
520 elif regs == ['FRA', '', 'FRC', 'FRT', '', 'CR1']:
521 res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
522 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
523 res['2'] = 's:FRC' # FRC: Rsrc1_EXTRA3
524 # should be for fcmp
525 elif regs == ['FRA', 'FRB', '', '', '', 'BF']:
526 res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
527 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
528 res['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
529 elif regs == ['FRA', 'FRB', '', 'FRT', '', '']:
530 res['0'] = 'd:FRT' # FRT: Rdest1_EXTRA3
531 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
532 res['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
533 elif regs == ['FRA', 'FRB', '', 'FRT', '', 'CR1']:
534 res['0'] = 'd:FRT;d:CR1' # FRT,CR1: Rdest1_EXTRA3
535 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA3
536 res['2'] = 's:FRB' # FRB: Rsrc1_EXTRA3
537 elif name == '2R-1W' or insn_name == 'cmpb': # cmpb
538 if insn_name in ['bpermd', 'cmpb']:
539 res['0'] = 'd:RA' # RA: Rdest1_EXTRA3
540 res['1'] = 's:RS' # RS: Rsrc1_EXTRA3
541 else:
542 res['0'] = 'd:RT' # RT: Rdest1_EXTRA3
543 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
544 res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
545 elif insn_name.startswith('cmp'): # cmp
546 res['0'] = 'd:BF' # BF: Rdest1_EXTRA3
547 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
548 res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
549 elif (regs == ['', 'RB', 'RS', 'RA', '', 'CR0'] or
550 regs == ['RS', 'RB', '', 'RA', '', 'CR0']):
551 res['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
552 res['1'] = 's:RB' # RB: Rsrc1_EXTRA3
553 res['2'] = 's:RS' # RS: Rsrc1_EXTRA3
554 elif regs == ['RA', 'RB', '', 'RT', '', 'CR0']:
555 res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA3
556 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
557 res['2'] = 's:RB' # RB: Rsrc1_EXTRA3
558 elif regs == ['RA', '', 'RS', 'RA', '', 'CR0']:
559 res['0'] = 'd:RA;d:CR0' # RA,CR0: Rdest1_EXTRA3
560 res['1'] = 's:RA' # RA: Rsrc1_EXTRA3
561 res['2'] = 's:RS' # RS: Rsrc1_EXTRA3
562 else:
563 res['0'] = 'TODO'
564
565 elif value == 'RM-2P-2S1D':
566 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
567 if insn_name.startswith('mt'): # mtcrf
568 res['0'] = 'd:CR' # CR: Rdest1_EXTRA2
569 res['1'] = 's:RS' # RS: Rsrc1_EXTRA2
570 res['2'] = 's:CR' # CR: Rsrc2_EXTRA2
571 else:
572 res['0'] = 'TODO'
573
574 elif value == 'RM-1P-3S1D':
575 res['Etype'] = 'EXTRA2' # RM EXTRA2 type
576 if regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']:
577 res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2
578 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
579 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2
580 res['3'] = 's:RT' # RT: Rsrc3_EXTRA2
581 elif insn_name == 'isel':
582 res['0'] = 'd:RT' # RT: Rdest1_EXTRA2
583 res['1'] = 's:RA' # RA: Rsrc1_EXTRA2
584 res['2'] = 's:RB' # RT: Rsrc2_EXTRA2
585 res['3'] = 's:BC' # BC: Rsrc3_EXTRA2
586 else:
587 res['0'] = 'd:FRT;d:CR1' # FRT, CR1: Rdest1_EXTRA2
588 res['1'] = 's:FRA' # FRA: Rsrc1_EXTRA2
589 res['2'] = 's:FRB' # FRB: Rsrc2_EXTRA2
590 res['3'] = 's:FRC' # FRC: Rsrc3_EXTRA2
591
592 elif value == 'RM-1P-1D':
593 res['Etype'] = 'EXTRA3' # RM EXTRA3 type
594 if insn_name == 'svstep':
595 res['0'] = 'd:RT;d:CR0' # RT,CR0: Rdest1_EXTRA2
596
597 # add to svp64 csvs
598 # for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
599 # del res[k]
600 # if res['0'] != 'TODO':
601 for k in res:
602 if k == 'CONDITIONS':
603 continue
604 if res[k] == 'NONE' or res[k] == '':
605 res[k] = '0'
606 svp64[value].append(res)
607 # also add to by-CSV version
608 csv_fname = insn_to_csv[insn_name]
609 csvs_svp64[csv_fname].append(res)
610
611 print('')
612
613 # now write out the csv files
614 for value, csv in svp64.items():
615 # print out svp64 tables by category
616 print("## %s" % value)
617 print('')
618 print('[[!table format=csv file="openpower/isatables/%s.csv"]]' %
619 value)
620 print('')
621
622 #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
623 write_csv("%s.csv" % value, csv, csvcols + ['out2'])
624
625 # okaaay, now we re-read them back in for producing microwatt SV
626
627 # get SVP64 augmented CSV files
628 svt = SVP64RM(microwatt_format=True)
629 # Expand that (all .csv files)
630 pth = find_wiki_file("*.csv")
631
632 # Ignore those containing: valid test sprs
633 for fname in glob(pth):
634 print("post-checking", fname)
635 _, name = os.path.split(fname)
636 if '-' in name:
637 continue
638 if 'valid' in fname:
639 continue
640 if 'test' in fname:
641 continue
642 if fname.endswith('sprs.csv'):
643 continue
644 if fname.endswith('minor_19_valid.csv'):
645 continue
646 if 'RM' in fname:
647 continue
648 svp64_csv = svt.get_svp64_csv(fname)
649
650 csvcols = ['insn', 'Ptype', 'Etype']
651 csvcols += ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
652
653 # and a nice microwatt VHDL file
654 file_path = find_wiki_file("sv_decode.vhdl")
655 with open(file_path, 'w') as vhdl:
656 # autogeneration warning
657 vhdl.write("-- this file is auto-generated, do not edit\n")
658 vhdl.write("-- http://libre-soc.org/openpower/sv_analysis.py\n")
659 vhdl.write("-- part of Libre-SOC, sponsored by NLnet\n")
660 vhdl.write("\n")
661
662 # first create array types
663 lens = {'major': 63,
664 'minor_4': 63,
665 'minor_19': 7,
666 'minor_30': 15,
667 'minor_31': 1023,
668 'minor_58': 63,
669 'minor_59': 31,
670 'minor_62': 63,
671 'minor_63l': 511,
672 'minor_63h': 16,
673 }
674 for value, csv in csvs_svp64.items():
675 # munge name
676 value = value.lower()
677 value = value.replace("-", "_")
678 if value not in lens:
679 todo = " -- TODO %s (or no SVP64 augmentation)\n"
680 vhdl.write(todo % value)
681 continue
682 width = lens[value]
683 typarray = " type sv_%s_rom_array_t is " \
684 "array(0 to %d) of sv_decode_rom_t;\n"
685 vhdl.write(typarray % (value, width))
686
687 # now output structs
688 sv_cols = ['sv_in1', 'sv_in2', 'sv_in3', 'sv_out', 'sv_out2',
689 'sv_cr_in', 'sv_cr_out']
690 fullcols = csvcols + sv_cols
691 hdr = "\n" \
692 " constant sv_%s_decode_rom_array :\n" \
693 " sv_%s_rom_array_t := (\n" \
694 " -- %s\n"
695 ftr = " others => sv_illegal_inst\n" \
696 " );\n\n"
697 for value, csv in csvs_svp64.items():
698 # munge name
699 value = value.lower()
700 value = value.replace("-", "_")
701 if value not in lens:
702 continue
703 vhdl.write(hdr % (value, value, " ".join(fullcols)))
704 for entry in csv:
705 insn = str(entry['insn'])
706 condition = str(entry['CONDITIONS'])
707 sventry = svt.svp64_instrs.get(insn, None)
708 op = insns[(insn, condition)]['opcode']
709 # binary-to-vhdl-binary
710 if op.startswith("0b"):
711 op = "2#%s#" % op[2:]
712 row = []
713 for colname in csvcols[1:]:
714 re = entry[colname]
715 # zero replace with NONE
716 if re == '0':
717 re = 'NONE'
718 # 1/2 predication
719 re = re.replace("1P", "P1")
720 re = re.replace("2P", "P2")
721 row.append(re)
722 print("sventry", sventry)
723 for colname in sv_cols:
724 if sventry is None:
725 re = 'NONE'
726 else:
727 re = sventry[colname]
728 row.append(re)
729 row = ', '.join(row)
730 vhdl.write(" %13s => (%s), -- %s\n" % (op, row, insn))
731 vhdl.write(ftr)
732
733
734 if __name__ == '__main__':
735 process_csvs()