1 from openpower
.test
.common
import TestAccumulatorBase
2 from openpower
.sv
.trans
.svp64
import SVP64Asm
3 from openpower
.test
.state
import ExpectedState
4 from openpower
.simulator
.program
import Program
7 # FIXME: output values are just what my computer produces for the current
8 # simulator, they are probably not all correct.
11 class FPTransCases(TestAccumulatorBase
):
12 def case_fatan2s(self
):
13 lst
= list(SVP64Asm(["fatan2s 3,4,5"]))
16 fprs
[4] = 0x3ff0000000000000 # 1.0
17 fprs
[5] = 0x3ff0000000000000 # 1.0
18 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
19 e
.fpregs
[3] = 0x3fe921fb60000000 # pi/4 as f32 as f64
20 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
22 def case_fatan2s_(self
):
23 lst
= list(SVP64Asm(["fatan2s. 3,4,5"]))
26 fprs
[4] = 0x3ff0000000000000 # 1.0
27 fprs
[5] = 0x3ff0000000000000 # 1.0
28 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
29 e
.fpregs
[3] = 0x3fe921fb60000000 # pi/4 as f32 as f64
31 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
33 def case_fatan2(self
):
34 lst
= list(SVP64Asm(["fatan2 3,4,5"]))
37 fprs
[4] = 0x3ff0000000000000 # 1.0
38 fprs
[5] = 0x3ff0000000000000 # 1.0
39 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
40 e
.fpregs
[3] = 0x3fe921fb54442d18
41 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
43 def case_fatan2_(self
):
44 lst
= list(SVP64Asm(["fatan2. 3,4,5"]))
47 fprs
[4] = 0x3ff0000000000000 # 1.0
48 fprs
[5] = 0x3ff0000000000000 # 1.0
49 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
50 e
.fpregs
[3] = 0x3fe921fb54442d18
52 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
54 def case_fatan2pis(self
):
55 lst
= list(SVP64Asm(["fatan2pis 3,4,5"]))
58 fprs
[4] = 0x3ff0000000000000 # 1.0
59 fprs
[5] = 0x3ff0000000000000 # 1.0
60 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
61 e
.fpregs
[3] = 0x3fd0000000000000
62 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
64 def case_fatan2pis_(self
):
65 lst
= list(SVP64Asm(["fatan2pis. 3,4,5"]))
68 fprs
[4] = 0x3ff0000000000000 # 1.0
69 fprs
[5] = 0x3ff0000000000000 # 1.0
70 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
71 e
.fpregs
[3] = 0x3fd0000000000000
73 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
75 def case_fatan2pi(self
):
76 lst
= list(SVP64Asm(["fatan2pi 3,4,5"]))
79 fprs
[4] = 0x3ff0000000000000 # 1.0
80 fprs
[5] = 0x3ff0000000000000 # 1.0
81 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
82 e
.fpregs
[3] = 0x3fd0000000000000
83 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
85 def case_fatan2pi_(self
):
86 lst
= list(SVP64Asm(["fatan2pi. 3,4,5"]))
89 fprs
[4] = 0x3ff0000000000000 # 1.0
90 fprs
[5] = 0x3ff0000000000000 # 1.0
91 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
92 e
.fpregs
[3] = 0x3fd0000000000000
94 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
97 lst
= list(SVP64Asm(["fpows 3,4,5"]))
100 fprs
[4] = 0x3ff0000000000000 # 1.0
101 fprs
[5] = 0x3ff0000000000000 # 1.0
102 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
103 e
.fpregs
[3] = 0x3ff0000000000000
104 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
106 def case_fpows_(self
):
107 lst
= list(SVP64Asm(["fpows. 3,4,5"]))
110 fprs
[4] = 0x3ff0000000000000 # 1.0
111 fprs
[5] = 0x3ff0000000000000 # 1.0
112 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
113 e
.fpregs
[3] = 0x3ff0000000000000
115 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
118 lst
= list(SVP64Asm(["fpow 3,4,5"]))
121 fprs
[4] = 0x3ff0000000000000 # 1.0
122 fprs
[5] = 0x3ff0000000000000 # 1.0
123 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
124 e
.fpregs
[3] = 0x3ff0000000000000
125 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
127 def case_fpow_(self
):
128 lst
= list(SVP64Asm(["fpow. 3,4,5"]))
131 fprs
[4] = 0x3ff0000000000000 # 1.0
132 fprs
[5] = 0x3ff0000000000000 # 1.0
133 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
134 e
.fpregs
[3] = 0x3ff0000000000000
136 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
138 def case_fpowns(self
):
139 lst
= list(SVP64Asm(["fpowns 3,4,5"]))
142 fprs
[4] = 0x3ff0000000000000 # 1.0
144 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
145 e
.fpregs
[3] = 0x3ff0000000000000
146 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
148 def case_fpowns_(self
):
149 lst
= list(SVP64Asm(["fpowns. 3,4,5"]))
152 fprs
[4] = 0x3ff0000000000000 # 1.0
154 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
155 e
.fpregs
[3] = 0x3ff0000000000000
157 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
159 def case_fpown(self
):
160 lst
= list(SVP64Asm(["fpown 3,4,5"]))
163 fprs
[4] = 0x3ff0000000000000 # 1.0
165 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
166 e
.fpregs
[3] = 0x3ff0000000000000
167 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
169 def case_fpown_(self
):
170 lst
= list(SVP64Asm(["fpown. 3,4,5"]))
173 fprs
[4] = 0x3ff0000000000000 # 1.0
175 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
176 e
.fpregs
[3] = 0x3ff0000000000000
178 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
180 def case_fpowrs(self
):
181 lst
= list(SVP64Asm(["fpowrs 3,4,5"]))
184 fprs
[4] = 0x3ff0000000000000 # 1.0
185 fprs
[5] = 0x3ff0000000000000 # 1.0
186 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
187 e
.fpregs
[3] = 0x3ff0000000000000
188 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
190 def case_fpowrs_(self
):
191 lst
= list(SVP64Asm(["fpowrs. 3,4,5"]))
194 fprs
[4] = 0x3ff0000000000000 # 1.0
195 fprs
[5] = 0x3ff0000000000000 # 1.0
196 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
197 e
.fpregs
[3] = 0x3ff0000000000000
199 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
201 def case_fpowr(self
):
202 lst
= list(SVP64Asm(["fpowr 3,4,5"]))
205 fprs
[4] = 0x3ff0000000000000 # 1.0
206 fprs
[5] = 0x3ff0000000000000 # 1.0
207 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
208 e
.fpregs
[3] = 0x3ff0000000000000
209 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
211 def case_fpowr_(self
):
212 lst
= list(SVP64Asm(["fpowr. 3,4,5"]))
215 fprs
[4] = 0x3ff0000000000000 # 1.0
216 fprs
[5] = 0x3ff0000000000000 # 1.0
217 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
218 e
.fpregs
[3] = 0x3ff0000000000000
220 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
222 def case_frootns(self
):
223 lst
= list(SVP64Asm(["frootns 3,4,5"]))
226 fprs
[4] = 0x3ff0000000000000 # 1.0
228 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
229 e
.fpregs
[3] = 0x3ff0000000000000
230 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
232 def case_frootns_(self
):
233 lst
= list(SVP64Asm(["frootns. 3,4,5"]))
236 fprs
[4] = 0x3ff0000000000000 # 1.0
238 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
239 e
.fpregs
[3] = 0x3ff0000000000000
241 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
243 def case_frootn(self
):
244 lst
= list(SVP64Asm(["frootn 3,4,5"]))
247 fprs
[4] = 0x3ff0000000000000 # 1.0
249 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
250 e
.fpregs
[3] = 0x3ff0000000000000
251 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
253 def case_frootn_(self
):
254 lst
= list(SVP64Asm(["frootn. 3,4,5"]))
257 fprs
[4] = 0x3ff0000000000000 # 1.0
259 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
260 e
.fpregs
[3] = 0x3ff0000000000000
262 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
264 def case_fhypots(self
):
265 lst
= list(SVP64Asm(["fhypots 3,4,5"]))
268 fprs
[4] = 0x3ff0000000000000 # 1.0
269 fprs
[5] = 0x3ff0000000000000 # 1.0
270 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
271 e
.fpregs
[3] = 0x3ff6a09e60000000
272 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
274 def case_fhypots_(self
):
275 lst
= list(SVP64Asm(["fhypots. 3,4,5"]))
278 fprs
[4] = 0x3ff0000000000000 # 1.0
279 fprs
[5] = 0x3ff0000000000000 # 1.0
280 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
281 e
.fpregs
[3] = 0x3ff6a09e60000000
283 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
285 def case_fhypot(self
):
286 lst
= list(SVP64Asm(["fhypot 3,4,5"]))
289 fprs
[4] = 0x3ff0000000000000 # 1.0
290 fprs
[5] = 0x3ff0000000000000 # 1.0
291 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
292 e
.fpregs
[3] = 0x3ff6a09e667f3bcd
293 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
295 def case_fhypot_(self
):
296 lst
= list(SVP64Asm(["fhypot. 3,4,5"]))
299 fprs
[4] = 0x3ff0000000000000 # 1.0
300 fprs
[5] = 0x3ff0000000000000 # 1.0
301 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
302 e
.fpregs
[3] = 0x3ff6a09e667f3bcd
304 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
306 def case_frsqrts(self
):
307 lst
= list(SVP64Asm(["frsqrts 3,4"]))
310 fprs
[4] = 0x3ff0000000000000 # 1.0
311 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
312 e
.fpregs
[3] = 0x3ff0000000000000
313 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
315 def case_frsqrts_(self
):
316 lst
= list(SVP64Asm(["frsqrts. 3,4"]))
319 fprs
[4] = 0x3ff0000000000000 # 1.0
320 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
321 e
.fpregs
[3] = 0x3ff0000000000000
323 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
325 def case_frsqrt(self
):
326 lst
= list(SVP64Asm(["frsqrt 3,4"]))
329 fprs
[4] = 0x3ff0000000000000 # 1.0
330 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
331 e
.fpregs
[3] = 0x3ff0000000000000
332 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
334 def case_frsqrt_(self
):
335 lst
= list(SVP64Asm(["frsqrt. 3,4"]))
338 fprs
[4] = 0x3ff0000000000000 # 1.0
339 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
340 e
.fpregs
[3] = 0x3ff0000000000000
342 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
344 def case_fcbrts(self
):
345 lst
= list(SVP64Asm(["fcbrts 3,4"]))
348 fprs
[4] = 0x3ff0000000000000 # 1.0
349 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
350 e
.fpregs
[3] = 0x3ff0000000000000
351 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
353 def case_fcbrts_(self
):
354 lst
= list(SVP64Asm(["fcbrts. 3,4"]))
357 fprs
[4] = 0x3ff0000000000000 # 1.0
358 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
359 e
.fpregs
[3] = 0x3ff0000000000000
361 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
363 def case_fcbrt(self
):
364 lst
= list(SVP64Asm(["fcbrt 3,4"]))
367 fprs
[4] = 0x3ff0000000000000 # 1.0
368 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
369 e
.fpregs
[3] = 0x3ff0000000000000
370 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
372 def case_fcbrt_(self
):
373 lst
= list(SVP64Asm(["fcbrt. 3,4"]))
376 fprs
[4] = 0x3ff0000000000000 # 1.0
377 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
378 e
.fpregs
[3] = 0x3ff0000000000000
380 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
382 def case_frecips(self
):
383 lst
= list(SVP64Asm(["frecips 3,4"]))
386 fprs
[4] = 0x3ff0000000000000 # 1.0
387 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
388 e
.fpregs
[3] = 0x3ff0000000000000
389 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
391 def case_frecips_(self
):
392 lst
= list(SVP64Asm(["frecips. 3,4"]))
395 fprs
[4] = 0x3ff0000000000000 # 1.0
396 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
397 e
.fpregs
[3] = 0x3ff0000000000000
399 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
401 def case_frecip(self
):
402 lst
= list(SVP64Asm(["frecip 3,4"]))
405 fprs
[4] = 0x3ff0000000000000 # 1.0
406 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
407 e
.fpregs
[3] = 0x3ff0000000000000
408 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
410 def case_frecip_(self
):
411 lst
= list(SVP64Asm(["frecip. 3,4"]))
414 fprs
[4] = 0x3ff0000000000000 # 1.0
415 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
416 e
.fpregs
[3] = 0x3ff0000000000000
418 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
420 def case_fexp2m1s(self
):
421 lst
= list(SVP64Asm(["fexp2m1s 3,4"]))
424 fprs
[4] = 0x3ff0000000000000 # 1.0
425 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
426 e
.fpregs
[3] = 0x3ff0000000000000
427 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
429 def case_fexp2m1s_(self
):
430 lst
= list(SVP64Asm(["fexp2m1s. 3,4"]))
433 fprs
[4] = 0x3ff0000000000000 # 1.0
434 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
435 e
.fpregs
[3] = 0x3ff0000000000000
437 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
439 def case_fexp2m1(self
):
440 lst
= list(SVP64Asm(["fexp2m1 3,4"]))
443 fprs
[4] = 0x3ff0000000000000 # 1.0
444 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
445 e
.fpregs
[3] = 0x3ff0000000000000
446 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
448 def case_fexp2m1_(self
):
449 lst
= list(SVP64Asm(["fexp2m1. 3,4"]))
452 fprs
[4] = 0x3ff0000000000000 # 1.0
453 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
454 e
.fpregs
[3] = 0x3ff0000000000000
456 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
458 def case_flog2p1s(self
):
459 lst
= list(SVP64Asm(["flog2p1s 3,4"]))
462 fprs
[4] = 0x3ff0000000000000 # 1.0
463 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
464 e
.fpregs
[3] = 0x3ff0000000000000
465 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
467 def case_flog2p1s_(self
):
468 lst
= list(SVP64Asm(["flog2p1s. 3,4"]))
471 fprs
[4] = 0x3ff0000000000000 # 1.0
472 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
473 e
.fpregs
[3] = 0x3ff0000000000000
475 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
477 def case_flog2p1(self
):
478 lst
= list(SVP64Asm(["flog2p1 3,4"]))
481 fprs
[4] = 0x3ff0000000000000 # 1.0
482 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
483 e
.fpregs
[3] = 0x3ff0000000000000
484 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
486 def case_flog2p1_(self
):
487 lst
= list(SVP64Asm(["flog2p1. 3,4"]))
490 fprs
[4] = 0x3ff0000000000000 # 1.0
491 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
492 e
.fpregs
[3] = 0x3ff0000000000000
494 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
496 def case_fexp2s(self
):
497 lst
= list(SVP64Asm(["fexp2s 3,4"]))
500 fprs
[4] = 0x3ff0000000000000 # 1.0
501 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
502 e
.fpregs
[3] = 0x4000000000000000
503 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
505 def case_fexp2s_(self
):
506 lst
= list(SVP64Asm(["fexp2s. 3,4"]))
509 fprs
[4] = 0x3ff0000000000000 # 1.0
510 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
511 e
.fpregs
[3] = 0x4000000000000000
513 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
515 def case_fexp2(self
):
516 lst
= list(SVP64Asm(["fexp2 3,4"]))
519 fprs
[4] = 0x3ff0000000000000 # 1.0
520 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
521 e
.fpregs
[3] = 0x4000000000000000
522 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
524 def case_fexp2_(self
):
525 lst
= list(SVP64Asm(["fexp2. 3,4"]))
528 fprs
[4] = 0x3ff0000000000000 # 1.0
529 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
530 e
.fpregs
[3] = 0x4000000000000000
532 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
534 def case_flog2s(self
):
535 lst
= list(SVP64Asm(["flog2s 3,4"]))
538 fprs
[4] = 0x3ff0000000000000 # 1.0
539 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
541 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
543 def case_flog2s_(self
):
544 lst
= list(SVP64Asm(["flog2s. 3,4"]))
547 fprs
[4] = 0x3ff0000000000000 # 1.0
548 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
551 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
553 def case_flog2(self
):
554 lst
= list(SVP64Asm(["flog2 3,4"]))
557 fprs
[4] = 0x3ff0000000000000 # 1.0
558 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
560 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
562 def case_flog2_(self
):
563 lst
= list(SVP64Asm(["flog2. 3,4"]))
566 fprs
[4] = 0x3ff0000000000000 # 1.0
567 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
570 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
572 def case_fexpm1s(self
):
573 lst
= list(SVP64Asm(["fexpm1s 3,4"]))
576 fprs
[4] = 0x3ff0000000000000 # 1.0
577 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
578 e
.fpregs
[3] = 0x3ffb7e1520000000
579 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
581 def case_fexpm1s_(self
):
582 lst
= list(SVP64Asm(["fexpm1s. 3,4"]))
585 fprs
[4] = 0x3ff0000000000000 # 1.0
586 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
587 e
.fpregs
[3] = 0x3ffb7e1520000000
589 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
591 def case_fexpm1(self
):
592 lst
= list(SVP64Asm(["fexpm1 3,4"]))
595 fprs
[4] = 0x3ff0000000000000 # 1.0
596 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
597 e
.fpregs
[3] = 0x3ffb7e151628aed2
598 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
600 def case_fexpm1_(self
):
601 lst
= list(SVP64Asm(["fexpm1. 3,4"]))
604 fprs
[4] = 0x3ff0000000000000 # 1.0
605 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
606 e
.fpregs
[3] = 0x3ffb7e151628aed2
608 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
610 def case_flogp1s(self
):
611 lst
= list(SVP64Asm(["flogp1s 3,4"]))
614 fprs
[4] = 0x3ff0000000000000 # 1.0
615 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
616 e
.fpregs
[3] = 0x3fe62e4300000000
617 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
619 def case_flogp1s_(self
):
620 lst
= list(SVP64Asm(["flogp1s. 3,4"]))
623 fprs
[4] = 0x3ff0000000000000 # 1.0
624 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
625 e
.fpregs
[3] = 0x3fe62e4300000000
627 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
629 def case_flogp1(self
):
630 lst
= list(SVP64Asm(["flogp1 3,4"]))
633 fprs
[4] = 0x3ff0000000000000 # 1.0
634 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
635 e
.fpregs
[3] = 0x3fe62e42fefa39ef
636 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
638 def case_flogp1_(self
):
639 lst
= list(SVP64Asm(["flogp1. 3,4"]))
642 fprs
[4] = 0x3ff0000000000000 # 1.0
643 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
644 e
.fpregs
[3] = 0x3fe62e42fefa39ef
646 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
648 def case_fexps(self
):
649 lst
= list(SVP64Asm(["fexps 3,4"]))
652 fprs
[4] = 0x3ff0000000000000 # 1.0
653 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
654 e
.fpregs
[3] = 0x4005bf0a80000000
655 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
657 def case_fexps_(self
):
658 lst
= list(SVP64Asm(["fexps. 3,4"]))
661 fprs
[4] = 0x3ff0000000000000 # 1.0
662 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
663 e
.fpregs
[3] = 0x4005bf0a80000000
665 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
668 lst
= list(SVP64Asm(["fexp 3,4"]))
671 fprs
[4] = 0x3ff0000000000000 # 1.0
672 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
673 e
.fpregs
[3] = 0x4005bf0a8b145769
674 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
676 def case_fexp_(self
):
677 lst
= list(SVP64Asm(["fexp. 3,4"]))
680 fprs
[4] = 0x3ff0000000000000 # 1.0
681 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
682 e
.fpregs
[3] = 0x4005bf0a8b145769
684 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
686 def case_flogs(self
):
687 lst
= list(SVP64Asm(["flogs 3,4"]))
690 fprs
[4] = 0x3ff0000000000000 # 1.0
691 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
693 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
695 def case_flogs_(self
):
696 lst
= list(SVP64Asm(["flogs. 3,4"]))
699 fprs
[4] = 0x3ff0000000000000 # 1.0
700 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
703 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
706 lst
= list(SVP64Asm(["flog 3,4"]))
709 fprs
[4] = 0x3ff0000000000000 # 1.0
710 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
712 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
714 def case_flog_(self
):
715 lst
= list(SVP64Asm(["flog. 3,4"]))
718 fprs
[4] = 0x3ff0000000000000 # 1.0
719 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
722 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
724 def case_fexp10m1s(self
):
725 lst
= list(SVP64Asm(["fexp10m1s 3,4"]))
728 fprs
[4] = 0x3ff0000000000000 # 1.0
729 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
730 e
.fpregs
[3] = 0x4022000000000000
731 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
733 def case_fexp10m1s_(self
):
734 lst
= list(SVP64Asm(["fexp10m1s. 3,4"]))
737 fprs
[4] = 0x3ff0000000000000 # 1.0
738 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
739 e
.fpregs
[3] = 0x4022000000000000
741 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
743 def case_fexp10m1(self
):
744 lst
= list(SVP64Asm(["fexp10m1 3,4"]))
747 fprs
[4] = 0x3ff0000000000000 # 1.0
748 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
749 e
.fpregs
[3] = 0x4022000000000000
750 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
752 def case_fexp10m1_(self
):
753 lst
= list(SVP64Asm(["fexp10m1. 3,4"]))
756 fprs
[4] = 0x3ff0000000000000 # 1.0
757 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
758 e
.fpregs
[3] = 0x4022000000000000
760 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
762 def case_flog10p1s(self
):
763 lst
= list(SVP64Asm(["flog10p1s 3,4"]))
766 fprs
[4] = 0x3ff0000000000000 # 1.0
767 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
768 e
.fpregs
[3] = 0x3fd3441360000000
769 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
771 def case_flog10p1s_(self
):
772 lst
= list(SVP64Asm(["flog10p1s. 3,4"]))
775 fprs
[4] = 0x3ff0000000000000 # 1.0
776 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
777 e
.fpregs
[3] = 0x3fd3441360000000
779 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
781 def case_flog10p1(self
):
782 lst
= list(SVP64Asm(["flog10p1 3,4"]))
785 fprs
[4] = 0x3ff0000000000000 # 1.0
786 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
787 e
.fpregs
[3] = 0x3fd34413509f79ff
788 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
790 def case_flog10p1_(self
):
791 lst
= list(SVP64Asm(["flog10p1. 3,4"]))
794 fprs
[4] = 0x3ff0000000000000 # 1.0
795 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
796 e
.fpregs
[3] = 0x3fd34413509f79ff
798 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
800 def case_fexp10s(self
):
801 lst
= list(SVP64Asm(["fexp10s 3,4"]))
804 fprs
[4] = 0x3ff0000000000000 # 1.0
805 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
806 e
.fpregs
[3] = 0x4024000000000000
807 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
809 def case_fexp10s_(self
):
810 lst
= list(SVP64Asm(["fexp10s. 3,4"]))
813 fprs
[4] = 0x3ff0000000000000 # 1.0
814 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
815 e
.fpregs
[3] = 0x4024000000000000
817 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
819 def case_fexp10(self
):
820 lst
= list(SVP64Asm(["fexp10 3,4"]))
823 fprs
[4] = 0x3ff0000000000000 # 1.0
824 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
825 e
.fpregs
[3] = 0x4024000000000000
826 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
828 def case_fexp10_(self
):
829 lst
= list(SVP64Asm(["fexp10. 3,4"]))
832 fprs
[4] = 0x3ff0000000000000 # 1.0
833 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
834 e
.fpregs
[3] = 0x4024000000000000
836 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
838 def case_flog10s(self
):
839 lst
= list(SVP64Asm(["flog10s 3,4"]))
842 fprs
[4] = 0x3ff0000000000000 # 1.0
843 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
845 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
847 def case_flog10s_(self
):
848 lst
= list(SVP64Asm(["flog10s. 3,4"]))
851 fprs
[4] = 0x3ff0000000000000 # 1.0
852 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
855 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
857 def case_flog10(self
):
858 lst
= list(SVP64Asm(["flog10 3,4"]))
861 fprs
[4] = 0x3ff0000000000000 # 1.0
862 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
864 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
866 def case_flog10_(self
):
867 lst
= list(SVP64Asm(["flog10. 3,4"]))
870 fprs
[4] = 0x3ff0000000000000 # 1.0
871 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
874 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
876 def case_fsins(self
):
877 lst
= list(SVP64Asm(["fsins 3,4"]))
880 fprs
[4] = 0x3ff0000000000000 # 1.0
881 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
882 e
.fpregs
[3] = 0x3feaed5480000000
883 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
885 def case_fsins_(self
):
886 lst
= list(SVP64Asm(["fsins. 3,4"]))
889 fprs
[4] = 0x3ff0000000000000 # 1.0
890 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
891 e
.fpregs
[3] = 0x3feaed5480000000
893 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
896 lst
= list(SVP64Asm(["fsin 3,4"]))
899 fprs
[4] = 0x3ff0000000000000 # 1.0
900 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
901 e
.fpregs
[3] = 0x3feaed548f090cee
902 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
904 def case_fsin_(self
):
905 lst
= list(SVP64Asm(["fsin. 3,4"]))
908 fprs
[4] = 0x3ff0000000000000 # 1.0
909 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
910 e
.fpregs
[3] = 0x3feaed548f090cee
912 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
914 def case_fcoss(self
):
915 lst
= list(SVP64Asm(["fcoss 3,4"]))
918 fprs
[4] = 0x3ff0000000000000 # 1.0
919 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
920 e
.fpregs
[3] = 0x3fe14a2800000000
921 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
923 def case_fcoss_(self
):
924 lst
= list(SVP64Asm(["fcoss. 3,4"]))
927 fprs
[4] = 0x3ff0000000000000 # 1.0
928 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
929 e
.fpregs
[3] = 0x3fe14a2800000000
931 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
934 lst
= list(SVP64Asm(["fcos 3,4"]))
937 fprs
[4] = 0x3ff0000000000000 # 1.0
938 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
939 e
.fpregs
[3] = 0x3fe14a280fb5068c
940 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
942 def case_fcos_(self
):
943 lst
= list(SVP64Asm(["fcos. 3,4"]))
946 fprs
[4] = 0x3ff0000000000000 # 1.0
947 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
948 e
.fpregs
[3] = 0x3fe14a280fb5068c
950 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
952 def case_ftans(self
):
953 lst
= list(SVP64Asm(["ftans 3,4"]))
956 fprs
[4] = 0x3ff0000000000000 # 1.0
957 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
958 e
.fpregs
[3] = 0x3ff8eb2460000000
959 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
961 def case_ftans_(self
):
962 lst
= list(SVP64Asm(["ftans. 3,4"]))
965 fprs
[4] = 0x3ff0000000000000 # 1.0
966 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
967 e
.fpregs
[3] = 0x3ff8eb2460000000
969 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
972 lst
= list(SVP64Asm(["ftan 3,4"]))
975 fprs
[4] = 0x3ff0000000000000 # 1.0
976 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
977 e
.fpregs
[3] = 0x3ff8eb245cbee3a6
978 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
980 def case_ftan_(self
):
981 lst
= list(SVP64Asm(["ftan. 3,4"]))
984 fprs
[4] = 0x3ff0000000000000 # 1.0
985 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
986 e
.fpregs
[3] = 0x3ff8eb245cbee3a6
988 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
990 def case_fasins(self
):
991 lst
= list(SVP64Asm(["fasins 3,4"]))
994 fprs
[4] = 0x3ff0000000000000 # 1.0
995 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
996 e
.fpregs
[3] = 0x3ff921fb60000000
997 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
999 def case_fasins_(self
):
1000 lst
= list(SVP64Asm(["fasins. 3,4"]))
1003 fprs
[4] = 0x3ff0000000000000 # 1.0
1004 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1005 e
.fpregs
[3] = 0x3ff921fb60000000
1007 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1009 def case_fasin(self
):
1010 lst
= list(SVP64Asm(["fasin 3,4"]))
1013 fprs
[4] = 0x3ff0000000000000 # 1.0
1014 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1015 e
.fpregs
[3] = 0x3ff921fb54442d18
1016 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1018 def case_fasin_(self
):
1019 lst
= list(SVP64Asm(["fasin. 3,4"]))
1022 fprs
[4] = 0x3ff0000000000000 # 1.0
1023 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1024 e
.fpregs
[3] = 0x3ff921fb54442d18
1026 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1028 def case_facoss(self
):
1029 lst
= list(SVP64Asm(["facoss 3,4"]))
1032 fprs
[4] = 0x3ff0000000000000 # 1.0
1033 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1035 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1037 def case_facoss_(self
):
1038 lst
= list(SVP64Asm(["facoss. 3,4"]))
1041 fprs
[4] = 0x3ff0000000000000 # 1.0
1042 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1045 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1047 def case_facos(self
):
1048 lst
= list(SVP64Asm(["facos 3,4"]))
1051 fprs
[4] = 0x3ff0000000000000 # 1.0
1052 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1054 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1056 def case_facos_(self
):
1057 lst
= list(SVP64Asm(["facos. 3,4"]))
1060 fprs
[4] = 0x3ff0000000000000 # 1.0
1061 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1064 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1066 def case_fatans(self
):
1067 lst
= list(SVP64Asm(["fatans 3,4"]))
1070 fprs
[4] = 0x3ff0000000000000 # 1.0
1071 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1072 e
.fpregs
[3] = 0x3fe921fb60000000
1073 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1075 def case_fatans_(self
):
1076 lst
= list(SVP64Asm(["fatans. 3,4"]))
1079 fprs
[4] = 0x3ff0000000000000 # 1.0
1080 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1081 e
.fpregs
[3] = 0x3fe921fb60000000
1083 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1085 def case_fatan(self
):
1086 lst
= list(SVP64Asm(["fatan 3,4"]))
1089 fprs
[4] = 0x3ff0000000000000 # 1.0
1090 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1091 e
.fpregs
[3] = 0x3fe921fb54442d18
1092 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1094 def case_fatan_(self
):
1095 lst
= list(SVP64Asm(["fatan. 3,4"]))
1098 fprs
[4] = 0x3ff0000000000000 # 1.0
1099 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1100 e
.fpregs
[3] = 0x3fe921fb54442d18
1102 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1104 def case_fsinpis(self
):
1105 lst
= list(SVP64Asm(["fsinpis 3,4"]))
1108 fprs
[4] = 0x3fe0000000000000 # 0.5
1109 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1110 e
.fpregs
[3] = 0x3ff0000000000000
1111 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1113 def case_fsinpis_(self
):
1114 lst
= list(SVP64Asm(["fsinpis. 3,4"]))
1117 fprs
[4] = 0x3fe0000000000000 # 0.5
1118 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1119 e
.fpregs
[3] = 0x3ff0000000000000
1121 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1123 def case_fsinpi(self
):
1124 lst
= list(SVP64Asm(["fsinpi 3,4"]))
1127 fprs
[4] = 0x3fe0000000000000 # 0.5
1128 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1129 e
.fpregs
[3] = 0x3ff0000000000000
1130 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1132 def case_fsinpi_(self
):
1133 lst
= list(SVP64Asm(["fsinpi. 3,4"]))
1136 fprs
[4] = 0x3fe0000000000000 # 0.5
1137 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1138 e
.fpregs
[3] = 0x3ff0000000000000
1140 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1142 def case_fcospis(self
):
1143 lst
= list(SVP64Asm(["fcospis 3,4"]))
1146 fprs
[4] = 0x3ff0000000000000 # 1.0
1147 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1148 e
.fpregs
[3] = 0xbff0000000000000
1149 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1151 def case_fcospis_(self
):
1152 lst
= list(SVP64Asm(["fcospis. 3,4"]))
1155 fprs
[4] = 0x3ff0000000000000 # 1.0
1156 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1157 e
.fpregs
[3] = 0xbff0000000000000
1159 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1161 def case_fcospi(self
):
1162 lst
= list(SVP64Asm(["fcospi 3,4"]))
1165 fprs
[4] = 0x3ff0000000000000 # 1.0
1166 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1167 e
.fpregs
[3] = 0xbff0000000000000
1168 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1170 def case_fcospi_(self
):
1171 lst
= list(SVP64Asm(["fcospi. 3,4"]))
1174 fprs
[4] = 0x3ff0000000000000 # 1.0
1175 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1176 e
.fpregs
[3] = 0xbff0000000000000
1178 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1180 def case_ftanpis(self
):
1181 lst
= list(SVP64Asm(["ftanpis 3,4"]))
1184 fprs
[4] = 0x3fc0000000000000 # 0.125
1185 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1186 e
.fpregs
[3] = 0x3fda8279a0000000
1187 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1189 def case_ftanpis_(self
):
1190 lst
= list(SVP64Asm(["ftanpis. 3,4"]))
1193 fprs
[4] = 0x3fc0000000000000 # 0.125
1194 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1195 e
.fpregs
[3] = 0x3fda8279a0000000
1197 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1199 def case_ftanpi(self
):
1200 lst
= list(SVP64Asm(["ftanpi 3,4"]))
1203 fprs
[4] = 0x3fc0000000000000 # 0.125
1204 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1205 e
.fpregs
[3] = 0x3fda827999fcef32
1206 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1208 def case_ftanpi_(self
):
1209 lst
= list(SVP64Asm(["ftanpi. 3,4"]))
1212 fprs
[4] = 0x3fc0000000000000 # 0.125
1213 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1214 e
.fpregs
[3] = 0x3fda827999fcef32
1216 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1218 def case_fasinpis(self
):
1219 lst
= list(SVP64Asm(["fasinpis 3,4"]))
1222 fprs
[4] = 0x3ff0000000000000 # 1.0
1223 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1224 e
.fpregs
[3] = 0x3fe0000000000000
1225 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1227 def case_fasinpis_(self
):
1228 lst
= list(SVP64Asm(["fasinpis. 3,4"]))
1231 fprs
[4] = 0x3ff0000000000000 # 1.0
1232 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1233 e
.fpregs
[3] = 0x3fe0000000000000
1235 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1237 def case_fasinpi(self
):
1238 lst
= list(SVP64Asm(["fasinpi 3,4"]))
1241 fprs
[4] = 0x3ff0000000000000 # 1.0
1242 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1243 e
.fpregs
[3] = 0x3fe0000000000000
1244 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1246 def case_fasinpi_(self
):
1247 lst
= list(SVP64Asm(["fasinpi. 3,4"]))
1250 fprs
[4] = 0x3ff0000000000000 # 1.0
1251 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1252 e
.fpregs
[3] = 0x3fe0000000000000
1254 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1256 def case_facospis(self
):
1257 lst
= list(SVP64Asm(["facospis 3,4"]))
1260 fprs
[4] = 0x3ff0000000000000 # 1.0
1261 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1263 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1265 def case_facospis_(self
):
1266 lst
= list(SVP64Asm(["facospis. 3,4"]))
1269 fprs
[4] = 0x3ff0000000000000 # 1.0
1270 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1273 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1275 def case_facospi(self
):
1276 lst
= list(SVP64Asm(["facospi 3,4"]))
1279 fprs
[4] = 0x3ff0000000000000 # 1.0
1280 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1282 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1284 def case_facospi_(self
):
1285 lst
= list(SVP64Asm(["facospi. 3,4"]))
1288 fprs
[4] = 0x3ff0000000000000 # 1.0
1289 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1292 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1294 def case_fatanpis(self
):
1295 lst
= list(SVP64Asm(["fatanpis 3,4"]))
1298 fprs
[4] = 0x3ff0000000000000 # 1.0
1299 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1300 e
.fpregs
[3] = 0x3fd0000000000000
1301 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1303 def case_fatanpis_(self
):
1304 lst
= list(SVP64Asm(["fatanpis. 3,4"]))
1307 fprs
[4] = 0x3ff0000000000000 # 1.0
1308 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1309 e
.fpregs
[3] = 0x3fd0000000000000
1311 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1313 def case_fatanpi(self
):
1314 lst
= list(SVP64Asm(["fatanpi 3,4"]))
1317 fprs
[4] = 0x3ff0000000000000 # 1.0
1318 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1319 e
.fpregs
[3] = 0x3fd0000000000000
1320 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1322 def case_fatanpi_(self
):
1323 lst
= list(SVP64Asm(["fatanpi. 3,4"]))
1326 fprs
[4] = 0x3ff0000000000000 # 1.0
1327 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1328 e
.fpregs
[3] = 0x3fd0000000000000
1330 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1332 def case_fsinhs(self
):
1333 lst
= list(SVP64Asm(["fsinhs 3,4"]))
1336 fprs
[4] = 0x3ff0000000000000 # 1.0
1337 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1338 e
.fpregs
[3] = 0x3ff2cd9fc0000000
1339 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1341 def case_fsinhs_(self
):
1342 lst
= list(SVP64Asm(["fsinhs. 3,4"]))
1345 fprs
[4] = 0x3ff0000000000000 # 1.0
1346 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1347 e
.fpregs
[3] = 0x3ff2cd9fc0000000
1349 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1351 def case_fsinh(self
):
1352 lst
= list(SVP64Asm(["fsinh 3,4"]))
1355 fprs
[4] = 0x3ff0000000000000 # 1.0
1356 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1357 e
.fpregs
[3] = 0x3ff2cd9fc44eb982
1358 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1360 def case_fsinh_(self
):
1361 lst
= list(SVP64Asm(["fsinh. 3,4"]))
1364 fprs
[4] = 0x3ff0000000000000 # 1.0
1365 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1366 e
.fpregs
[3] = 0x3ff2cd9fc44eb982
1368 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1370 def case_fcoshs(self
):
1371 lst
= list(SVP64Asm(["fcoshs 3,4"]))
1374 fprs
[4] = 0x3ff0000000000000 # 1.0
1375 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1376 e
.fpregs
[3] = 0x3ff8b07560000000
1377 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1379 def case_fcoshs_(self
):
1380 lst
= list(SVP64Asm(["fcoshs. 3,4"]))
1383 fprs
[4] = 0x3ff0000000000000 # 1.0
1384 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1385 e
.fpregs
[3] = 0x3ff8b07560000000
1387 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1389 def case_fcosh(self
):
1390 lst
= list(SVP64Asm(["fcosh 3,4"]))
1393 fprs
[4] = 0x3ff0000000000000 # 1.0
1394 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1395 e
.fpregs
[3] = 0x3ff8b07551d9f550
1396 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1398 def case_fcosh_(self
):
1399 lst
= list(SVP64Asm(["fcosh. 3,4"]))
1402 fprs
[4] = 0x3ff0000000000000 # 1.0
1403 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1404 e
.fpregs
[3] = 0x3ff8b07551d9f550
1406 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1408 def case_ftanhs(self
):
1409 lst
= list(SVP64Asm(["ftanhs 3,4"]))
1412 fprs
[4] = 0x3ff0000000000000 # 1.0
1413 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1414 e
.fpregs
[3] = 0x3fe85efac0000000
1415 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1417 def case_ftanhs_(self
):
1418 lst
= list(SVP64Asm(["ftanhs. 3,4"]))
1421 fprs
[4] = 0x3ff0000000000000 # 1.0
1422 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1423 e
.fpregs
[3] = 0x3fe85efac0000000
1425 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1427 def case_ftanh(self
):
1428 lst
= list(SVP64Asm(["ftanh 3,4"]))
1431 fprs
[4] = 0x3ff0000000000000 # 1.0
1432 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1433 e
.fpregs
[3] = 0x3fe85efab514f394
1434 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1436 def case_ftanh_(self
):
1437 lst
= list(SVP64Asm(["ftanh. 3,4"]))
1440 fprs
[4] = 0x3ff0000000000000 # 1.0
1441 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1442 e
.fpregs
[3] = 0x3fe85efab514f394
1444 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1446 def case_fasinhs(self
):
1447 lst
= list(SVP64Asm(["fasinhs 3,4"]))
1450 fprs
[4] = 0x3ff0000000000000 # 1.0
1451 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1452 e
.fpregs
[3] = 0x3fec343660000000
1453 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1455 def case_fasinhs_(self
):
1456 lst
= list(SVP64Asm(["fasinhs. 3,4"]))
1459 fprs
[4] = 0x3ff0000000000000 # 1.0
1460 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1461 e
.fpregs
[3] = 0x3fec343660000000
1463 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1465 def case_fasinh(self
):
1466 lst
= list(SVP64Asm(["fasinh 3,4"]))
1469 fprs
[4] = 0x3ff0000000000000 # 1.0
1470 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1471 e
.fpregs
[3] = 0x3fec34366179d427
1472 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1474 def case_fasinh_(self
):
1475 lst
= list(SVP64Asm(["fasinh. 3,4"]))
1478 fprs
[4] = 0x3ff0000000000000 # 1.0
1479 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1480 e
.fpregs
[3] = 0x3fec34366179d427
1482 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1484 def case_facoshs(self
):
1485 lst
= list(SVP64Asm(["facoshs 3,4"]))
1488 fprs
[4] = 0x3ff0000000000000 # 1.0
1489 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1491 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1493 def case_facoshs_(self
):
1494 lst
= list(SVP64Asm(["facoshs. 3,4"]))
1497 fprs
[4] = 0x3ff0000000000000 # 1.0
1498 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1501 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1503 def case_facosh(self
):
1504 lst
= list(SVP64Asm(["facosh 3,4"]))
1507 fprs
[4] = 0x3ff0000000000000 # 1.0
1508 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1510 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1512 def case_facosh_(self
):
1513 lst
= list(SVP64Asm(["facosh. 3,4"]))
1516 fprs
[4] = 0x3ff0000000000000 # 1.0
1517 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1520 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1522 def case_fatanhs(self
):
1523 lst
= list(SVP64Asm(["fatanhs 3,4"]))
1526 fprs
[4] = 0x3fe0000000000000 # 0.5
1527 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1528 e
.fpregs
[3] = 0x3fe193ea80000000
1529 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1531 def case_fatanhs_(self
):
1532 lst
= list(SVP64Asm(["fatanhs. 3,4"]))
1535 fprs
[4] = 0x3fe0000000000000 # 0.5
1536 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1537 e
.fpregs
[3] = 0x3fe193ea80000000
1539 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1541 def case_fatanh(self
):
1542 lst
= list(SVP64Asm(["fatanh 3,4"]))
1545 fprs
[4] = 0x3fe0000000000000 # 0.5
1546 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1547 e
.fpregs
[3] = 0x3fe193ea7aad030a
1548 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1550 def case_fatanh_(self
):
1551 lst
= list(SVP64Asm(["fatanh. 3,4"]))
1554 fprs
[4] = 0x3fe0000000000000 # 0.5
1555 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1556 e
.fpregs
[3] = 0x3fe193ea7aad030a
1558 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1560 def case_fminnum08s(self
):
1561 lst
= list(SVP64Asm(["fminnum08s 3,4,5"]))
1564 fprs
[4] = 0x3ff0000000000000 # 1.0
1565 fprs
[5] = 0x3ff0000000000000 # 1.0
1566 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1567 e
.fpregs
[3] = 0x3ff0000000000000
1568 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1570 def case_fminnum08s_(self
):
1571 lst
= list(SVP64Asm(["fminnum08s. 3,4,5"]))
1574 fprs
[4] = 0x3ff0000000000000 # 1.0
1575 fprs
[5] = 0x3ff0000000000000 # 1.0
1576 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1577 e
.fpregs
[3] = 0x3ff0000000000000
1579 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1581 def case_fminnum08(self
):
1582 lst
= list(SVP64Asm(["fminnum08 3,4,5"]))
1585 fprs
[4] = 0x3ff0000000000000 # 1.0
1586 fprs
[5] = 0x3ff0000000000000 # 1.0
1587 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1588 e
.fpregs
[3] = 0x3ff0000000000000
1589 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1591 def case_fminnum08_(self
):
1592 lst
= list(SVP64Asm(["fminnum08. 3,4,5"]))
1595 fprs
[4] = 0x3ff0000000000000 # 1.0
1596 fprs
[5] = 0x3ff0000000000000 # 1.0
1597 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1598 e
.fpregs
[3] = 0x3ff0000000000000
1600 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1602 def case_fmaxnum08s(self
):
1603 lst
= list(SVP64Asm(["fmaxnum08s 3,4,5"]))
1606 fprs
[4] = 0x3ff0000000000000 # 1.0
1607 fprs
[5] = 0x3ff0000000000000 # 1.0
1608 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1609 e
.fpregs
[3] = 0x3ff0000000000000
1610 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1612 def case_fmaxnum08s_(self
):
1613 lst
= list(SVP64Asm(["fmaxnum08s. 3,4,5"]))
1616 fprs
[4] = 0x3ff0000000000000 # 1.0
1617 fprs
[5] = 0x3ff0000000000000 # 1.0
1618 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1619 e
.fpregs
[3] = 0x3ff0000000000000
1621 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1623 def case_fmaxnum08(self
):
1624 lst
= list(SVP64Asm(["fmaxnum08 3,4,5"]))
1627 fprs
[4] = 0x3ff0000000000000 # 1.0
1628 fprs
[5] = 0x3ff0000000000000 # 1.0
1629 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1630 e
.fpregs
[3] = 0x3ff0000000000000
1631 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1633 def case_fmaxnum08_(self
):
1634 lst
= list(SVP64Asm(["fmaxnum08. 3,4,5"]))
1637 fprs
[4] = 0x3ff0000000000000 # 1.0
1638 fprs
[5] = 0x3ff0000000000000 # 1.0
1639 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1640 e
.fpregs
[3] = 0x3ff0000000000000
1642 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1644 def case_fmin19s(self
):
1645 lst
= list(SVP64Asm(["fmin19s 3,4,5"]))
1648 fprs
[4] = 0x3ff0000000000000 # 1.0
1649 fprs
[5] = 0x3ff0000000000000 # 1.0
1650 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1651 e
.fpregs
[3] = 0x3ff0000000000000
1652 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1654 def case_fmin19s_(self
):
1655 lst
= list(SVP64Asm(["fmin19s. 3,4,5"]))
1658 fprs
[4] = 0x3ff0000000000000 # 1.0
1659 fprs
[5] = 0x3ff0000000000000 # 1.0
1660 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1661 e
.fpregs
[3] = 0x3ff0000000000000
1663 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1665 def case_fmin19(self
):
1666 lst
= list(SVP64Asm(["fmin19 3,4,5"]))
1669 fprs
[4] = 0x3ff0000000000000 # 1.0
1670 fprs
[5] = 0x3ff0000000000000 # 1.0
1671 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1672 e
.fpregs
[3] = 0x3ff0000000000000
1673 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1675 def case_fmin19_(self
):
1676 lst
= list(SVP64Asm(["fmin19. 3,4,5"]))
1679 fprs
[4] = 0x3ff0000000000000 # 1.0
1680 fprs
[5] = 0x3ff0000000000000 # 1.0
1681 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1682 e
.fpregs
[3] = 0x3ff0000000000000
1684 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1686 def case_fmax19s(self
):
1687 lst
= list(SVP64Asm(["fmax19s 3,4,5"]))
1690 fprs
[4] = 0x3ff0000000000000 # 1.0
1691 fprs
[5] = 0x3ff0000000000000 # 1.0
1692 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1693 e
.fpregs
[3] = 0x3ff0000000000000
1694 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1696 def case_fmax19s_(self
):
1697 lst
= list(SVP64Asm(["fmax19s. 3,4,5"]))
1700 fprs
[4] = 0x3ff0000000000000 # 1.0
1701 fprs
[5] = 0x3ff0000000000000 # 1.0
1702 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1703 e
.fpregs
[3] = 0x3ff0000000000000
1705 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1707 def case_fmax19(self
):
1708 lst
= list(SVP64Asm(["fmax19 3,4,5"]))
1711 fprs
[4] = 0x3ff0000000000000 # 1.0
1712 fprs
[5] = 0x3ff0000000000000 # 1.0
1713 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1714 e
.fpregs
[3] = 0x3ff0000000000000
1715 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1717 def case_fmax19_(self
):
1718 lst
= list(SVP64Asm(["fmax19. 3,4,5"]))
1721 fprs
[4] = 0x3ff0000000000000 # 1.0
1722 fprs
[5] = 0x3ff0000000000000 # 1.0
1723 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1724 e
.fpregs
[3] = 0x3ff0000000000000
1726 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1728 def case_fminnum19s(self
):
1729 lst
= list(SVP64Asm(["fminnum19s 3,4,5"]))
1732 fprs
[4] = 0x3ff0000000000000 # 1.0
1733 fprs
[5] = 0x3ff0000000000000 # 1.0
1734 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1735 e
.fpregs
[3] = 0x3ff0000000000000
1736 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1738 def case_fminnum19s_(self
):
1739 lst
= list(SVP64Asm(["fminnum19s. 3,4,5"]))
1742 fprs
[4] = 0x3ff0000000000000 # 1.0
1743 fprs
[5] = 0x3ff0000000000000 # 1.0
1744 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1745 e
.fpregs
[3] = 0x3ff0000000000000
1747 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1749 def case_fminnum19(self
):
1750 lst
= list(SVP64Asm(["fminnum19 3,4,5"]))
1753 fprs
[4] = 0x3ff0000000000000 # 1.0
1754 fprs
[5] = 0x3ff0000000000000 # 1.0
1755 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1756 e
.fpregs
[3] = 0x3ff0000000000000
1757 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1759 def case_fminnum19_(self
):
1760 lst
= list(SVP64Asm(["fminnum19. 3,4,5"]))
1763 fprs
[4] = 0x3ff0000000000000 # 1.0
1764 fprs
[5] = 0x3ff0000000000000 # 1.0
1765 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1766 e
.fpregs
[3] = 0x3ff0000000000000
1768 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1770 def case_fmaxnum19s(self
):
1771 lst
= list(SVP64Asm(["fmaxnum19s 3,4,5"]))
1774 fprs
[4] = 0x3ff0000000000000 # 1.0
1775 fprs
[5] = 0x3ff0000000000000 # 1.0
1776 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1777 e
.fpregs
[3] = 0x3ff0000000000000
1778 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1780 def case_fmaxnum19s_(self
):
1781 lst
= list(SVP64Asm(["fmaxnum19s. 3,4,5"]))
1784 fprs
[4] = 0x3ff0000000000000 # 1.0
1785 fprs
[5] = 0x3ff0000000000000 # 1.0
1786 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1787 e
.fpregs
[3] = 0x3ff0000000000000
1789 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1791 def case_fmaxnum19(self
):
1792 lst
= list(SVP64Asm(["fmaxnum19 3,4,5"]))
1795 fprs
[4] = 0x3ff0000000000000 # 1.0
1796 fprs
[5] = 0x3ff0000000000000 # 1.0
1797 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1798 e
.fpregs
[3] = 0x3ff0000000000000
1799 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1801 def case_fmaxnum19_(self
):
1802 lst
= list(SVP64Asm(["fmaxnum19. 3,4,5"]))
1805 fprs
[4] = 0x3ff0000000000000 # 1.0
1806 fprs
[5] = 0x3ff0000000000000 # 1.0
1807 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1808 e
.fpregs
[3] = 0x3ff0000000000000
1810 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1812 def case_fmincs(self
):
1813 lst
= list(SVP64Asm(["fmincs 3,4,5"]))
1816 fprs
[4] = 0x3ff0000000000000 # 1.0
1817 fprs
[5] = 0x3ff0000000000000 # 1.0
1818 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1819 e
.fpregs
[3] = 0x3ff0000000000000
1820 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1822 def case_fmincs_(self
):
1823 lst
= list(SVP64Asm(["fmincs. 3,4,5"]))
1826 fprs
[4] = 0x3ff0000000000000 # 1.0
1827 fprs
[5] = 0x3ff0000000000000 # 1.0
1828 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1829 e
.fpregs
[3] = 0x3ff0000000000000
1831 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1833 def case_fminc(self
):
1834 lst
= list(SVP64Asm(["fminc 3,4,5"]))
1837 fprs
[4] = 0x3ff0000000000000 # 1.0
1838 fprs
[5] = 0x3ff0000000000000 # 1.0
1839 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1840 e
.fpregs
[3] = 0x3ff0000000000000
1841 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1843 def case_fminc_(self
):
1844 lst
= list(SVP64Asm(["fminc. 3,4,5"]))
1847 fprs
[4] = 0x3ff0000000000000 # 1.0
1848 fprs
[5] = 0x3ff0000000000000 # 1.0
1849 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1850 e
.fpregs
[3] = 0x3ff0000000000000
1852 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1854 def case_fmaxcs(self
):
1855 lst
= list(SVP64Asm(["fmaxcs 3,4,5"]))
1858 fprs
[4] = 0x3ff0000000000000 # 1.0
1859 fprs
[5] = 0x3ff0000000000000 # 1.0
1860 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1861 e
.fpregs
[3] = 0x3ff0000000000000
1862 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1864 def case_fmaxcs_(self
):
1865 lst
= list(SVP64Asm(["fmaxcs. 3,4,5"]))
1868 fprs
[4] = 0x3ff0000000000000 # 1.0
1869 fprs
[5] = 0x3ff0000000000000 # 1.0
1870 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1871 e
.fpregs
[3] = 0x3ff0000000000000
1873 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1875 def case_fmaxc(self
):
1876 lst
= list(SVP64Asm(["fmaxc 3,4,5"]))
1879 fprs
[4] = 0x3ff0000000000000 # 1.0
1880 fprs
[5] = 0x3ff0000000000000 # 1.0
1881 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1882 e
.fpregs
[3] = 0x3ff0000000000000
1883 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1885 def case_fmaxc_(self
):
1886 lst
= list(SVP64Asm(["fmaxc. 3,4,5"]))
1889 fprs
[4] = 0x3ff0000000000000 # 1.0
1890 fprs
[5] = 0x3ff0000000000000 # 1.0
1891 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1892 e
.fpregs
[3] = 0x3ff0000000000000
1894 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1896 def case_fminmagnum08s(self
):
1897 lst
= list(SVP64Asm(["fminmagnum08s 3,4,5"]))
1900 fprs
[4] = 0x3ff0000000000000 # 1.0
1901 fprs
[5] = 0x3ff0000000000000 # 1.0
1902 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1903 e
.fpregs
[3] = 0x3ff0000000000000
1904 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1906 def case_fminmagnum08s_(self
):
1907 lst
= list(SVP64Asm(["fminmagnum08s. 3,4,5"]))
1910 fprs
[4] = 0x3ff0000000000000 # 1.0
1911 fprs
[5] = 0x3ff0000000000000 # 1.0
1912 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1913 e
.fpregs
[3] = 0x3ff0000000000000
1915 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1917 def case_fminmagnum08(self
):
1918 lst
= list(SVP64Asm(["fminmagnum08 3,4,5"]))
1921 fprs
[4] = 0x3ff0000000000000 # 1.0
1922 fprs
[5] = 0x3ff0000000000000 # 1.0
1923 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1924 e
.fpregs
[3] = 0x3ff0000000000000
1925 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1927 def case_fminmagnum08_(self
):
1928 lst
= list(SVP64Asm(["fminmagnum08. 3,4,5"]))
1931 fprs
[4] = 0x3ff0000000000000 # 1.0
1932 fprs
[5] = 0x3ff0000000000000 # 1.0
1933 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1934 e
.fpregs
[3] = 0x3ff0000000000000
1936 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1938 def case_fmaxmagnum08s(self
):
1939 lst
= list(SVP64Asm(["fmaxmagnum08s 3,4,5"]))
1942 fprs
[4] = 0x3ff0000000000000 # 1.0
1943 fprs
[5] = 0x3ff0000000000000 # 1.0
1944 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1945 e
.fpregs
[3] = 0x3ff0000000000000
1946 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1948 def case_fmaxmagnum08s_(self
):
1949 lst
= list(SVP64Asm(["fmaxmagnum08s. 3,4,5"]))
1952 fprs
[4] = 0x3ff0000000000000 # 1.0
1953 fprs
[5] = 0x3ff0000000000000 # 1.0
1954 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1955 e
.fpregs
[3] = 0x3ff0000000000000
1957 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1959 def case_fmaxmagnum08(self
):
1960 lst
= list(SVP64Asm(["fmaxmagnum08 3,4,5"]))
1963 fprs
[4] = 0x3ff0000000000000 # 1.0
1964 fprs
[5] = 0x3ff0000000000000 # 1.0
1965 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1966 e
.fpregs
[3] = 0x3ff0000000000000
1967 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1969 def case_fmaxmagnum08_(self
):
1970 lst
= list(SVP64Asm(["fmaxmagnum08. 3,4,5"]))
1973 fprs
[4] = 0x3ff0000000000000 # 1.0
1974 fprs
[5] = 0x3ff0000000000000 # 1.0
1975 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1976 e
.fpregs
[3] = 0x3ff0000000000000
1978 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1980 def case_fminmag19s(self
):
1981 lst
= list(SVP64Asm(["fminmag19s 3,4,5"]))
1984 fprs
[4] = 0x3ff0000000000000 # 1.0
1985 fprs
[5] = 0x3ff0000000000000 # 1.0
1986 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1987 e
.fpregs
[3] = 0x3ff0000000000000
1988 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
1990 def case_fminmag19s_(self
):
1991 lst
= list(SVP64Asm(["fminmag19s. 3,4,5"]))
1994 fprs
[4] = 0x3ff0000000000000 # 1.0
1995 fprs
[5] = 0x3ff0000000000000 # 1.0
1996 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
1997 e
.fpregs
[3] = 0x3ff0000000000000
1999 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2001 def case_fminmag19(self
):
2002 lst
= list(SVP64Asm(["fminmag19 3,4,5"]))
2005 fprs
[4] = 0x3ff0000000000000 # 1.0
2006 fprs
[5] = 0x3ff0000000000000 # 1.0
2007 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2008 e
.fpregs
[3] = 0x3ff0000000000000
2009 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2011 def case_fminmag19_(self
):
2012 lst
= list(SVP64Asm(["fminmag19. 3,4,5"]))
2015 fprs
[4] = 0x3ff0000000000000 # 1.0
2016 fprs
[5] = 0x3ff0000000000000 # 1.0
2017 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2018 e
.fpregs
[3] = 0x3ff0000000000000
2020 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2022 def case_fmaxmag19s(self
):
2023 lst
= list(SVP64Asm(["fmaxmag19s 3,4,5"]))
2026 fprs
[4] = 0x3ff0000000000000 # 1.0
2027 fprs
[5] = 0x3ff0000000000000 # 1.0
2028 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2029 e
.fpregs
[3] = 0x3ff0000000000000
2030 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2032 def case_fmaxmag19s_(self
):
2033 lst
= list(SVP64Asm(["fmaxmag19s. 3,4,5"]))
2036 fprs
[4] = 0x3ff0000000000000 # 1.0
2037 fprs
[5] = 0x3ff0000000000000 # 1.0
2038 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2039 e
.fpregs
[3] = 0x3ff0000000000000
2041 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2043 def case_fmaxmag19(self
):
2044 lst
= list(SVP64Asm(["fmaxmag19 3,4,5"]))
2047 fprs
[4] = 0x3ff0000000000000 # 1.0
2048 fprs
[5] = 0x3ff0000000000000 # 1.0
2049 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2050 e
.fpregs
[3] = 0x3ff0000000000000
2051 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2053 def case_fmaxmag19_(self
):
2054 lst
= list(SVP64Asm(["fmaxmag19. 3,4,5"]))
2057 fprs
[4] = 0x3ff0000000000000 # 1.0
2058 fprs
[5] = 0x3ff0000000000000 # 1.0
2059 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2060 e
.fpregs
[3] = 0x3ff0000000000000
2062 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2064 def case_fminmagnum19s(self
):
2065 lst
= list(SVP64Asm(["fminmagnum19s 3,4,5"]))
2068 fprs
[4] = 0x3ff0000000000000 # 1.0
2069 fprs
[5] = 0x3ff0000000000000 # 1.0
2070 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2071 e
.fpregs
[3] = 0x3ff0000000000000
2072 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2074 def case_fminmagnum19s_(self
):
2075 lst
= list(SVP64Asm(["fminmagnum19s. 3,4,5"]))
2078 fprs
[4] = 0x3ff0000000000000 # 1.0
2079 fprs
[5] = 0x3ff0000000000000 # 1.0
2080 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2081 e
.fpregs
[3] = 0x3ff0000000000000
2083 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2085 def case_fminmagnum19(self
):
2086 lst
= list(SVP64Asm(["fminmagnum19 3,4,5"]))
2089 fprs
[4] = 0x3ff0000000000000 # 1.0
2090 fprs
[5] = 0x3ff0000000000000 # 1.0
2091 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2092 e
.fpregs
[3] = 0x3ff0000000000000
2093 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2095 def case_fminmagnum19_(self
):
2096 lst
= list(SVP64Asm(["fminmagnum19. 3,4,5"]))
2099 fprs
[4] = 0x3ff0000000000000 # 1.0
2100 fprs
[5] = 0x3ff0000000000000 # 1.0
2101 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2102 e
.fpregs
[3] = 0x3ff0000000000000
2104 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2106 def case_fmaxmagnum19s(self
):
2107 lst
= list(SVP64Asm(["fmaxmagnum19s 3,4,5"]))
2110 fprs
[4] = 0x3ff0000000000000 # 1.0
2111 fprs
[5] = 0x3ff0000000000000 # 1.0
2112 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2113 e
.fpregs
[3] = 0x3ff0000000000000
2114 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2116 def case_fmaxmagnum19s_(self
):
2117 lst
= list(SVP64Asm(["fmaxmagnum19s. 3,4,5"]))
2120 fprs
[4] = 0x3ff0000000000000 # 1.0
2121 fprs
[5] = 0x3ff0000000000000 # 1.0
2122 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2123 e
.fpregs
[3] = 0x3ff0000000000000
2125 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2127 def case_fmaxmagnum19(self
):
2128 lst
= list(SVP64Asm(["fmaxmagnum19 3,4,5"]))
2131 fprs
[4] = 0x3ff0000000000000 # 1.0
2132 fprs
[5] = 0x3ff0000000000000 # 1.0
2133 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2134 e
.fpregs
[3] = 0x3ff0000000000000
2135 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2137 def case_fmaxmagnum19_(self
):
2138 lst
= list(SVP64Asm(["fmaxmagnum19. 3,4,5"]))
2141 fprs
[4] = 0x3ff0000000000000 # 1.0
2142 fprs
[5] = 0x3ff0000000000000 # 1.0
2143 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2144 e
.fpregs
[3] = 0x3ff0000000000000
2146 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2148 def case_fminmagcs(self
):
2149 lst
= list(SVP64Asm(["fminmagcs 3,4,5"]))
2152 fprs
[4] = 0x3ff0000000000000 # 1.0
2153 fprs
[5] = 0x3ff0000000000000 # 1.0
2154 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2155 e
.fpregs
[3] = 0x3ff0000000000000
2156 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2158 def case_fminmagcs_(self
):
2159 lst
= list(SVP64Asm(["fminmagcs. 3,4,5"]))
2162 fprs
[4] = 0x3ff0000000000000 # 1.0
2163 fprs
[5] = 0x3ff0000000000000 # 1.0
2164 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2165 e
.fpregs
[3] = 0x3ff0000000000000
2167 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2169 def case_fminmagc(self
):
2170 lst
= list(SVP64Asm(["fminmagc 3,4,5"]))
2173 fprs
[4] = 0x3ff0000000000000 # 1.0
2174 fprs
[5] = 0x3ff0000000000000 # 1.0
2175 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2176 e
.fpregs
[3] = 0x3ff0000000000000
2177 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2179 def case_fminmagc_(self
):
2180 lst
= list(SVP64Asm(["fminmagc. 3,4,5"]))
2183 fprs
[4] = 0x3ff0000000000000 # 1.0
2184 fprs
[5] = 0x3ff0000000000000 # 1.0
2185 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2186 e
.fpregs
[3] = 0x3ff0000000000000
2188 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2190 def case_fmaxmagcs(self
):
2191 lst
= list(SVP64Asm(["fmaxmagcs 3,4,5"]))
2194 fprs
[4] = 0x3ff0000000000000 # 1.0
2195 fprs
[5] = 0x3ff0000000000000 # 1.0
2196 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2197 e
.fpregs
[3] = 0x3ff0000000000000
2198 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2200 def case_fmaxmagcs_(self
):
2201 lst
= list(SVP64Asm(["fmaxmagcs. 3,4,5"]))
2204 fprs
[4] = 0x3ff0000000000000 # 1.0
2205 fprs
[5] = 0x3ff0000000000000 # 1.0
2206 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2207 e
.fpregs
[3] = 0x3ff0000000000000
2209 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2211 def case_fmaxmagc(self
):
2212 lst
= list(SVP64Asm(["fmaxmagc 3,4,5"]))
2215 fprs
[4] = 0x3ff0000000000000 # 1.0
2216 fprs
[5] = 0x3ff0000000000000 # 1.0
2217 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2218 e
.fpregs
[3] = 0x3ff0000000000000
2219 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2221 def case_fmaxmagc_(self
):
2222 lst
= list(SVP64Asm(["fmaxmagc. 3,4,5"]))
2225 fprs
[4] = 0x3ff0000000000000 # 1.0
2226 fprs
[5] = 0x3ff0000000000000 # 1.0
2227 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2228 e
.fpregs
[3] = 0x3ff0000000000000
2230 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2232 def case_fmods(self
):
2233 lst
= list(SVP64Asm(["fmods 3,4,5"]))
2236 fprs
[4] = 0x3ff0000000000000 # 1.0
2237 fprs
[5] = 0x3ff0000000000000 # 1.0
2238 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2240 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2242 def case_fmods_(self
):
2243 lst
= list(SVP64Asm(["fmods. 3,4,5"]))
2246 fprs
[4] = 0x3ff0000000000000 # 1.0
2247 fprs
[5] = 0x3ff0000000000000 # 1.0
2248 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2251 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2253 def case_fmod(self
):
2254 lst
= list(SVP64Asm(["fmod 3,4,5"]))
2257 fprs
[4] = 0x3ff0000000000000 # 1.0
2258 fprs
[5] = 0x3ff0000000000000 # 1.0
2259 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2261 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2263 def case_fmod_(self
):
2264 lst
= list(SVP64Asm(["fmod. 3,4,5"]))
2267 fprs
[4] = 0x3ff0000000000000 # 1.0
2268 fprs
[5] = 0x3ff0000000000000 # 1.0
2269 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2272 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2274 def case_fremainders(self
):
2275 lst
= list(SVP64Asm(["fremainders 3,4,5"]))
2278 fprs
[4] = 0x3ff0000000000000 # 1.0
2279 fprs
[5] = 0x3ff0000000000000 # 1.0
2280 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2282 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2284 def case_fremainders_(self
):
2285 lst
= list(SVP64Asm(["fremainders. 3,4,5"]))
2288 fprs
[4] = 0x3ff0000000000000 # 1.0
2289 fprs
[5] = 0x3ff0000000000000 # 1.0
2290 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2293 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2295 def case_fremainder(self
):
2296 lst
= list(SVP64Asm(["fremainder 3,4,5"]))
2299 fprs
[4] = 0x3ff0000000000000 # 1.0
2300 fprs
[5] = 0x3ff0000000000000 # 1.0
2301 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2303 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)
2305 def case_fremainder_(self
):
2306 lst
= list(SVP64Asm(["fremainder. 3,4,5"]))
2309 fprs
[4] = 0x3ff0000000000000 # 1.0
2310 fprs
[5] = 0x3ff0000000000000 # 1.0
2311 e
= ExpectedState(pc
=4, int_regs
=gprs
, fp_regs
=fprs
)
2314 self
.add_case(Program(lst
, False), gprs
, fpregs
=fprs
, expected
=e
)