src/openpower/test/runner.py

   1 """TestRunner class, part of the Test API
   2
   3 SPDX-License: LGPLv2+
   4
   5 Copyright (C) 2020,2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6 Copyright (C) 2021 Kyle Lehman <klehman9@comcast.net>
   7 Copyright (C) 2021 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
   8 Copyright (C) 2021 Tobias Platen <tplaten@posteo.de>
   9 Copyright (C) 2021 Cesar Strauss <cestrauss@gmail.com>
  10
  11 related bugs:
  12
  13  * https://bugs.libre-soc.org/show_bug.cgi?id=363
  14  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
  15 """
  16
  17 from nmigen import Module, ClockSignal
  18 from copy import copy
  19 from pprint import pprint
  20
  21 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  22 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  23 from nmutil.sim_tmp_alternative import Simulator, Settle
  24
  25 from nmutil.formaltest import FHDLTestCase
  26 from nmutil.gtkw import write_gtkw
  27 from openpower.decoder.isa.all import ISA
  28 from openpower.endian import bigendian
  29
  30 from openpower.decoder.power_decoder2 import PowerDecode2
  31
  32 from soc.config.test.test_loadstore import TestMemPspec
  33 from nmutil.util import wrap
  34 from openpower.test.wb_get import wb_get
  35 import openpower.test.wb_get as wbget
  36 from openpower.test.state import TestState, StateRunner, ExpectedState
  37
  38
  39 class SimRunner(StateRunner):
  40     """SimRunner:  Implements methods for the setup, preparation, and
  41     running of tests using ISACaller simulation
  42     """
  43     def __init__(self, dut, m, pspec):
  44         super().__init__("sim", SimRunner)
  45         self.dut = dut
  46
  47         self.mmu = pspec.mmu == True
  48         regreduce_en = pspec.regreduce_en == True
  49         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
  50         m.submodules.simdec2 = simdec2  # pain in the neck
  51
  52     def prepare_for_test(self, test):
  53         self.test = test
  54         if False:
  55             yield
  56
  57     def run_test(self, instructions, gen, insncode):
  58         """run_sim_state - runs an ISACaller simulation
  59         """
  60
  61         dut, test, simdec2 = self.dut, self.test, self.simdec2
  62         sim_states = []
  63
  64         # set up the Simulator (which must track TestIssuer exactly)
  65         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
  66                   test.msr,
  67                   initial_insns=gen, respect_pc=True,
  68                   disassembly=insncode,
  69                   bigendian=bigendian,
  70                   initial_svstate=test.svstate,
  71                   mmu=self.mmu)
  72
  73         # run the loop of the instructions on the current test
  74         index = sim.pc.CIA.value//4
  75         while index < len(instructions):
  76             ins, code = instructions[index]
  77
  78             print("sim instr: 0x{:X}".format(ins & 0xffffffff))
  79             print(index, code)
  80
  81             # set up simulated instruction (in simdec2)
  82             try:
  83                 yield from sim.setup_one()
  84             except KeyError:  # instruction not in imem: stop
  85                 break
  86             yield Settle()
  87
  88             # call simulated operation
  89             print("sim", code)
  90             yield from sim.execute_one()
  91             yield Settle()
  92             index = sim.pc.CIA.value//4
  93
  94             # get sim register and memory TestState, add to list
  95             state = yield from TestState("sim", sim, dut, code)
  96             sim_states.append(state)
  97
  98         if self.dut.allow_overlap:
  99             # get last state, at end of run
 100             state = yield from TestState("sim", sim, dut, code)
 101             sim_states.append(state)
 102
 103         return sim_states
 104
 105
 106 class TestRunnerBase(FHDLTestCase):
 107     """TestRunnerBase:  Sets up and executes the running of tests
 108     contained in tst_data. run_hdl (if provided) is an HDLRunner
 109     object.  If not provided, hdl simulation is skipped.
 110
 111     ISACaller simulation can be skipped by setting run_sim=False.
 112
 113     When using an Expected state to test with, the expected state
 114     is passed in with tst_data.
 115     """
 116     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 117                         svp64=True, run_hdl=None, run_sim=True,
 118                         allow_overlap=False):
 119         super().__init__("run_all")
 120         self.test_data = tst_data
 121         self.microwatt_mmu = microwatt_mmu
 122         self.rom = rom
 123         self.svp64 = svp64
 124         self.allow_overlap = allow_overlap
 125         self.run_hdl = run_hdl
 126         self.run_sim = run_sim
 127
 128     def run_all(self):
 129         m = Module()
 130         comb = m.d.comb
 131         if self.microwatt_mmu:
 132             # do not wire these up to anything if wb_get is to be used
 133             if self.rom is not None:
 134                 ldst_ifacetype = 'mmu_cache_wb'
 135                 imem_ifacetype = 'mmu_cache_wb'
 136             else:
 137                 ldst_ifacetype = 'test_mmu_cache_wb'
 138                 imem_ifacetype = 'test_bare_wb'
 139         else:
 140             ldst_ifacetype = 'test_bare_wb'
 141             imem_ifacetype = 'test_bare_wb'
 142
 143         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 144                              imem_ifacetype=imem_ifacetype,
 145                              addr_wid=48,
 146                              mask_wid=8,
 147                              imem_reg_wid=64,
 148                              # wb_data_width=32,
 149                              use_pll=False,
 150                              nocore=False,
 151                              xics=False,
 152                              gpio=False,
 153                              regreduce=not self.allow_overlap,
 154                              svp64=self.svp64,
 155                              allow_overlap=self.allow_overlap,
 156                              mmu=self.microwatt_mmu,
 157                              reg_wid=64)
 158
 159         ###### SETUP PHASE #######
 160         # Determine the simulations needed and add to state_list
 161         # for setup and running
 162         # The methods contained in the respective Runner classes are
 163         # called using this list when possible
 164
 165         # allow wb_get to run
 166         if self.rom is not None:
 167             wbget.stop = False
 168
 169         state_list = []
 170
 171         if self.run_hdl:
 172             hdlrun = self.run_hdl(self, m, pspec)
 173             state_list.append(hdlrun)
 174
 175         if self.run_sim:
 176             simrun = SimRunner(self, m, pspec)
 177             state_list.append(simrun)
 178
 179         # run core clock at same rate as test clock
 180         # XXX this has to stay here! TODO, work out why,
 181         # but Simulation-only fails without it
 182         intclk = ClockSignal("coresync")
 183         comb += intclk.eq(ClockSignal())
 184
 185         # nmigen Simulation - everything runs around this, so it
 186         # still has to be created.
 187         sim = Simulator(m)
 188         sim.add_clock(1e-6)
 189
 190         def process():
 191
 192             ###### PREPARATION PHASE AT START OF RUNNING #######
 193
 194             for runner in state_list:
 195                 yield from runner.setup_during_test()
 196
 197             # get each test, completely reset the core, and run it
 198
 199             for test in self.test_data:
 200
 201                 with self.subTest(test.name):
 202
 203                     ###### PREPARATION PHASE AT START OF TEST #######
 204
 205                     for runner in state_list:
 206                         yield from runner.prepare_for_test(test)
 207
 208                     print(test.name)
 209                     program = test.program
 210                     print("regs", test.regs)
 211                     print("sprs", test.sprs)
 212                     print("cr", test.cr)
 213                     print("mem", test.mem)
 214                     print("msr", test.msr)
 215                     print("assem", program.assembly)
 216                     gen = list(program.generate_instructions())
 217                     insncode = program.assembly.splitlines()
 218                     instructions = list(zip(gen, insncode))
 219
 220                     ###### RUNNING OF EACH TEST #######
 221                     # StateRunner.step_test()
 222
 223                     # Run two tests (TODO, move these to functions)
 224                     # * first the Simulator, collate a batch of results
 225                     # * then the HDL, likewise
 226                     #   (actually, the other way round because running
 227                     #    Simulator somehow modifies the test state!)
 228                     # * finally, compare all the results
 229
 230                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 231
 232                     ##########
 233                     # 1. HDL
 234                     ##########
 235                     if self.run_hdl:
 236                         hdl_states = yield from hdlrun.run_test(instructions)
 237
 238                     ##########
 239                     # 2. Simulator
 240                     ##########
 241
 242                     if self.run_sim:
 243                         sim_states = yield from simrun.run_test(
 244                                                           instructions, gen,
 245                                                           insncode)
 246
 247                     ###### COMPARING THE TESTS #######
 248
 249                     ###############
 250                     # 3. Compare
 251                     ###############
 252
 253                     # TODO: here just grab one entry from list_of_sim_runners
 254                     # (doesn't matter which one, honestly)
 255                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 256
 257                     if self.run_sim:
 258                         last_sim = copy(sim_states[-1])
 259                     elif self.run_hdl:
 260                         last_sim = copy(hdl_states[-1])
 261                     else:
 262                         last_sim = None # err what are you doing??
 263
 264                     if self.run_hdl:
 265                         print ("hdl_states")
 266                         for state in hdl_states:
 267                             print (state)
 268
 269                     if self.run_sim:
 270                         print ("sim_states")
 271                         for state in sim_states:
 272                             print (state)
 273
 274                     # compare the states
 275                     if self.run_hdl and self.run_sim:
 276                         # if allow_overlap is enabled, because allow_overlap
 277                         # can commit out-of-order, only compare the last ones
 278                         if self.allow_overlap:
 279                             print ("allow_overlap: truncating %d %d "
 280                                     "states to last" % (len(sim_states),
 281                                                         len(hdl_states)))
 282                             sim_states = sim_states[-1:]
 283                             hdl_states = hdl_states[-1:]
 284                             sim_states[-1].dump_state_tofile()
 285                             print ("allow_overlap: last hdl_state")
 286                             hdl_states[-1].dump_state_tofile()
 287                         for simstate, hdlstate in zip(sim_states, hdl_states):
 288                             simstate.compare(hdlstate)     # register check
 289                             simstate.compare_mem(hdlstate) # memory check
 290
 291                     # if no expected, create /tmp/case_name.py with code
 292                     # setting expected state to last_sim
 293                     if test.expected is None:
 294                         last_sim.dump_state_tofile(test.name, test.test_file)
 295
 296                     # compare against expected results
 297                     if test.expected is not None:
 298                         # have to put these in manually
 299                         test.expected.to_test = test.expected
 300                         test.expected.dut = self
 301                         test.expected.state_type = "expected"
 302                         test.expected.code = 0
 303                         # do actual comparison, against last item
 304                         last_sim.compare(test.expected)
 305
 306                     if self.run_hdl and self.run_sim:
 307                         self.assertTrue(len(hdl_states) == len(sim_states),
 308                                     "number of instructions run not the same")
 309
 310                 ###### END OF A TEST #######
 311                 # StateRunner.end_test()
 312
 313                 for runner in state_list:
 314                     yield from runner.end_test() # TODO, some arguments?
 315
 316             ###### END OF EVERYTHING (but none needs doing, still call fn) ####
 317             # StateRunner.cleanup()
 318
 319             for runner in state_list:
 320                 yield from runner.cleanup() # TODO, some arguments?
 321
 322             # finally stop wb_get from going
 323             if self.rom is not None:
 324                 wbget.stop = True
 325
 326         styles = {
 327             'dec': {'base': 'dec'},
 328             'bin': {'base': 'bin'},
 329             'closed': {'closed': True}
 330         }
 331
 332         traces = [
 333             'clk',
 334             ('state machines', 'closed', [
 335                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 336                 'fetch_fsm_state',
 337                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 338                 'pred_insn_i_valid', 'pred_insn_o_ready',
 339                 'fetch_predicate_state',
 340                 'pred_mask_o_valid', 'pred_mask_i_ready',
 341                 'issue_fsm_state',
 342                 'exec_insn_i_valid', 'exec_insn_o_ready',
 343                 'exec_fsm_state',
 344                 'exec_pc_o_valid', 'exec_pc_i_ready',
 345                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 346                 'is_last', 'dec2.no_out_vec']),
 347             {'comment': 'fetch and decode'},
 348             (None, 'dec', [
 349                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
 350                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 351             'raw_insn_i[31:0]',
 352             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 353             ('svp64 decoding', 'closed', [
 354                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 355                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 356                 'dec2.sv_rm_dec.ptype_in',
 357                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 358                 'dstmask[63:0]', 'srcmask[63:0]',
 359                 'dregread[4:0]', 'dinvert',
 360                 'sregread[4:0]', 'sinvert',
 361                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 362                 'core.int.pred__ren']),
 363             ('register augmentation', 'dec', 'closed', [
 364                 {'comment': 'v3.0b registers'},
 365                 'dec2.dec_o.RT[4:0]',
 366                 'dec2.dec_a.RA[4:0]',
 367                 'dec2.dec_b.RB[4:0]',
 368                 ('Rdest', [
 369                     'dec2.o_svdec.reg_in[4:0]',
 370                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 371                     'dec2.o_svdec.reg_out[6:0]']),
 372                 ('Rsrc1', [
 373                     'dec2.in1_svdec.reg_in[4:0]',
 374                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 375                     'dec2.in1_svdec.reg_out[6:0]']),
 376                 ('Rsrc1', [
 377                     'dec2.in2_svdec.reg_in[4:0]',
 378                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 379                     'dec2.in2_svdec.reg_out[6:0]']),
 380                 {'comment': 'SVP64 registers'},
 381                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 382             ]),
 383             {'comment': 'svp64 context'},
 384             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 385             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 386             'core_core_dststep[6:0]',
 387             {'comment': 'issue and execute'},
 388             'core.core_core_insn_type',
 389             (None, 'dec', [
 390                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 391             'issue_i', 'busy_o',
 392             {'comment': 'dmi'},
 393             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 394             {'comment': 'instruction memory'},
 395             'imem.sram.rdport.memory(0)[63:0]',
 396             {'comment': 'registers'},
 397             # match with soc.regfile.regfiles.IntRegs port names
 398             'core.int.rp_src1.memory(0)[63:0]',
 399             'core.int.rp_src1.memory(1)[63:0]',
 400             'core.int.rp_src1.memory(2)[63:0]',
 401             'core.int.rp_src1.memory(3)[63:0]',
 402             'core.int.rp_src1.memory(4)[63:0]',
 403             'core.int.rp_src1.memory(5)[63:0]',
 404             'core.int.rp_src1.memory(6)[63:0]',
 405             'core.int.rp_src1.memory(7)[63:0]',
 406             'core.int.rp_src1.memory(9)[63:0]',
 407             'core.int.rp_src1.memory(10)[63:0]',
 408             'core.int.rp_src1.memory(13)[63:0]',
 409             # Exceptions: see list archive for description of the chain
 410             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
 411             ('exceptions', 'closed', [
 412                 'exc_happened',
 413                 'pdecode2.exc_happened',
 414                 'core.exc_happened',
 415                 'core.fus.ldst0.exc_o_happened']),
 416         ]
 417
 418         # PortInterface module path varies depending on MMU option
 419         if self.microwatt_mmu:
 420             pi_module = 'core.ldst0'
 421         else:
 422             pi_module = 'core.fus.ldst0'
 423
 424         traces += [('ld/st port interface', {'submodule': pi_module}, [
 425             'oper_r__insn_type',
 426             'oper_r__msr[63:0]',
 427             'ldst_port0_is_ld_i',
 428             'ldst_port0_is_st_i',
 429             'ldst_port0_busy_o',
 430             'ldst_port0_addr_i[47:0]',
 431             'ldst_port0_addr_i_ok',
 432             'ldst_port0_addr_ok_o',
 433             'ldst_port0_exc_happened',
 434             'ldst_port0_st_data_i[63:0]',
 435             'ldst_port0_st_data_i_ok',
 436             'ldst_port0_ld_data_o[63:0]',
 437             'ldst_port0_ld_data_o_ok',
 438             'ldst_port0_msr_pr',
 439             'exc_o_happened',
 440             'cancel'
 441         ])]
 442
 443         if self.microwatt_mmu:
 444             traces += [
 445                 {'comment': 'microwatt_mmu'},
 446                 'core.fus.mmu0.alu_mmu0.illegal',
 447                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 448                 'core.fus.mmu0.alu_mmu0.mmu.state',
 449                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 450                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 451                 {'comment': 'wishbone_memory'},
 452                 'core.l0.pimem.bus__ack',
 453                 'core.l0.pimem.bus__adr[4:0]',
 454                 'core.l0.pimem.bus__bte',
 455                 'core.l0.pimem.bus__cti',
 456                 'core.l0.pimem.bus__cyc',
 457                 'core.l0.pimem.bus__dat_r[63:0]',
 458                 'core.l0.pimem.bus__dat_w[63:0]',
 459                 'core.l0.pimem.bus__dat_err',
 460                 'core.l0.pimem.bus__dat_sel[7:0]',
 461                 'core.l0.pimem.bus__dat_stb',
 462                 'core.l0.pimem.bus__dat_we',
 463             ]
 464
 465         write_gtkw("issuer_simulator.gtkw",
 466                    "issuer_simulator.vcd",
 467                    traces, styles, module='top.issuer')
 468
 469         # add run of instructions
 470         sim.add_sync_process(process)
 471
 472         # ARGH oh whoops. TODO, core is not passed in!
 473         # urrr... work out a hacky-way to sort this (access run_hdl
 474         # core directly for now)
 475
 476         # optionally, if a wishbone-based ROM is passed in, run that as an
 477         # extra emulated process
 478         if self.rom is not None:
 479             print ("TestRunner with MMU ROM")
 480             pprint (self.rom)
 481             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
 482             icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache
 483             default_mem = self.rom
 484             sim.add_sync_process(wrap(wb_get(dcache.bus,
 485                                              default_mem, "DCACHE")))
 486             sim.add_sync_process(wrap(wb_get(icache.ibus,
 487                                              default_mem, "ICACHE")))
 488
 489         with sim.write_vcd("issuer_simulator.vcd"):
 490             sim.run()