src/openpower/test/test_state_class.py

   1 """ Test States
   2
   3 This module tests the functionality of the state class by manually
   4 loading various registers and memory with values to be compared
   5 between different states.
   6
   7 related bugs:
   8     * https://bugs.libre-soc.org/show_bug.cgi?id=686
   9
  10 """
  11
  12 import unittest
  13 import random
  14 from openpower.test.state import SimState, state_factory
  15 from soc.simple.test.teststate import HDLState
  16
  17
  18 class TestStates(unittest.TestCase):
  19     def test_basic_regs(self):
  20         initial_regs = [0] * 32
  21         for i in range(32):
  22             initial_regs[i] = random.randint(0, (1 << 64) - 1)
  23         sim = self.empty_state('sim')
  24         sim.intregs = initial_regs
  25         hdl = self.empty_state('hdl')
  26         hdl.intregs = initial_regs
  27         sim.compare(hdl)
  28         sim = self.empty_state('sim')
  29         sim.intregs = initial_regs
  30         hdl = self.empty_state('hdl')
  31         hdl.intregs = initial_regs
  32         hdl.compare(sim)
  33
  34     @unittest.expectedFailure
  35     def test_basic_regs_fail(self):
  36         initial_regs = [0] * 32
  37         for i in range(32):
  38             initial_regs[i] = random.randint(0, (1 << 64) - 1)
  39             fail_regs[i] = random.randint(0, (1 << 64) - 1)
  40         sim = self.empty_state('sim')
  41         sim.intregs = initial_regs
  42         hdl = self.empty_state('hdl')
  43         hdl.intregs = fail_regs
  44         sim.compare(hdl)
  45         sim = self.empty_state('sim')
  46         sim.intregs = initial_regs
  47         hdl = self.empty_state('hdl')
  48         hdl.intregs = fail_regs
  49         hdl.compare(sim)
  50
  51     def test_basic_mem(self):
  52         initial_mem = {}
  53         for i in range(32):
  54             initial_mem[i*8] = random.randint(0, (1 << 64) - 1)
  55         sim = self.empty_state('sim')
  56         sim.mem = initial_mem
  57         hdl = self.empty_state('hdl')
  58         hdl.mem = initial_mem
  59         sim.compare_mem(hdl)
  60         hdl.compare_mem(sim)
  61
  62     def test_basic_mem_size_0_diff(self):
  63         sim_mem = {0: 8, 16: 24, 240: 32}
  64         hdl_mem = {0: 8, 16: 24, 224: 0, 232: 0, 240: 32}
  65         sim = self.empty_state('sim')
  66         sim.mem = sim_mem
  67         hdl = self.empty_state('hdl')
  68         hdl.mem = hdl_mem
  69         sim.compare_mem(hdl)
  70         hdl.compare_mem(sim)
  71
  72     @unittest.expectedFailure
  73     def test_basic_mem_size_fail(self):
  74         initial_mem = {}
  75         for i in range(32):
  76             initial_mem[i] = random.randint(0, (1 << 64) - 1)
  77         sim = self.empty_state('sim')
  78         sim.mem = initial_mem
  79         hdl = self.empty_state('hdl')
  80         for i in range(16):
  81             hdl.mem[i] = initial_mem[i]
  82         sim.compare_mem(hdl)
  83         hdl.compare_mem(sim)
  84
  85     @unittest.expectedFailure
  86     def test_basic_mem_off_by_one(self):
  87         sim_mem = {0: 8, 16: 24, 24: 0}
  88         hdl_mem = {0: 8, 8: 24, 24: 0}
  89         sim = self.empty_state('sim')
  90         sim.mem = sim_mem
  91         hdl = self.empty_state('hdl')
  92         hdl.mem = hdl_mem
  93         sim.compare_mem(hdl)
  94         hdl.compare_mem(sim)
  95
  96     @unittest.expectedFailure
  97     def test_basic_mem_one_word_fail(self):
  98         sim_mem = {0: 8}
  99         hdl_mem = {0: 16}
 100         sim = self.empty_state('sim')
 101         sim.mem = sim_mem
 102         hdl = self.empty_state('hdl')
 103         hdl.mem = hdl_mem
 104         sim.compare_mem(hdl)
 105         hdl.compare_mem(sim)
 106
 107     @unittest.expectedFailure
 108     def test_basic_no_mem_fail(self):
 109         hdl_mem = {16: 32}
 110         sim = self.empty_state('sim')
 111         hdl = self.empty_state('hdl')
 112         hdl.mem = hdl_mem
 113         sim.compare_mem(hdl)
 114         hdl.compare_mem(sim)
 115
 116     def empty_state(self, state_type):
 117         state_class = state_factory[state_type]
 118         state = state_class(None)
 119         state.intregs = []
 120         state.crregs = []
 121         state.pc = []
 122         state.so, state.sv, state.ov, state.ca = 0, 0, 0, 0
 123         state.mem = {}
 124         state.code = 0
 125         state.dut = self
 126         state.state_type = state_type
 127         return state
 128
 129
 130 if __name__ == '__main__':
 131     unittest.main()