fix bigint shift tests
[openpower-isa.git] / src /
2022-10-28 Jacob Lifshayfix bigint shift tests dsld_dsrd_experiment
2022-10-27 Luke Kenneth Casso... add test for identifying [expr] * name in parser
2022-10-27 Dmitry Selyutinpower_enums: support shadd/shadduw instructions
2022-10-27 Dmitry Selyutinisa/caller.py: support shadd/shadduw instructions
2022-10-27 Luke Kenneth Casso... fix dsrd, ROTL128 use 128-n not 64-n,
2022-10-27 Luke Kenneth Casso... fix dsrd pseudocode for new 3-in 2-out
2022-10-27 Luke Kenneth Casso... sort out dsld pseudocode, creating mask is tricky
2022-10-27 Luke Kenneth Casso... endeavouring to implement shift-carry-dsld
2022-10-26 Luke Kenneth Casso... restore Z23 shadd/shadduw
2022-10-26 Luke Kenneth Casso... redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2...
2022-10-25 Dmitry Selyutinpysvp64asm: support shadd/shadduw instructions
2022-10-25 Dmitry Selyutinpysvp64asm: introduce more flexible Z23 wrapper
2022-10-25 Dmitry Selyutintest_pysvp64dis: test shadd/shadduw instructions
2022-10-25 Dmitry Selyutinminor_4.csv: support shadd/shadduw instructions
2022-10-24 Luke Kenneth Casso... add maxs. combined with cmp capability
2022-10-23 Luke Kenneth Casso... use svshape2 instead of svindex for the 4th shape
2022-10-22 Luke Kenneth Casso... add extra pysvp64dis tests for divmod2du and maddedu
2022-10-22 Luke Kenneth Casso... argh, extremely annoying: 4-operand dsld/dsrd is not...
2022-10-22 Luke Kenneth Casso... remove redundant case_dsrd3
2022-10-22 Luke Kenneth Casso... bigint shuffle
2022-10-22 Jacob Lifshayfix get_masked_reg and add test
2022-10-22 Jacob Lifshayformat code removing unused imports
2022-10-21 Luke Kenneth Casso... code-comments
2022-10-21 Luke Kenneth Casso... add 2nd outer loop, CTR 2 rounds, in chacha20 test
2022-10-21 Luke Kenneth Casso... move chacha20 to separate test, set/get masked regs...
2022-10-21 Luke Kenneth Casso... move HASK, ROTL32, ROTL64, MASK32, into helper class
2022-10-20 Luke Kenneth Casso... comments
2022-10-20 Luke Kenneth Casso... add first chacha20 round test
2022-10-19 Dmitry Selyutinsv_binutils_fptrans: fix registers generation
2022-10-19 Luke Kenneth Casso... TODO, sort out remap indices order
2022-10-18 Jacob Lifshayadd test for scalar sv.maddedu
2022-10-18 Jacob Lifshayadd missing files to .gitignore
2022-10-16 Luke Kenneth Casso... debug print correction
2022-10-16 Luke Kenneth Casso... sigh, have to use yield from on get_out_map()
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out2 in ISACaller to split out
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out in ISACaller to split out
2022-10-16 Luke Kenneth Casso... add unit test showing two svindex calls, found bugs,
2022-10-16 Luke Kenneth Casso... code-shuffle, rework get_idx_in() to separate out the...
2022-10-14 Dmitry Selyutinsv_binutils_fptrans: fix opcodes mode
2022-10-14 Dmitry Selyutinpower_insn: really skip sv. entries for PPC database
2022-10-14 Dmitry Selyutinsv_binutils_fptrans: generate all permutations
2022-10-14 Dmitry Selyutinpysvp64asm: fix coding style
2022-10-14 Dmitry Selyutinpower_insn: skip sv. instructions in PPC database
2022-10-14 Dmitry Selyutinpower_insn: fix AA match
2022-10-14 Dmitry Selyutinpower_insn: do not allow default records
2022-10-14 Luke Kenneth Casso... add max-with-getting-index-of vertical-first loop example
2022-10-14 Luke Kenneth Casso... SVP64RMModeDecode detects Post-Inc LDST-imm mode
2022-10-14 Luke Kenneth Casso... correct comments
2022-10-14 Luke Kenneth Casso... add in zeroing on test strncpy
2022-10-14 Luke Kenneth Casso... remove unneeded svstate from test
2022-10-14 Luke Kenneth Casso... add strncpy example - 6 instructions
2022-10-14 Luke Kenneth Casso... add sv.stwu/pi example in test_sv_load_store_postinc
2022-10-14 Luke Kenneth Casso... add ld/st-immediate "post-inc" mode support. unit test...
2022-10-14 Luke Kenneth Casso... add /pi to sv/trans/svp64.py and power_insns.py
2022-10-14 Luke Kenneth Casso... add new LD-Immediate Post constants
2022-10-12 Luke Kenneth Casso... add sv.divmod2du test, inverse of the sv.madded
2022-10-12 Luke Kenneth Casso... comments clean-up on bigint big-mul case
2022-10-11 Luke Kenneth Casso... add asciidump option to Mem class
2022-10-11 Luke Kenneth Casso... whoops zero-error on masked-out
2022-10-10 Luke Kenneth Casso... add elwidth overrides on Indexed REMAP, 8-bit example...
2022-10-10 Luke Kenneth Casso... add elwidth overrides to get_idx_out2
2022-10-08 Luke Kenneth Casso... fix format in debug log
2022-10-08 Luke Kenneth Casso... forgot to add offset on GPR() get
2022-10-08 Luke Kenneth Casso... add elwidth overrides on destination (write) in ISACaller.
2022-10-08 Luke Kenneth Casso... split out base,offset in register decoding for elwidth...
2022-10-08 Luke Kenneth Casso... add 8-bit elwidth alu svp64 case
2022-10-08 Luke Kenneth Casso... add rfscv to major_19.csv, add test_pysvp64dis.py unit...
2022-10-08 Luke Kenneth Casso... drat
2022-10-08 Luke Kenneth Casso... add sc and scv support after moving from major.csv...
2022-10-08 Luke Kenneth Casso... vector name "RSp" not recognised in sv.stq, added as...
2022-10-08 Luke Kenneth Casso... add stq to CSV files and unit test to test_pysvp64dis.py
2022-10-08 Luke Kenneth Casso... separate out DQ and DS to separate custom_immediates
2022-10-08 Luke Kenneth Casso... use new base-class EXTSOperand, derive from ImmediateOp...
2022-10-08 Luke Kenneth Casso... convert TargetAddrOperand to base class EXTSOperand
2022-10-08 Luke Kenneth Casso... add lq and CONST_DQ
2022-10-08 Luke Kenneth Casso... restore tests, accidentally disabled
2022-10-08 Luke Kenneth Casso... add XER bits to register enums
2022-10-08 Luke Kenneth Casso... add addex to csv and sv_analysis db. also needs CryIn...
2022-10-07 Luke Kenneth Casso... more work on inssort. add useful reg-dump in ISACaller
2022-10-06 Luke Kenneth Casso... nope. failfirst needs to always save the result, but...
2022-10-06 Luke Kenneth Casso... fix fail-first to exclude failed element in VLi=0 mode
2022-10-06 Luke Kenneth Casso... sort out CROPs fail-first in ISACaller. needed to...
2022-10-06 Luke Kenneth Casso... make fail-first cope with sv.cmp which uses CR[BF]
2022-10-06 Luke Kenneth Casso... add insert sort svp64 test
2022-10-06 Luke Kenneth Casso... search for BF in registers to over-ride Vector lookup...
2022-10-06 Luke Kenneth Casso... starting to add sv.cmp support and failfirst, had to add
2022-10-06 Luke Kenneth Casso... add PredicateBaseRM decode to CR Ops Simple mode as...
2022-10-06 Luke Kenneth Casso... add vli mode to ff=5 CR ops
2022-10-06 Luke Kenneth Casso... whoops must only be PredicateBaseRM in CROpFF5RM
2022-10-06 Luke Kenneth Casso... add sv.cmp (ffirst-5) decode/encode asm support
2022-10-06 Luke Kenneth Casso... slightly different crops failfirst mode bits
2022-10-06 Luke Kenneth Casso... add sv.cmp and try fail-first test_pysvp64dist.py
2022-10-02 Luke Kenneth Casso... remove complaints about standard Cray-style Vectors...
2022-10-02 Luke Kenneth Casso... comments for why preinc is called for svstep
2022-10-02 Luke Kenneth Casso... comment out selectableint getitem logs
2022-10-01 Luke Kenneth Casso... skip svstate_pre_inc on svremap
2022-10-01 Luke Kenneth Casso... no svstate instruction
2022-10-01 Luke Kenneth Casso... svstep calls SVSTATE_NEXT so needs svstate_pre_inc
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
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