src/spec/jtag.py

   1 """JTAG interface
   2
   3 using Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 from collections import OrderedDict
   7 from nmigen import (Module, Signal, Elaboratable, Cat)
   8 from nmigen.cli import rtlil
   9 from c4m.nmigen.jtag.tap import IOType, TAP
  10
  11 # map from pinmux to c4m jtag iotypes
  12 iotypes = {'-': IOType.In,
  13            '+': IOType.Out,
  14            '>': IOType.TriOut,
  15            '*': IOType.InTriOut,
  16         }
  17
  18 resiotypes = {'i': IOType.In,
  19            'o': IOType.Out,
  20            'oe': IOType.TriOut,
  21            'io': IOType.InTriOut,
  22         }
  23
  24 scanlens = {IOType.In: 1,
  25            IOType.Out: 1,
  26            IOType.TriOut: 2,
  27            IOType.InTriOut: 3,
  28             }
  29
  30 def dummy_pinset():
  31     # sigh this needs to come from pinmux.
  32     gpios = []
  33     for i in range(16):
  34         gpios.append("%d*" % i)
  35     return {'uart': ['tx+', 'rx-'],
  36              'gpio': gpios,
  37              'i2c': ['sda*', 'scl+']}
  38
  39
  40 # TODO: move to suitable location
  41 class Pins:
  42     """declare a list of pins, including name and direction.  grouped by fn
  43     the pin dictionary needs to be in a reliable order so that the JTAG
  44     Boundary Scan is also in a reliable order
  45     """
  46     def __init__(self, pindict=None):
  47         if pindict is None:
  48             pindict = {}
  49         self.io_names = OrderedDict()
  50         if isinstance(pindict, OrderedDict):
  51             self.io_names.update(pindict)
  52         else:
  53             keys = list(pindict.keys())
  54             keys.sort()
  55             for k in keys:
  56                 self.io_names[k] = pindict[k]
  57
  58     def __iter__(self):
  59         # start parsing io_names and enumerate them to return pin specs
  60         scan_idx = 0
  61         for fn, pins in self.io_names.items():
  62             for pin in pins:
  63                 # decode the pin name and determine the c4m jtag io type
  64                 name, pin_type = pin[:-1], pin[-1]
  65                 iotype = iotypes[pin_type]
  66                 pin_name = "%s_%s" % (fn, name)
  67                 yield (fn, name, iotype, pin_name, scan_idx)
  68                 scan_idx += scanlens[iotype] # inc boundary reg scan offset
  69
  70
  71 class JTAG(TAP, Pins):
  72     # 32-bit data width here so that it matches with litex
  73     def __init__(self, pinset, domain, wb_data_wid=32):
  74         self.domain = domain
  75         TAP.__init__(self, ir_width=4)
  76         Pins.__init__(self, pinset)
  77
  78         # enumerate pin specs and create IOConn Records.
  79         # we store the boundary scan register offset in the IOConn record
  80         self.ios = {} # these are enumerated in external_ports
  81         self.scan_len = 0
  82         for fn, pin, iotype, pin_name, scan_idx in list(self):
  83             io = self.add_io(iotype=iotype, name=pin_name)
  84             io._scan_idx = scan_idx # hmm shouldn't really do this
  85             self.scan_len += scan_idx # record full length of boundary scan
  86             self.ios[pin_name] = io
  87
  88         # this is redundant.  or maybe part of testing, i don't know.
  89         self.sr = self.add_shiftreg(ircode=4, length=3,
  90                                     domain=domain)
  91
  92         # create and connect wishbone
  93         self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
  94                                    address_width=30, data_width=wb_data_wid,
  95                                    granularity=8, # 8-bit wide
  96                                    name="jtag_wb",
  97                                    domain=domain)
  98
  99         # create DMI2JTAG (goes through to dmi_sim())
 100         self.dmi = self.add_dmi(ircodes=[8, 9, 10],
 101                                     domain=domain)
 102
 103         # use this for enable/disable of parts of the ASIC.
 104         # XXX make sure to add the _en sig to en_sigs list
 105         self.wb_icache_en = Signal(reset=1)
 106         self.wb_dcache_en = Signal(reset=1)
 107         self.wb_sram_en = Signal(reset=1)
 108         self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
 109                                      self.wb_sram_en)
 110         self.sr_en = self.add_shiftreg(ircode=11, length=len(en_sigs),
 111                                        domain=domain)
 112
 113     def elaborate(self, platform):
 114         m = super().elaborate(platform)
 115         m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
 116
 117         # provide way to enable/disable wishbone caches and SRAM
 118         # just in case of issues
 119         # see https://bugs.libre-soc.org/show_bug.cgi?id=520
 120         with m.If(self.sr_en.oe):
 121             m.d.sync += self.en_sigs.eq(self.sr_en.o)
 122         # also make it possible to read the enable/disable current state
 123         with m.If(self.sr_en.ie):
 124             m.d.comb += self.sr_en.i.eq(self.en_sigs)
 125
 126         # create a fake "stall"
 127         #wb = self.wb
 128         #m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
 129
 130         return m
 131
 132     def external_ports(self):
 133         """create a list of ports that goes into the top level il (or verilog)
 134         """
 135         ports = super().external_ports()           # gets JTAG signal names
 136         ports += list(self.wb.fields.values())     # wishbone signals
 137         for io in self.ios.values():
 138             ports += list(io.core.fields.values()) # io "core" signals
 139             ports += list(io.pad.fields.values())  # io "pad" signals"
 140         return ports
 141
 142
 143 if __name__ == '__main__':
 144     pinset = dummy_pinset()
 145     dut = JTAG(pinset, "sync")
 146
 147     vl = rtlil.convert(dut)
 148     with open("test_jtag.il", "w") as f:
 149         f.write(vl)
 150