2 # see https://bugs.libre-soc.org/show_bug.cgi?id=304
4 from spec
.base
import PinSpec
5 from parse
import Parse
7 from pprint
import pprint
8 from spec
.ifaceprint
import display
, display_fns
, check_functions
9 from spec
.ifaceprint
import display_fixed
10 from collections
import OrderedDict
13 pinbanks
= OrderedDict((
41 'PWM': 'PWM (pulse-width modulation)',
42 'MSPI0': 'SPI Master 1 (general)',
43 'MSPI1': 'SPI Master 2 (SDCard)',
44 'UART0': 'UART (TX/RX) 1',
45 'SYS': 'System Control',
47 'EINT': 'External Interrupt',
50 'MTWI': 'I2C Master 1',
55 #'LPC1': 'Low Pincount Interface 1',
56 #'LPC2': 'Low Pincount Interface 2',
59 ps
= PinSpec(pinbanks
, fixedpins
, function_names
)
61 ps
.sdram1("", ('W', 0), 0, 15, 6, rev
=True) # AD4-9, turned round
62 ps
.vdd("E", ('W', 6), 0, 0, 1)
63 ps
.vss("E", ('W', 7), 0, 0, 1)
64 ps
.vdd("I", ('W', 8), 0, 0, 1)
65 ps
.vss("I", ('W', 9), 0, 0, 1)
66 ps
.sdram1("", ('W', 10), 0, 0, 15, rev
=True) # SDRAM DAM0, D0-7, AD0-3
67 ps
.mi2c("", ('W', 26), 0, 0, 2)
68 ps
.vss("I", ('W', 28), 0, 1, 1)
69 ps
.vdd("I", ('W', 29), 0, 1, 1)
70 ps
.vss("E", ('W', 30), 0, 1, 1)
71 ps
.vdd("E", ('W', 31), 0, 1, 1)
73 ps
.sdram2("", ('S', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
74 ps
.vdd("E", ('S', 4), 0, 2, 1)
75 ps
.vss("E", ('S', 5), 0, 2, 1)
76 ps
.vdd("I", ('S', 6), 0, 2, 1)
77 ps
.vss("I", ('S', 7), 0, 2, 1)
78 ps
.sdram2("", ('S', 8), 0, 4, 8) # D8-15
79 ps
.sdram1("", ('S', 16), 0, 21, 9) # clk etc.
80 ps
.vss("I", ('S', 22), 0, 3, 1)
81 ps
.vdd("I", ('S', 23), 0, 3, 1)
82 ps
.vss("E", ('S', 24), 0, 3, 1)
83 ps
.vdd("E", ('S', 25), 0, 3, 1)
84 ps
.uart("0", ('S', 26), 0)
85 ps
.mspi("0", ('S', 28), 0)
87 ps
.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
88 ps
.vss("E", ('E', 6), 0, 4, 1)
89 ps
.vdd("E", ('E', 7), 0, 4, 1)
90 ps
.vdd("I", ('E', 8), 0, 4, 1)
91 ps
.vss("I", ('E', 9), 0, 4, 1)
92 ps
.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
93 ps
.jtag("", ('E', 13), 0, 0, 4)
94 ps
.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
95 ps
.vss("I", ('E', 22), 0, 5, 1)
96 ps
.vdd("I", ('E', 23), 0, 5, 1)
97 ps
.vss("E", ('E', 24), 0, 5, 1)
98 ps
.vdd("E", ('E', 25), 0, 5, 1)
99 ps
.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
100 ps
.eint("", ('E', 28), 0, 0, 3)
101 ps
.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
103 ps
.vss("E", ('N', 6), 0, 6, 1)
104 ps
.vdd("E", ('N', 7), 0, 6, 1)
105 ps
.vdd("I", ('N', 8), 0, 6, 1)
106 ps
.vss("I", ('N', 9), 0, 6, 1)
107 #ps.pwm("", ('N', 2), 0, 0, 2) comment out (fabric problem 25mar2021)
108 #ps.mspi("1", ('N', 7), 0) comment out (fabric problem 25mar2021)
109 #ps.sdmmc("0", ('N', 11), 0) # comment out (fabric problem 25mar2021)
110 ps
.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
111 ps
.vss("I", ('N', 22), 0, 7, 1)
112 ps
.vdd("I", ('N', 23), 0, 7, 1)
113 ps
.vss("E", ('N', 24), 0, 7, 1)
114 ps
.vdd("E", ('N', 25), 0, 7, 1)
116 #ps.mquadspi("1", ('S', 0), 0)
118 print ("ps clocks", ps
.clocks
)
120 # Scenarios below can be spec'd out as either "find first interface"
121 # by name/number e.g. SPI1, or as "find in bank/mux" which must be
122 # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
123 # EINT and PWM are grouped together, specially, but may still be spec'd
124 # using "BM:Name". Pins are removed in-order as listed from
125 # lists (interfaces, EINTs, PWMs) from available pins.
128 # 'SD0', fabric problem 25mar2021
129 'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
132 # 'MSPI1', fabric problem 25mar2021
135 ls180_pwm
= []#['B0:PWM_0']
137 'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
138 'and UART2, for debug purposes',
147 'B1:LCD/22': '18-bit RGB/TTL LCD',
148 'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
149 'ULPI1': 'dual USB2 Host ULPI PHY'
152 ps
.add_scenario("Libre-SOC 180nm", ls180
, ls180_eint
, ls180_pwm
,