rename to fabric
[pinmux.git] / src / spec / ngi_router.py
1 #!/usr/bin/env python
2 # see https://bugs.libre-soc.org/show_bug.cgi?id=739
3
4 from spec.base import PinSpec
5 from parse import Parse
6
7 from pprint import pprint
8 from spec.ifaceprint import display, display_fns, check_functions
9 from spec.ifaceprint import display_fixed
10 from collections import OrderedDict
11
12 def pinspec():
13 pinbanks = OrderedDict((
14 ('N', (32, 4)),
15 ('E', (32, 4)),
16 ('S', (32, 4)),
17 ('W', (32, 4)),
18 ))
19 fixedpins = {
20 'CTRL_SYS': [
21 'TEST',
22 'JTAG_SEL',
23 'UBOOT_SEL',
24 'NMI#',
25 'RESET#',
26 'CLK24M_IN',
27 'CLK24M_OUT',
28 'PLLTEST',
29 'PLLREGIO',
30 'PLLVP25',
31 'PLLDV',
32 'PLLVREG',
33 'PLLGND',
34 ],
35 'POWER_GPIO': [
36 'VDD_GPIOB',
37 'GND_GPIOB',
38 ]}
39 fixedpins = {}
40 function_names = {
41 'RG0': 'Gigabit Ethernet 0',
42 'PWM': 'PWM (pulse-width modulation)',
43 'MSPI0': 'SPI Master 1 (general)',
44 'MSPI1': 'SPI Master 2 (SDCard)',
45 'UART0': 'UART (TX/RX) 1',
46 'SYS': 'System Control',
47 'GPIO': 'GPIO',
48 'EINT': 'External Interrupt',
49 'PWM': 'PWM',
50 'JTAG': 'JTAG',
51 'MTWI': 'I2C Master 1',
52 'SD0': 'SD/MMC 1',
53 'SDR': 'SDRAM',
54 'VDD': 'Power',
55 'VSS': 'GND',
56 #'LPC1': 'Low Pincount Interface 1',
57 #'LPC2': 'Low Pincount Interface 2',
58 }
59
60 ps = PinSpec(pinbanks, fixedpins, function_names)
61
62 ps.gpio("", ('W', 0), 0, 0, 6) # GPIO 0-5
63 ps.sdram1("", ('W', 0), 1, 15, 6, rev=True) # AD4-9, turned round
64 ps.vdd("E", ('W', 6), 0, 0, 1)
65 ps.vss("E", ('W', 7), 0, 0, 1)
66 ps.vdd("I", ('W', 8), 0, 0, 1)
67 ps.vss("I", ('W', 9), 0, 0, 1)
68 ps.gpio("", ('W', 10), 0, 6, 15) # GPIO 6-20
69 ps.sdram1("", ('W', 10), 1, 0, 15, rev=True) # SDRAM DAM0, D0-7, AD0-3
70 ps.vss("I", ('W', 25), 0, 1, 1)
71 ps.vdd("I", ('W', 26), 0, 1, 1)
72 ps.vss("E", ('W', 27), 0, 1, 1)
73 ps.vdd("E", ('W', 28), 0, 1, 1)
74 ps.gpio("", ('W', 29), 0, 21, 3) # GPIO 21-23
75 ps.mi2c("", ('W', 30), 1, 0, 2)
76
77 ps.gpio("", ('S', 0), 0, 0, 4) # GPIO 0-4
78 ps.sdram2("", ('S', 0), 1, 0, 4) # 1st 4, AD10-12,DQM1
79 ps.vdd("E", ('S', 4), 0, 2, 1)
80 ps.vss("E", ('S', 5), 0, 2, 1)
81 ps.vdd("I", ('S', 6), 0, 2, 1)
82 ps.vss("I", ('S', 7), 0, 2, 1)
83 ps.gpio("", ('S', 8), 0, 4, 14) # GPIO 5-17
84 ps.sdram2("", ('S', 8), 1, 4, 8) # D8-15
85 ps.sdram1("", ('S', 16), 1, 21, 9) # clk etc.
86 ps.vss("I", ('S', 22), 0, 3, 1)
87 ps.vdd("I", ('S', 23), 0, 3, 1)
88 ps.vss("E", ('S', 24), 0, 3, 1)
89 ps.vdd("E", ('S', 25), 0, 3, 1)
90 ps.gpio("", ('S', 26), 0, 18, 6) # GPIO 18-23
91 ps.uart("0", ('S', 26), 1)
92 ps.mspi("0", ('S', 28), 1)
93
94 ps.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-3
95 ps.rgmii("1", ('E', 0), 1, 0, 6) # RXD0-3+CK/ERR
96 ps.vss("E", ('E', 6), 0, 4, 1)
97 ps.vdd("E", ('E', 7), 0, 4, 1)
98 ps.vdd("I", ('E', 8), 0, 4, 1)
99 ps.vss("I", ('E', 9), 0, 4, 1)
100 ps.gpio("", ('E', 10), 0, 6, 8) # GPIO 4-11
101 ps.rgmii("1", ('E', 10), 1, 6, 8) # more RGMII-2
102 ps.jtag("", ('E', 18), 0, 0, 4)
103 ps.vss("I", ('E', 22), 0, 5, 1)
104 ps.vdd("I", ('E', 23), 0, 5, 1)
105 ps.vss("E", ('E', 24), 0, 5, 1)
106 ps.vdd("E", ('E', 25), 0, 5, 1)
107 ps.gpio("", ('E', 26), 0, 16, 5) # GPIO 14-18
108 ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
109 ps.eint("", ('E', 28), 2, 0, 3)
110 ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
111
112 ps.gpio("", ('N', 0), 0, 0, 6) # GPIO 0-5
113 ps.rgmii("0", ('N', 0), 1, 0, 6) # RXD0-3+CK/ERR
114 ps.vss("E", ('N', 6), 0, 6, 1)
115 ps.vdd("E", ('N', 7), 0, 6, 1)
116 ps.vdd("I", ('N', 8), 0, 6, 1)
117 ps.vss("I", ('N', 9), 0, 6, 1)
118 ps.gpio("", ('N', 10), 0, 6, 12) # GPIO 4-17
119 ps.rgmii("0", ('N', 10), 1, 6, 12) # more RGMII-1
120 ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
121 ps.vss("I", ('N', 23), 0, 7, 1)
122 ps.vdd("I", ('N', 24), 0, 7, 1)
123 ps.vss("E", ('N', 25), 0, 7, 1)
124 ps.vdd("E", ('N', 26), 0, 7, 1)
125
126 #ps.mquadspi("1", ('S', 0), 0)
127
128 print ("ps clocks", ps.clocks)
129
130 # Scenarios below can be spec'd out as either "find first interface"
131 # by name/number e.g. SPI1, or as "find in bank/mux" which must be
132 # spec'd as "BM:Name" where B is bank (A-F), M is Mux (0-3)
133 # EINT and PWM are grouped together, specially, but may still be spec'd
134 # using "BM:Name". Pins are removed in-order as listed from
135 # lists (interfaces, EINTs, PWMs) from available pins.
136
137 ls180 = [
138 'UART0', 'JTAG', 'PWM', 'EINT',
139 'VDD', 'VSS', 'SYS',
140 'MTWI', 'MSPI0',
141 'RG0', 'RG1',
142 'SDR']
143 ls180_eint = []
144 ls180_pwm = []#['B0:PWM_0']
145 descriptions = {
146 'SD0': 'user-facing: internal (on Card), multiplexed with JTAG\n'
147 'and UART2, for debug purposes',
148 'MTWI': 'I2C.\n',
149 'E2:SD1': '',
150 'MSPI1': '',
151 'UART0': '',
152 'LPC1': '',
153 'RG0': '',
154 'RG1': '',
155 'SYS': '',
156 'LPC2': '',
157 'SDR': '',
158 'B1:LCD/22': '18-bit RGB/TTL LCD',
159 'ULPI0/8': 'user-facing: internal (on Card), USB-OTG ULPI PHY',
160 'ULPI1': 'dual USB2 Host ULPI PHY'
161 }
162
163 ps.add_scenario("Libre-SOC 2 (NGI Router) 180nm", ls180, ls180_eint,
164 ls180_pwm, descriptions)
165
166 return ps