src/spec/simple_gpio.py

   1 """Simple GPIO peripheral on wishbone
   2
   3 This is an extremely simple GPIO peripheral intended for use in XICS
   4 testing, however it could also be used as an actual GPIO peripheral
   5
   6 Modified for use with pinmux, will probably change the class name later.
   7 """
   8 from random import randint
   9 from nmigen import Elaboratable, Module, Signal, Record, Array
  10 from nmigen.utils import log2_int
  11 from nmigen.cli import rtlil
  12 from soc.minerva.wishbone import make_wb_layout
  13 from nmutil.util import wrap
  14 from soc.bus.test.wb_rw import wb_read, wb_write
  15
  16 cxxsim = False
  17 if cxxsim:
  18     from nmigen.sim.cxxsim import Simulator, Settle
  19 else:
  20     from nmigen.sim import Simulator, Settle
  21
  22 ADDROFFSET = 8 # offset where CSR/output/input addr are specified
  23 CSRADDR = 0 # addr to access CSR
  24 OADDR = 1 # addr needed to write/read output
  25 IADDR = 2 # addr to read GPIO inputs
  26 # Layout of 16-bit configuration word (? is unused):
  27 # ? ? ? i | bank_select[3:0] |? pden puen opendrain |? ien oe o
  28 ISHIFT = 12
  29 BANKSHIFT = 8
  30 # Pull-up/down, open-drain, ien have been skipped for now
  31 OESHIFT = 1
  32 OSHIFT = 0
  33
  34 class SimpleGPIO(Elaboratable):
  35
  36     def __init__(self, n_gpio=16):
  37         self.n_gpio = n_gpio
  38         class Spec: pass
  39         spec = Spec()
  40         spec.addr_wid = 30
  41         spec.mask_wid = 4
  42         spec.reg_wid = 32
  43         self.bus = Record(make_wb_layout(spec), name="gpio_wb")
  44         # ONLY ONE BANK FOR ALL GPIOs atm...
  45         self.bank_sel = Signal(4) # set maximum number of banks to 16
  46         self.gpio_o = Signal(n_gpio)
  47         self.gpio_oe = Signal(n_gpio)
  48         self.gpio_i = Signal(n_gpio)
  49
  50     def elaborate(self, platform):
  51         m = Module()
  52         comb, sync = m.d.comb, m.d.sync
  53
  54         bus = self.bus
  55         wb_rd_data = bus.dat_r
  56         wb_wr_data = bus.dat_w
  57         wb_ack = bus.ack
  58
  59         bank_sel = self.bank_sel
  60         gpio_o = self.gpio_o
  61         gpio_oe = self.gpio_oe
  62         gpio_i = self.gpio_i
  63
  64         comb += wb_ack.eq(0)
  65
  66         gpio_addr = Signal(log2_int(self.n_gpio))
  67         gpio_o_list = Array(list(gpio_o))
  68         print(bank_sel)
  69         print(gpio_o_list)
  70         gpio_oe_list = Array(list(gpio_oe))
  71         gpio_i_list = Array(list(gpio_i))
  72
  73         # Address first byte for GPIO (max would be 256 GPIOs)
  74         # Address second byte, indicates CSR, output, or input access
  75         with m.If(bus.cyc & bus.stb):
  76             comb += wb_ack.eq(1) # always ack
  77             comb += gpio_addr.eq(bus.adr[0:ADDROFFSET])
  78             with m.If(bus.we): # write
  79                 # Write/set output
  80                 with m.If(bus.adr[ADDROFFSET:] == OADDR):
  81                     sync += gpio_o_list[gpio_addr].eq(wb_wr_data[OSHIFT])
  82                 # Write/set CSR
  83                 with m.Else():
  84                     sync += gpio_o_list[gpio_addr].eq(wb_wr_data[OSHIFT])
  85                     sync += gpio_oe_list[gpio_addr].eq(wb_wr_data[OESHIFT])
  86                     sync += bank_sel.eq(wb_wr_data[BANKSHIFT:BANKSHIFT+4])
  87             with m.Else(): # read
  88                 # Read the value of the output
  89                 with m.If(bus.adr[ADDROFFSET:] == OADDR):
  90                     comb += wb_rd_data.eq(gpio_o_list[gpio_addr])
  91                 # Read the value of the input
  92                 with m.If(bus.adr[ADDROFFSET:] == IADDR):
  93                     comb += wb_rd_data.eq(gpio_i_list[gpio_addr])
  94                 # Read the state of CSR bits
  95                 with m.Else():
  96                     comb += wb_rd_data.eq((gpio_o_list[gpio_addr] << OSHIFT)
  97                                           + (gpio_oe_list[gpio_addr] << OESHIFT)
  98                                           + (bank_sel << BANKSHIFT))
  99         return m
 100
 101     def __iter__(self):
 102         for field in self.bus.fields.values():
 103             yield field
 104         yield self.gpio_o
 105
 106     def ports(self):
 107         return list(self)
 108
 109 def gpio_configure(dut, gpio, oe, output=0, bank_sel=0):
 110     csr_val = ( (bank_sel << BANKSHIFT)
 111               | (oe << OESHIFT)
 112               | (output << OSHIFT) )
 113               # | (PUEN, PDUN, Open-drain etc...)
 114     print("Configuring CSR to {0:x}".format(csr_val))
 115     yield from wb_write(dut.bus, gpio, csr_val)
 116
 117 # TODO: Return the configuration states
 118 def gpio_rd_csr(dut, gpio):
 119     csr_val = yield from wb_read(dut.bus, gpio)
 120     print("GPIO{0} | CSR: {1:x}".format(gpio, csr_val))
 121     # gpio_parse_csr(csr_val)
 122     return data
 123
 124 def gpio_rd_input(dut, gpio):
 125     in_val = yield from wb_read(dut.bus, gpio | (IADDR<<ADDROFFSET))
 126     print("GPIO{0} | Input: {1:b}".format(gpio, in_val))
 127     return data
 128
 129 def gpio_set_out(dut, gpio, output):
 130     yield from wb_write(dut.bus, gpio | (OADDR<<ADDROFFSET), (output<<OSHIFT))
 131
 132 # TODO: There's probably a cleaner way to clear the bit...
 133 def gpio_set_in_pad(dut, gpio, in_val):
 134     old_in_val = yield dut.gpio_i
 135     if in_val:
 136         new_in_val = old_in_val | (in_val << gpio)
 137     else:
 138         temp = (old_in_val >> gpio) & 1
 139         if temp:
 140             mask = ~(1 << gpio)
 141             new_in_val = old_in_val & mask
 142         else:
 143             new_in_val = old_in_val
 144     print("Previous GPIO i: {0:b} | New GPIO i: {1:b}"
 145           .format(old_in_val, new_in_val))
 146     yield dut.gpio_i.eq(new_in_val)
 147
 148 def sim_gpio(dut, use_random=True):
 149
 150     # GPIO0
 151     #data = yield from read_gpio(gpio, 0) # read gpio addr  0
 152     #yield from wb_write(gpio.bus, 0, 1) # write gpio addr 0
 153     #data = yield from read_gpio(gpio, 0) # read gpio addr  0
 154     print(dir(dut))
 155     print(dut)
 156     num_gpios = len(dut.gpio_o)
 157     if use_random:
 158         bank_sel = randint(0, num_gpios)
 159     else:
 160         bank_sel = 3 # not special, chose for testing
 161     oe = 1
 162     output = 0
 163     # Configure GPIOs for
 164     for gpio in range(0, num_gpios):
 165         yield from gpio_configure(dut, gpio, oe, output, bank_sel)
 166
 167     for gpio in range(0, num_gpios):
 168         yield from gpio_set_out(dut, gpio, 1)
 169
 170     for gpio in range(0, num_gpios):
 171         yield from gpio_set_in_pad(dut, gpio, 1)
 172         yield
 173
 174     for gpio in range(0, num_gpios):
 175         yield from gpio_set_in_pad(dut, gpio, 0)
 176         yield
 177
 178     print("Finished the simple GPIO block test!")
 179
 180 def test_gpio():
 181
 182     dut = SimpleGPIO()
 183     vl = rtlil.convert(dut, ports=dut.ports())
 184     with open("test_gpio.il", "w") as f:
 185         f.write(vl)
 186
 187     m = Module()
 188     m.submodules.xics_icp = dut
 189
 190     sim = Simulator(m)
 191     sim.add_clock(1e-6)
 192
 193     sim.add_sync_process(wrap(sim_gpio(dut)))
 194     sim_writer = sim.write_vcd('test_gpio.vcd')
 195     with sim_writer:
 196         sim.run()
 197
 198
 199 if __name__ == '__main__':
 200     test_gpio()
 201