2 from nmigen
.build
.dsl
import Resource
, Subsignal
, Pins
3 from nmigen
.build
.plat
import TemplatedPlatform
4 from nmigen
.build
.res
import ResourceManager
, ResourceError
5 from nmigen
import Elaboratable
, Signal
, Module
, Instance
6 from collections
import OrderedDict
7 from jtag
import JTAG
, resiotypes
8 from copy
import deepcopy
10 # Was thinking of using these functions, but skipped for simplicity for now
11 # XXX nope. the output from JSON file.
12 #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
13 # quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
14 # flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
16 # File for stage 1 pinmux tested proposed by Luke,
17 # https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
21 # sigh this needs to come from pinmux.
24 gpios
.append("%d*" % i
)
25 return {'uart': ['tx+', 'rx-'],
27 'i2c': ['sda*', 'scl+']}
30 a function is needed which turns the results of dummy_pinset()
33 [UARTResource("uart", 0, tx=..., rx=..),
34 I2CResource("i2c", 0, scl=..., sda=...),
35 Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
36 Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
42 def create_resources(pinset
):
44 for periph
, pins
in pinset
.items():
47 #print("I2C required!")
48 resources
.append(I2CResource('i2c', 0, sda
='sda', scl
='scl'))
49 elif periph
== 'uart':
50 #print("UART required!")
51 resources
.append(UARTResource('uart', 0, tx
='tx', rx
='rx'))
52 elif periph
== 'gpio':
53 #print("GPIO required!")
54 print ("GPIO is defined as '*' type, meaning i, o and oe needed")
57 pname
= "gpio"+pin
[:-1] # strip "*" on end
58 # urrrr... tristsate and io assume a single pin which is
59 # of course exactly what we don't want in an ASIC: we want
60 # *all three* pins but the damn port is not outputted
61 # as a triplet, it's a single Record named "io". sigh.
62 # therefore the only way to get a triplet of i/o/oe
63 # is to *actually* create explicit triple pins
65 Pins("%s_i %s_o %s_oe" % (pname
, pname
, pname
),
66 dir="io", assert_width
=3))
67 ios
.append(Resource(pname
, 0, pad
))
68 resources
.append(Resource
.family(periph
, 0, default_name
="gpio",
72 clk
= Resource("clk", 0, Pins("sys_clk", dir="i"))
73 rst
= Resource("rst", 0, Pins("sys_rst", dir="i"))
79 def UARTResource(*args
, rx
, tx
):
81 io
.append(Subsignal("rx", Pins(rx
, dir="i", assert_width
=1)))
82 io
.append(Subsignal("tx", Pins(tx
, dir="o", assert_width
=1)))
83 return Resource
.family(*args
, default_name
="uart", ios
=io
)
86 def I2CResource(*args
, scl
, sda
):
88 io
.append(Subsignal("scl", Pins(scl
, dir="io", assert_width
=1)))
89 io
.append(Subsignal("sda", Pins(sda
, dir="io", assert_width
=1)))
90 return Resource
.family(*args
, default_name
="i2c", ios
=io
)
93 # ridiculously-simple top-level module. doesn't even have a sync domain
94 # and can't have one until a clock has been established by ASICPlatform.
95 class Blinker(Elaboratable
):
96 def __init__(self
, pinset
):
97 self
.jtag
= JTAG({}, "sync")
99 def elaborate(self
, platform
):
101 m
.submodules
.jtag
= self
.jtag
103 m
.d
.sync
+= count
.eq(5)
104 print ("resources", platform
.resources
.items())
105 gpio
= platform
.request('gpio')
106 print (gpio
, gpio
.layout
, gpio
.fields
)
107 # get the GPIO bank, mess about with some of the pins
108 m
.d
.comb
+= gpio
.gpio0
.io
.o
.eq(1)
109 m
.d
.comb
+= gpio
.gpio1
.io
.o
.eq(gpio
.gpio2
.io
.i
)
110 m
.d
.comb
+= gpio
.gpio1
.io
.oe
.eq(count
[4])
111 m
.d
.sync
+= count
[0].eq(gpio
.gpio1
.io
.i
)
112 # get the UART resource, mess with the output tx
113 uart
= platform
.request('uart')
114 print (uart
, uart
.fields
)
115 intermediary
= Signal()
116 m
.d
.comb
+= uart
.tx
.eq(intermediary
)
117 m
.d
.comb
+= intermediary
.eq(uart
.rx
)
122 _trellis_command_templates = [
124 {{invoke_tool("yosys")}}
126 {{get_override("yosys_opts")|options}}
133 # sigh, have to create a dummy platform for now.
134 # TODO: investigate how the heck to get it to output ilang. or verilog.
135 # or, anything, really. but at least it doesn't barf
136 class ASICPlatform(TemplatedPlatform
):
138 resources
= OrderedDict()
140 command_templates
= ['/bin/true']
142 **TemplatedPlatform
.build_script_templates
,
147 "{{name}}.debug.v": r
"""
148 /* {{autogenerated}} */
149 {{emit_debug_verilog()}}
153 default_clk
= "clk" # should be picked up / overridden by platform sys.clk
154 default_rst
= "rst" # should be picked up / overridden by platform sys.rst
156 def __init__(self
, resources
, jtag
):
157 self
.pad_mgr
= ResourceManager([], [])
160 # create set of pin resources based on the pinset, this is for the core
161 self
.add_resources(resources
)
162 # record resource lookup between core IO names and pads
165 def request(self
, name
, number
=0, *, dir=None, xdr
=None):
166 """request a Resource (e.g. name="uart", number=0) which will
167 return a data structure containing Records of all the pins.
169 this override will also - automatically - create a JTAG Boundary Scan
170 connection *without* any change to the actual Platform.request() API
172 # okaaaay, bit of shenanigens going on: the important data structure
173 # here is Resourcemanager._ports. requests add to _ports, which is
174 # what needs redirecting. therefore what has to happen is to
175 # capture the number of ports *before* the request. sigh.
176 start_ports
= len(self
._ports
)
177 value
= super().request(name
, number
, dir=dir, xdr
=xdr
)
178 end_ports
= len(self
._ports
)
180 # now make a corresponding (duplicate) request to the pad manager
181 # BUT, if it doesn't exist, don't sweat it: all it means is, the
182 # application did not request Boundary Scan for that resource.
183 pad_start_ports
= len(self
.pad_mgr
._ports
)
185 pvalue
= self
.pad_mgr
.request(name
, number
, dir=dir, xdr
=xdr
)
186 except AssertionError:
188 pad_end_ports
= len(self
.pad_mgr
._ports
)
190 # ok now we have the lengths: now create a lookup between the pad
191 # and the core, so that JTAG boundary scan can be inserted in between
192 core
= self
._ports
[start_ports
:end_ports
]
193 pads
= self
.pad_mgr
._ports
[pad_start_ports
:pad_end_ports
]
194 # oops if not the same numbers added. it's a duplicate. shouldn't happen
195 assert len(core
) == len(pads
), "argh, resource manager error"
199 # pad/core each return a list of tuples of (res, pin, port, attrs)
200 for pad
, core
in zip(pads
, core
):
201 # create a lookup on pin name to get at the hidden pad instance
202 # this pin name will be handed to get_input, get_output etc.
203 # and without the padlookup you can't find the (duplicate) pad.
204 # note that self.padlookup and self.jtag.ios use the *exact* same
208 if pin
is None: continue # skip when pin is None
209 assert corepin
is not None # if pad was None, core should be too
210 print ("iter", pad
, pin
.name
)
211 print ("existing pads", self
.padlookup
.keys())
212 assert pin
.name
not in self
.padlookup
# no overwrites allowed!
213 assert pin
.name
== corepin
.name
# has to be the same!
214 self
.padlookup
[pin
.name
] = pad
# store pad by pin name
216 # now add the IO Shift Register. first identify the type
217 # then request a JTAG IOConn. we can't wire it up (yet) because
218 # we don't have a Module() instance. doh. that comes in get_input
219 # and get_output etc. etc.
220 iotype
= resiotypes
[pin
.dir] # look up the C4M-JTAG IOType
221 io
= self
.jtag
.add_io(iotype
=iotype
, name
=pin
.name
) # create IOConn
222 self
.jtag
.ios
[pin
.name
] = io
# store IOConn Record by pin name
224 # finally return the value just like ResourceManager.request()
227 def add_resources(self
, resources
, no_boundary_scan
=False):
228 super().add_resources(resources
)
231 # make a *second* - identical - set of pin resources for the IO ring
232 padres
= deepcopy(resources
)
233 self
.pad_mgr
.add_resources(padres
)
235 #def iter_ports(self):
236 # yield from super().iter_ports()
237 # for io in self.jtag.ios.values():
238 # print ("iter ports", io.layout, io)
239 # for field in io.core.fields:
240 # yield getattr(io.core, field)
241 # for field in io.pad.fields:
242 # yield getattr(io.pad, field)
244 # XXX these aren't strictly necessary right now but the next
245 # phase is to add JTAG Boundary Scan so it maaay be worth adding?
246 # at least for the print statements
247 def get_input(self
, pin
, port
, attrs
, invert
):
248 self
._check
_feature
("single-ended input", pin
, attrs
,
249 valid_xdrs
=(0,), valid_attrs
=None)
252 print (" get_input", pin
, "port", port
, port
.layout
)
253 if pin
.name
in ['clk_0', 'rst_0']: # sigh
254 # simple pass-through from port to pin
255 print("No JTAG chain in-between")
256 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
258 (padres
, padpin
, padport
, padattrs
) = self
.padlookup
[pin
.name
]
259 io
= self
.jtag
.ios
[pin
.name
]
260 print (" pad", padres
, padpin
, padport
, attrs
)
261 print (" padpin", padpin
.layout
)
262 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
263 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
264 m
.d
.comb
+= padpin
.i
.eq(padport
)
265 m
.d
.comb
+= padport
.io
.eq(io
.core
.i
)
266 m
.d
.comb
+= io
.pad
.i
.eq(pin
.i
)
268 print("+=+=+= pin: ", pin
)
269 print("+=+=+= port: ", port
.layout
)
270 print("+=+=+= pad pin: ", padpin
)
271 print("+=+=+= pad port: ", padport
)
274 def get_output(self
, pin
, port
, attrs
, invert
):
275 self
._check
_feature
("single-ended output", pin
, attrs
,
276 valid_xdrs
=(0,), valid_attrs
=None)
279 print (" get_output", pin
, "port", port
, port
.layout
)
280 if pin
.name
in ['clk_0', 'rst_0']: # sigh
281 # simple pass-through from pin to port
282 print("No JTAG chain in-between")
283 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
285 (padres
, padpin
, padport
, padattrs
) = self
.padlookup
[pin
.name
]
286 io
= self
.jtag
.ios
[pin
.name
]
287 print (" pad", padres
, padpin
, padport
, padattrs
)
288 print (" pin", padpin
.layout
)
289 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
290 m
.d
.comb
+= port
.eq(self
._invert
_if
(invert
, pin
.o
))
291 m
.d
.comb
+= padport
.io
.eq(self
._invert
_if
(invert
, padpin
.o
))
292 m
.d
.comb
+= io
.core
.o
.eq(port
.io
)
293 m
.d
.comb
+= padpin
.o
.eq(io
.pad
.o
)
296 def get_tristate(self
, pin
, port
, attrs
, invert
):
297 self
._check
_feature
("single-ended tristate", pin
, attrs
,
298 valid_xdrs
=(0,), valid_attrs
=None)
300 print (" get_tristate", pin
, "port", port
, port
.layout
)
302 if pin
.name
in ['clk_0', 'rst_0']: # sigh
303 print("No JTAG chain in-between")
304 m
.submodules
+= Instance("$tribuf",
307 i_A
=self
._invert
_if
(invert
, pin
.o
),
311 (res
, pin
, port
, attrs
) = self
.padlookup
[pin
.name
]
312 io
= self
.jtag
.ios
[pin
.name
]
313 print (" pad", res
, pin
, port
, attrs
)
314 print (" pin", pin
.layout
)
315 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
316 #m.submodules += Instance("$tribuf",
319 # i_A=self._invert_if(invert, io.pad.o),
322 m
.d
.comb
+= io
.core
.o
.eq(pin
.o
)
323 m
.d
.comb
+= io
.core
.oe
.eq(pin
.oe
)
324 m
.d
.comb
+= pin
.i
.eq(io
.core
.i
)
325 m
.d
.comb
+= io
.pad
.i
.eq(port
.i
)
326 m
.d
.comb
+= port
.o
.eq(io
.pad
.o
)
327 m
.d
.comb
+= port
.oe
.eq(io
.pad
.oe
)
330 def get_input_output(self
, pin
, port
, attrs
, invert
):
331 self
._check
_feature
("single-ended input/output", pin
, attrs
,
332 valid_xdrs
=(0,), valid_attrs
=None)
334 print (" get_input_output", pin
, "port", port
, port
.layout
)
336 if pin
.name
in ['clk_0', 'rst_0']: # sigh
337 print("No JTAG chain in-between")
338 m
.submodules
+= Instance("$tribuf",
341 i_A
=self
._invert
_if
(invert
, pin
.o
),
344 m
.d
.comb
+= pin
.i
.eq(self
._invert
_if
(invert
, port
))
346 (padres
, padpin
, padport
, padattrs
) = self
.padlookup
[pin
.name
]
347 io
= self
.jtag
.ios
[pin
.name
]
348 print (" pad", padres
, padpin
, padport
, padattrs
)
349 print (" pin", padpin
.layout
)
350 print (" port layout", port
.layout
)
351 print (" jtag", io
.core
.layout
, io
.pad
.layout
)
352 #m.submodules += Instance("$tribuf",
355 # i_A=self._invert_if(invert, io.pad.o),
358 # Create aliases for the port sub-signals
363 padport_i
= padport
.io
[0]
364 padport_o
= padport
.io
[1]
365 padport_oe
= padport
.io
[2]
367 # Connect SoC pins to SoC port
368 m
.d
.comb
+= pin
.i
.eq(port_i
)
369 m
.d
.comb
+= port_o
.eq(pin
.o
)
370 m
.d
.comb
+= port_oe
.eq(pin
.oe
)
371 # Connect SoC port to JTAG io.core side
372 m
.d
.comb
+= port_i
.eq(io
.core
.i
)
373 m
.d
.comb
+= io
.core
.o
.eq(port_o
)
374 m
.d
.comb
+= io
.core
.oe
.eq(port_oe
)
375 # Connect JTAG io.pad side to pad port
376 m
.d
.comb
+= io
.pad
.i
.eq(padport_i
)
377 m
.d
.comb
+= padport_o
.eq(io
.pad
.o
)
378 m
.d
.comb
+= padport_oe
.eq(io
.pad
.oe
)
379 # Connect pad port to pad pins
380 m
.d
.comb
+= padport_i
.eq(padpin
.i
)
381 m
.d
.comb
+= padpin
.o
.eq(padport_o
)
382 m
.d
.comb
+= padpin
.oe
.eq(padport_oe
)
387 and to create a Platform instance with that list, and build
391 p.resources=listofstuff
394 pinset
= dummy_pinset()
395 top
= Blinker(pinset
)
397 resources
= create_resources(pinset
)
398 p
= ASICPlatform (resources
, top
.jtag
)