Make the debug tests aware of multicore.
[riscv-tests.git] / debug / targets / RISC-V / spike32.py
1 import targets
2 import testlib
3
4 class spike32_hart(targets.Hart):
5 xlen = 32
6 ram = 0x10000000
7 ram_size = 0x10000000
8 instruction_hardware_breakpoint_count = 4
9 reset_vector = 0x1000
10 link_script_path = "spike64.lds"
11
12 class spike32(targets.Target):
13 harts = [spike32_hart()]
14 openocd_config_path = "spike.cfg"
15
16 def create(self):
17 return testlib.Spike(self)