src/peripherals/sdram/tb_bsv_wrapper.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package tb_bsv_wrapper;
  15
  16 import Semi_FIFOF        :: *;
  17 import AXI4_Types   :: *;
  18 import AXI4_Fabric  :: *;
  19 import bsvmksdram_model_wrapper :: *;
  20 import Connectable       :: *;
  21 `include "defined_parameters.bsv"
  22
  23 `define DELAY 10200
  24
  25    interface Ifc_tb_sdram_in;
  26
  27         method Action iAddr(Bit#(11) addr);
  28         method Action iBa(Bit#(2) ba);
  29         method Action iCke(bit cke);
  30         method Action iClk(bit clk);
  31         method Action iCs_n(bit cs_n);
  32         method Action iRas_n(bit ras_n);
  33         method Action iCas_n(bit cas_n);
  34         method Action iWe_n(bit we_n);
  35         method Action iDqm(Bit#(8) dqm);
  36
  37     endinterface
  38
  39 interface Ifc_tb_bsv_wrapper;
  40     interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) axi4_sdram;
  41     interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) axi4_cntrl_reg;
  42     interface Ifc_tb_sdram_in ifc_tb_sdram_in;
  43     interface Inout#(Bit#(32)) dq_0 ;
  44     interface Inout#(Bit#(32)) dq_1;
  45 endinterface
  46
  47
  48 module mktb_bsv_wrapper(Ifc_tb_bsv_wrapper);
  49
  50    Reg#(Bit#(9)) rg_burst_count <- mkReg(0);
  51    Reg#(bit) rg_tb_app_req <- mkReg(0);
  52    Reg#(bit) rg_tb_app_wr_n <- mkRegU();
  53    Reg#(Bit#(64))  rg_tb_app_req_addr <- mkReg(0);
  54    Reg#(Bit#(8))   rg_tb_app_req_len  <- mkReg(0);
  55    Reg#(Bit#(64))  rg_tb_wr_data <- mkReg(0);
  56    Reg#(Bit#(8))   rg_tb_wr_en_n <- mkReg(0);
  57    Reg#(Bit#(64))  rg_tb_rd_data <- mkReg(0);
  58    Reg#(Bit#(5))   rg_state_cnt  <- mkReg(0);
  59    Reg#(Bit#(64))  rg_tb_app_rd_addr <- mkReg(0);
  60    Reg#(Bit#(8))   rg_tb_app_rd_len  <- mkReg(0);
  61    Reg#(Bit#(16))  rg_delay_count <- mkReg(0);
  62    Reg#(bit)   rg_ff <- mkReg(0);
  63    Reg#(Bit#(2)) rg_bmode <- mkReg(0);
  64
  65    Reg#(Bit#(64)) rg_tb_cntrl_addr <- mkReg(0);
  66    Reg#(Bit#(64)) rg_tb_cntrl_data <- mkReg(4);
  67
  68    AXI4_Master_Xactor_IFC #(`PADDR,`Reg_width,`USERSPACE) m_xactor_sdram <- mkAXI4_Master_Xactor;
  69    AXI4_Master_Xactor_IFC #(`PADDR,`Reg_width,`USERSPACE) m_xactor_cntrl_reg <- mkAXI4_Master_Xactor;
  70
  71    Ifc_sdram_model sdram_model_0 <- mksdram_model_wrapper;
  72    Ifc_sdram_model sdram_model_1 <- mksdram_model_wrapper;
  73
  74    function Action burst_write(Bit#(64) address, Bit#(8) bl);
  75      return
  76      action
  77        rg_tb_app_req        <= 1;
  78        rg_tb_app_wr_n       <= 0;
  79        rg_tb_app_req_addr   <= address;
  80        rg_tb_app_req_len    <= bl;
  81
  82 //       for(Integer i = 0;i <= bl; i++) begin
  83        rg_tb_wr_en_n <= 8'hFF;
  84   //     end
  85       endaction;
  86   endfunction
  87
  88   function Action data_change(bit ff);
  89       return
  90       action
  91        if(ff == 1)
  92            rg_tb_wr_data <= 64'hDEADBEEFBABECAFE;
  93        else
  94            rg_tb_wr_data <= 64'hBABECAFEDEADBEEF;
  95
  96            rg_ff <= ~rg_ff;
  97
  98       endaction;
  99   endfunction
 100
 101
 102    function Action burst_read(Bit#(64) address, Bit#(8) bl);
 103        return
 104        action
 105        rg_tb_app_req        <= 1;
 106        rg_tb_app_wr_n       <= 1;
 107        rg_tb_app_rd_addr   <= address;
 108        rg_tb_app_rd_len    <= bl;
 109        endaction;
 110
 111     endfunction
 112
 113     function Action fn_send_cntrl_reg(Bit#(9) count);
 114         action
 115         case(count)
 116             0: begin
 117                 rg_tb_cntrl_addr <= 64'h00;
 118                 rg_tb_cntrl_data <= 64'h4;
 119             end
 120             1: begin
 121                 rg_tb_cntrl_addr <= 64'h08;
 122                 rg_tb_cntrl_data <= 64'h4;
 123             end
 124             2: begin
 125                 rg_tb_cntrl_addr <= 64'h10;
 126                 rg_tb_cntrl_data <= 64'h2;
 127             end
 128             3: begin
 129                 rg_tb_cntrl_addr <= 64'h18;
 130                 rg_tb_cntrl_data <= 64'h1;
 131             end
 132             4: begin
 133                 rg_tb_cntrl_addr <= 64'h20;
 134                 rg_tb_cntrl_data <= 64'h3;
 135             end
 136             5: begin
 137                 rg_tb_cntrl_addr <= 64'h28;
 138                 rg_tb_cntrl_data <= 64'h32;
 139             end
 140             6: begin
 141                 rg_tb_cntrl_addr <= 64'h30;
 142                 rg_tb_cntrl_data <= 64'h3;
 143             end
 144             7: begin
 145                 rg_tb_cntrl_addr <= 64'h38;
 146                 rg_tb_cntrl_data <= 64'h7;
 147             end
 148             8: begin
 149                 rg_tb_cntrl_addr <= 64'h40;
 150                 rg_tb_cntrl_data <= 64'h1;
 151             end
 152             9: begin
 153                 rg_tb_cntrl_addr <= 64'h48;
 154                 rg_tb_cntrl_data <= 64'h100;
 155             end
 156             10: begin
 157                 rg_tb_cntrl_addr <= 64'h50;
 158                 rg_tb_cntrl_data <= 64'h6;
 159             end
 160         endcase
 161     endaction
 162 endfunction
 163
 164
 165     rule rl_delay(rg_ff == 0 && rg_state_cnt == 0);
 166         if(rg_burst_count == 300)
 167             rg_ff <= 1;
 168         else
 169             rg_burst_count <= rg_burst_count + 1;
 170
 171         if(rg_burst_count <= 10) begin
 172             if(rg_burst_count == 0) begin
 173                 let aw = AXI4_Wr_Addr {awaddr: rg_tb_cntrl_addr, awprot:0, awuser:0, awlen: 10, awsize: 3, awburst: 'b01};
 174                 m_xactor_cntrl_reg.i_wr_addr.enq(aw);
 175             end
 176
 177             let w = AXI4_Wr_Data {wdata:  rg_tb_cntrl_data, wstrb: 8'h11, wlast: (rg_burst_count == 10)};
 178             m_xactor_cntrl_reg.i_wr_data.enq(w);
 179             fn_send_cntrl_reg(rg_burst_count + 1);
 180             $display("%d: Sending Control register info",$stime());
 181         end
 182     endrule
 183
 184     rule rl_response_from_cntrl_reg;
 185        let resp <- pop_o(m_xactor_cntrl_reg.o_wr_resp);
 186        $display("%d: Response from control reg bus %d",$stime(),(resp.bresp == AXI4_OKAY)? 1:0);
 187     endrule
 188
 189
 190
 191     rule rl_write_request(rg_state_cnt == 0 && rg_ff == 1);
 192         burst_write({32'b0,{8'd0,11'h0,2'b00,8'd0,3'b0}}, 8'd255);
 193         rg_state_cnt <= rg_state_cnt + 1;
 194         rg_burst_count <= 0;
 195     endrule
 196
 197     rule rl_read_request_gen(rg_state_cnt == 15);
 198         burst_read({32'b0,{8'd0,11'd0,2'b00,8'hA,3'b000}}, 8'd7);
 199         rg_state_cnt <= rg_state_cnt + 1;
 200         rg_bmode <= 'b01;
 201         rg_burst_count <= 0;
 202     endrule
 203
 204    rule rl_iapp_req_ack_connection(rg_state_cnt == 2 || rg_state_cnt == 5 || rg_state_cnt == 8 || rg_state_cnt == 11 || rg_state_cnt == 14 || rg_state_cnt == 27);
 205        let resp <- pop_o(m_xactor_sdram.o_wr_resp);
 206        $display("%d: Response from write bus %d",$stime(),(resp.bresp == AXI4_OKAY)? 1:0);
 207        rg_state_cnt <= rg_state_cnt + 1;
 208 //       $finish();
 209 //       tb_core.iapp_req_ack((resp.bresp == AXI4_OKAY)? 1:0 );
 210    endrule
 211
 212     rule rl_oapp_wr_data(rg_state_cnt == 1 || rg_state_cnt == 4 || rg_state_cnt == 7 || rg_state_cnt == 10 || rg_state_cnt == 13 || rg_state_cnt == 26);
 213         if(rg_tb_app_req_len == 0) begin
 214            let aw = AXI4_Wr_Addr {awaddr: rg_tb_app_req_addr, awprot:0, awuser:0, awlen: extend(rg_tb_app_req_len), awsize: 2, awburst: 'b01};
 215            let w = AXI4_Wr_Data {wdata:  64'hDEADBEEFBABECAFE, wstrb: rg_tb_wr_en_n, wlast: True};
 216         m_xactor_sdram.i_wr_addr.enq(aw);
 217         m_xactor_sdram.i_wr_data.enq(w);
 218         $display("%d: Sending write request",$stime());
 219         end
 220         else begin
 221             if(rg_burst_count == 0) begin
 222                 let aw = AXI4_Wr_Addr {awaddr: rg_tb_app_req_addr, awprot:0, awuser: 0, awlen: extend(rg_tb_app_req_len), awsize: 2, awburst: 'b01};
 223                 let w = AXI4_Wr_Data {wdata:  64'hDEADBEEFBABECAFE, wstrb: rg_tb_wr_en_n, wlast: False};
 224                 data_change(rg_ff);
 225                 rg_burst_count <= rg_burst_count + 1;
 226                 m_xactor_sdram.i_wr_addr.enq(aw);
 227                 m_xactor_sdram.i_wr_data.enq(w);
 228
 229             end
 230             else if(rg_burst_count <= extend(rg_tb_app_req_len) && rg_burst_count != 0) begin
 231                 let w = AXI4_Wr_Data {wdata:  rg_tb_wr_data, wstrb: rg_tb_wr_en_n, wlast: (rg_burst_count == extend(rg_tb_app_req_len))};
 232                 rg_burst_count <= rg_burst_count + 1;
 233                 $display("%d: Sending write data %x rg_ff %b",$stime(),rg_tb_wr_data, rg_ff);
 234                 data_change(rg_ff);
 235                 m_xactor_sdram.i_wr_data.enq(w);
 236                 //tb_core.iapp_last_wr(pack(rg_burst_count == tb_core.oapp_req_len));
 237             end
 238             else begin
 239                 rg_burst_count <= 0;
 240                 rg_state_cnt <= rg_state_cnt + 1;
 241             end
 242         end
 243    endrule
 244
 245    rule rl_next_write(rg_state_cnt == 3);
 246         burst_write({32'b0,{8'd0,11'd1500,2'b01,8'd56,3'b0}}, 8'd246);
 247         rg_state_cnt <= rg_state_cnt + 1;
 248         rg_burst_count <= 0;
 249     endrule
 250
 251    rule rl_next_write1(rg_state_cnt == 6);
 252         burst_write({32'b0,{8'd0,11'd2010,2'b01,8'd25,3'b0}}, 8'd7);
 253         rg_state_cnt <= rg_state_cnt + 1;
 254         rg_burst_count <= 0;
 255     endrule
 256
 257    rule rl_next_write2(rg_state_cnt == 9);
 258         burst_write({32'b0,{8'd0,11'd1600,2'b10,8'd55,3'b0}}, 8'd4);
 259         rg_state_cnt <= rg_state_cnt + 1;
 260         rg_burst_count <= 0;
 261     endrule
 262
 263    rule rl_next_write3(rg_state_cnt == 12);
 264         burst_write({32'b0,{8'd0,11'h8,2'b0,8'd5,3'b0}}, 8'd3);
 265         rg_state_cnt <= rg_state_cnt + 1;
 266         rg_burst_count <= 0;
 267     endrule
 268
 269    rule rl_next_write4(rg_state_cnt == 20);
 270         burst_write({32'b0,{8'd0,11'h8,2'b01,8'd255,3'b0}}, 8'd2);
 271         rg_state_cnt <= rg_state_cnt + 1;
 272         rg_burst_count <= 0;
 273     endrule
 274
 275    rule rl_read_request(rg_state_cnt == 16 || rg_state_cnt == 19);
 276        let read_request = AXI4_Rd_Addr {araddr: rg_tb_app_rd_addr, arprot: 0, aruser: 0, arlen: extend(rg_tb_app_rd_len), arsize: 3, arburst: rg_bmode}; // arburst: 00-FIXED 01-INCR 10-WRAP
 277        m_xactor_sdram.i_rd_addr.enq(read_request);
 278        $display("%d: Sending read request",$stime());
 279        rg_state_cnt <= rg_state_cnt + 1;
 280    endrule
 281
 282    rule rl_read_response(rg_state_cnt == 17 || rg_state_cnt == 20);
 283        if(rg_burst_count == 300) begin
 284            let response <- pop_o(m_xactor_sdram.o_rd_data);
 285            rg_tb_rd_data <= response.rdata;
 286            $display("%d: Read data %x",$stime(),response.rdata);
 287            rg_tb_app_rd_len <= rg_tb_app_rd_len - 1;
 288            if(rg_tb_app_rd_len == 0)
 289                rg_state_cnt <= rg_state_cnt + 1;
 290        end
 291        else rg_burst_count <= rg_burst_count + 1;
 292    endrule
 293
 294     rule rl_read_request_gen1(rg_state_cnt == 18);
 295         burst_read({32'b0,{8'd0,11'd0,2'b00,8'hA,3'b000}}, 8'd3);
 296         rg_bmode <= 'b10;
 297         rg_state_cnt <= rg_state_cnt + 1;
 298         rg_burst_count <= 0;
 299     endrule
 300
 301
 302
 303    interface dq_0 = sdram_model_0.dq;
 304    interface dq_1 = sdram_model_1.dq;
 305
 306    interface Ifc_tb_sdram_in ifc_tb_sdram_in;
 307
 308 //       interface Inout#(Bit#(32)) dq = tb_core.sdr_dq;
 309
 310         method Action iAddr(Bit#(11) addr);
 311             sdram_model_0.iAddr(addr);
 312             sdram_model_1.iAddr(addr);
 313         endmethod
 314
 315         method Action iBa(Bit#(2) ba);
 316             sdram_model_0.iBa(ba);
 317             sdram_model_1.iBa(ba);
 318         endmethod
 319
 320         method Action iCke(bit cke);
 321             sdram_model_0.iCke(cke);
 322             sdram_model_1.iCke(cke);
 323         endmethod
 324
 325         method Action iClk(bit clk);
 326             sdram_model_0.iClk(clk);
 327             sdram_model_1.iClk(clk);
 328         endmethod
 329
 330         method Action iCs_n(bit cs_n);
 331             sdram_model_0.iCs_n(cs_n);
 332             sdram_model_1.iCs_n(cs_n);
 333         endmethod
 334
 335         method Action iRas_n(bit ras_n);
 336             sdram_model_0.iRas_n(ras_n);
 337             sdram_model_1.iRas_n(ras_n);
 338         endmethod
 339
 340         method Action iCas_n(bit cas_n);
 341             sdram_model_0.iCas_n(cas_n);
 342             sdram_model_1.iCas_n(cas_n);
 343         endmethod
 344
 345         method Action iWe_n(bit we_n);
 346             sdram_model_0.iWe_n(we_n);
 347             sdram_model_1.iWe_n(we_n);
 348         endmethod
 349
 350         method Action iDqm(Bit#(8) dqm);
 351             sdram_model_0.iDqm(dqm[3:0]);
 352             sdram_model_1.iDqm(dqm[7:4]);
 353         endmethod
 354
 355     endinterface
 356
 357    interface axi4_sdram = m_xactor_sdram.axi_side;
 358    interface axi4_cntrl_reg = m_xactor_cntrl_reg.axi_side;
 359
 360 endmodule
 361 endpackage
 362
 363
 364
 365